2 % (c) The AQUA Project, Glasgow University, 1996-1998
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "nativeGen/NCG.h"
45 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh
48 , eax, ebx, ecx, edx, esi, esp
49 , st0, st1, st2, st3, st4, st5, st6, st7
54 , fPair, fpRel, gReg, iReg, lReg, oReg, largeOffsetError
60 #include "HsVersions.h"
62 import AbsCSyn ( MagicId(..) )
63 import AbsCUtils ( magicIdPrimRep )
64 import CLabel ( CLabel )
65 import PrimOp ( PrimOp(..) )
66 import PrimRep ( PrimRep(..) )
67 import Stix ( sStLitLbl, StixTree(..), StixReg(..) )
68 import Unique ( mkPseudoUnique1, mkPseudoUnique2, mkPseudoUnique3,
71 import UniqSupply ( getUniqueUs, returnUs, thenUs, UniqSM )
75 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
80 | ImmInteger Integer -- Sigh.
81 | ImmCLbl CLabel -- AbstractC Label (with baggage)
82 | ImmLab SDoc -- Simple string label (underscore-able)
83 | ImmLit SDoc -- Simple string
87 | LO Imm -- Possible restrictions...
90 strImmLit s = ImmLit (text s)
93 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
104 = AddrBaseIndex Base Index Displacement
107 type Base = Maybe Reg
108 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
109 type Displacement = Imm
112 #if sparc_TARGET_ARCH
117 addrOffset :: MachRegsAddr -> Int -> Maybe MachRegsAddr
121 #if alpha_TARGET_ARCH
122 _ -> panic "MachMisc.addrOffset not defined for Alpha"
125 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
126 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
127 AddrBaseIndex r i (ImmInteger n)
128 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
131 #if sparc_TARGET_ARCH
132 AddrRegImm r (ImmInt n)
133 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
134 | otherwise -> Nothing
137 AddrRegImm r (ImmInteger n)
138 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
139 | otherwise -> Nothing
140 where n2 = n + toInteger off
142 AddrRegReg r (FixedReg ILIT(0))
143 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
144 | otherwise -> Nothing
151 #if alpha_TARGET_ARCH
153 fits8Bits :: Integer -> Bool
154 fits8Bits i = i >= -256 && i < 256
158 #if sparc_TARGET_ARCH
160 fits13Bits :: Int -> Bool
163 fits13Bits :: Integer -> Bool
166 fits13Bits :: Integral a => a -> Bool
167 fits13Bits x = x >= -4096 && x < 4096
171 = error ("ERROR: SPARC native-code generator cannot handle large offset ("++show i++");\nprobably because of large constant data structures;\nworkaround: use -fvia-C on this module.\n")
176 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
178 @stgReg@: we map STG registers onto appropriate Stix Trees. First, we
179 handle the two constants, @STK_STUB_closure@ and @vtbl_StdUpdFrame@.
180 The rest are either in real machine registers or stored as offsets
184 data RegLoc = Save StixTree | Always StixTree
187 Trees for register save locations:
189 saveLoc :: MagicId -> StixTree
191 saveLoc reg = case (stgReg reg) of {Always loc -> loc; Save loc -> loc}
195 stgReg :: MagicId -> RegLoc
198 = case (magicIdRegMaybe x) of
199 Just _ -> Save nonReg
200 Nothing -> Always nonReg
202 offset = baseRegOffset x
204 baseLoc = case (magicIdRegMaybe BaseReg) of
205 Just _ -> StReg (StixMagicId BaseReg)
206 Nothing -> sStLitLbl SLIT("MainRegTable")
209 BaseReg -> sStLitLbl SLIT("MainRegTable")
211 _ -> StInd (magicIdPrimRep x)
212 (StPrim IntAddOp [baseLoc,
213 StInt (toInteger (offset*BYTES_PER_WORD))])
216 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
218 @spRel@ gives us a stack relative addressing mode for volatile
219 temporaries and for excess call arguments. @fpRel@, where
220 applicable, is the same but for the frame pointer.
223 spRel :: Int -- desired stack offset in words, positive or negative
228 = AddrBaseIndex (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
230 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
233 #if sparc_TARGET_ARCH
234 fpRel :: Int -> MachRegsAddr
235 -- Duznae work for offsets greater than 13 bits; we just hope for
238 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
242 %************************************************************************
244 \subsection[Reg]{Real registers}
246 %************************************************************************
248 Static Registers correspond to actual machine registers. These should
249 be avoided until the last possible moment.
251 Dynamic registers are allocated on the fly, usually to represent a single
252 value in the abstract assembly code (i.e. dynamic registers are usually
253 single assignment). Ultimately, they are mapped to available machine
254 registers before spitting out the code.
258 = FixedReg FAST_INT -- A pre-allocated machine register
260 | MappedReg FAST_INT -- A dynamically allocated machine register
262 | MemoryReg Int PrimRep -- A machine "register" actually held in
263 -- a memory allocated table of
264 -- registers which didn't fit in real
267 | UnmappedReg Unique PrimRep -- One of an infinite supply of registers,
268 -- always mapped to one of the earlier
269 -- two (?) before we're done.
270 mkReg :: Unique -> PrimRep -> Reg
273 getNewRegNCG :: PrimRep -> UniqSM Reg
275 = getUniqueUs `thenUs` \ u ->
276 returnUs (UnmappedReg u pk)
278 instance Text Reg where
279 showsPrec _ (FixedReg i) = showString "%" . shows IBOX(i)
280 showsPrec _ (MappedReg i) = showString "%" . shows IBOX(i)
281 showsPrec _ (MemoryReg i _) = showString "%M" . shows i
282 showsPrec _ (UnmappedReg i _) = showString "%U" . shows i
285 instance Outputable Reg where
286 ppr r = text (show r)
289 cmpReg (FixedReg i) (FixedReg i') = cmp_ihash i i'
290 cmpReg (MappedReg i) (MappedReg i') = cmp_ihash i i'
291 cmpReg (MemoryReg i _) (MemoryReg i' _) = i `compare` i'
292 cmpReg (UnmappedReg u _) (UnmappedReg u' _) = compare u u'
294 = let tag1 = tagReg r1
297 if tag1 _LT_ tag2 then LT else GT
299 tagReg (FixedReg _) = (ILIT(1) :: FAST_INT)
300 tagReg (MappedReg _) = ILIT(2)
301 tagReg (MemoryReg _ _) = ILIT(3)
302 tagReg (UnmappedReg _ _) = ILIT(4)
304 cmp_ihash :: FAST_INT -> FAST_INT -> Ordering
305 cmp_ihash a1 a2 = if a1 _EQ_ a2 then EQ else if a1 _LT_ a2 then LT else GT
307 instance Eq Reg where
308 a == b = case (a `compare` b) of { EQ -> True; _ -> False }
309 a /= b = case (a `compare` b) of { EQ -> False; _ -> True }
311 instance Ord Reg where
312 a <= b = case (a `compare` b) of { LT -> True; EQ -> True; GT -> False }
313 a < b = case (a `compare` b) of { LT -> True; EQ -> False; GT -> False }
314 a >= b = case (a `compare` b) of { LT -> False; EQ -> True; GT -> True }
315 a > b = case (a `compare` b) of { LT -> False; EQ -> False; GT -> True }
316 compare a b = cmpReg a b
318 instance Uniquable Reg where
319 getUnique (UnmappedReg u _) = u
320 getUnique (FixedReg i) = mkPseudoUnique1 IBOX(i)
321 getUnique (MappedReg i) = mkPseudoUnique2 IBOX(i)
322 getUnique (MemoryReg i _) = mkPseudoUnique3 i
328 realReg :: RegNo -> Reg
330 = if _IS_TRUE_(freeReg i) then MappedReg i else FixedReg i
332 extractMappedRegNos :: [Reg] -> [RegNo]
334 extractMappedRegNos regs
337 ex (MappedReg i) acc = IBOX(i) : acc -- we'll take it
338 ex _ acc = acc -- leave it out
341 ** Machine-specific Reg stuff: **
343 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
344 point registers. The mapping of STG registers to alpha machine registers
345 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
347 #if alpha_TARGET_ARCH
351 v0, f0, ra, pv, gp, sp, zeroh :: Reg
353 f0 = realReg (fReg 0)
354 ra = FixedReg ILIT(26)
356 gp = FixedReg ILIT(29)
357 sp = FixedReg ILIT(30)
358 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
360 t9, t10, t11, t12 :: Reg
368 Intel x86 architecture:
369 - All registers except 7 (esp) are available for use.
370 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
371 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
372 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
373 - Registers 8-15 hold extended floating point values.
377 gReg,fReg :: Int -> Int
381 st0, st1, st2, st3, st4, st5, st6, st7, eax, ebx, ecx, edx, esp :: Reg
382 eax = realReg (gReg 0)
383 ebx = realReg (gReg 1)
384 ecx = realReg (gReg 2)
385 edx = realReg (gReg 3)
386 esi = realReg (gReg 4)
387 edi = realReg (gReg 5)
388 ebp = realReg (gReg 6)
389 esp = realReg (gReg 7)
390 st0 = realReg (fReg 0)
391 st1 = realReg (fReg 1)
392 st2 = realReg (fReg 2)
393 st3 = realReg (fReg 3)
394 st4 = realReg (fReg 4)
395 st5 = realReg (fReg 5)
396 st6 = realReg (fReg 6)
397 st7 = realReg (fReg 7)
402 The SPARC has 64 registers of interest; 32 integer registers and 32
403 floating point registers. The mapping of STG registers to SPARC
404 machine registers is defined in StgRegs.h. We are, of course,
405 prepared for any eventuality.
408 #if sparc_TARGET_ARCH
410 gReg,lReg,iReg,oReg,fReg :: Int -> Int
418 fPair (FixedReg i) = FixedReg (i _ADD_ ILIT(1))
419 fPair (MappedReg i) = MappedReg (i _ADD_ ILIT(1))
421 g0, fp, sp, o0, f0 :: Reg
422 g0 = case (gReg 0) of { IBOX(g0) -> FixedReg g0 }
423 fp = case (iReg 6) of { IBOX(i6) -> FixedReg i6 }
424 sp = case (oReg 6) of { IBOX(o6) -> FixedReg o6 }
425 o0 = realReg (oReg 0)
426 f0 = realReg (fReg 0)
431 Redefine the literals used for machine-registers with non-numeric
432 names in the header files. Gag me with a spoon, eh?
434 #if alpha_TARGET_ARCH
486 #if sparc_TARGET_ARCH
555 baseRegOffset :: MagicId -> Int
557 baseRegOffset (VanillaReg _ ILIT(1)) = OFFSET_R1
558 baseRegOffset (VanillaReg _ ILIT(2)) = OFFSET_R2
559 baseRegOffset (VanillaReg _ ILIT(3)) = OFFSET_R3
560 baseRegOffset (VanillaReg _ ILIT(4)) = OFFSET_R4
561 baseRegOffset (VanillaReg _ ILIT(5)) = OFFSET_R5
562 baseRegOffset (VanillaReg _ ILIT(6)) = OFFSET_R6
563 baseRegOffset (VanillaReg _ ILIT(7)) = OFFSET_R7
564 baseRegOffset (VanillaReg _ ILIT(8)) = OFFSET_R8
565 baseRegOffset (FloatReg ILIT(1)) = OFFSET_F1
566 baseRegOffset (FloatReg ILIT(2)) = OFFSET_F2
567 baseRegOffset (FloatReg ILIT(3)) = OFFSET_F3
568 baseRegOffset (FloatReg ILIT(4)) = OFFSET_F4
569 baseRegOffset (DoubleReg ILIT(1)) = OFFSET_D1
570 baseRegOffset (DoubleReg ILIT(2)) = OFFSET_D2
571 baseRegOffset Sp = OFFSET_Sp
572 baseRegOffset Su = OFFSET_Su
573 baseRegOffset SpLim = OFFSET_SpLim
575 baseRegOffset (LongReg _ ILIT(1)) = OFFSET_Lng1
578 baseRegOffset (LongReg _ ILIT(2)) = OFFSET_Lng2
580 baseRegOffset Hp = OFFSET_Hp
581 baseRegOffset HpLim = OFFSET_HpLim
583 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
584 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
585 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
590 callerSaves :: MagicId -> Bool
592 #ifdef CALLER_SAVES_Base
593 callerSaves BaseReg = True
595 #ifdef CALLER_SAVES_R1
596 callerSaves (VanillaReg _ ILIT(1)) = True
598 #ifdef CALLER_SAVES_R2
599 callerSaves (VanillaReg _ ILIT(2)) = True
601 #ifdef CALLER_SAVES_R3
602 callerSaves (VanillaReg _ ILIT(3)) = True
604 #ifdef CALLER_SAVES_R4
605 callerSaves (VanillaReg _ ILIT(4)) = True
607 #ifdef CALLER_SAVES_R5
608 callerSaves (VanillaReg _ ILIT(5)) = True
610 #ifdef CALLER_SAVES_R6
611 callerSaves (VanillaReg _ ILIT(6)) = True
613 #ifdef CALLER_SAVES_R7
614 callerSaves (VanillaReg _ ILIT(7)) = True
616 #ifdef CALLER_SAVES_R8
617 callerSaves (VanillaReg _ ILIT(8)) = True
619 #ifdef CALLER_SAVES_F1
620 callerSaves (FloatReg ILIT(1)) = True
622 #ifdef CALLER_SAVES_F2
623 callerSaves (FloatReg ILIT(2)) = True
625 #ifdef CALLER_SAVES_F3
626 callerSaves (FloatReg ILIT(3)) = True
628 #ifdef CALLER_SAVES_F4
629 callerSaves (FloatReg ILIT(4)) = True
631 #ifdef CALLER_SAVES_D1
632 callerSaves (DoubleReg ILIT(1)) = True
634 #ifdef CALLER_SAVES_D2
635 callerSaves (DoubleReg ILIT(2)) = True
637 #ifdef CALLER_SAVES_L1
638 callerSaves (LongReg _ ILIT(1)) = True
640 #ifdef CALLER_SAVES_Sp
641 callerSaves Sp = True
643 #ifdef CALLER_SAVES_Su
644 callerSaves Su = True
646 #ifdef CALLER_SAVES_SpLim
647 callerSaves SpLim = True
649 #ifdef CALLER_SAVES_Hp
650 callerSaves Hp = True
652 #ifdef CALLER_SAVES_HpLim
653 callerSaves HpLim = True
655 callerSaves _ = False
659 magicIdRegMaybe :: MagicId -> Maybe Reg
662 magicIdRegMaybe BaseReg = Just (FixedReg ILIT(REG_Base))
665 magicIdRegMaybe (VanillaReg _ ILIT(1)) = Just (FixedReg ILIT(REG_R1))
668 magicIdRegMaybe (VanillaReg _ ILIT(2)) = Just (FixedReg ILIT(REG_R2))
671 magicIdRegMaybe (VanillaReg _ ILIT(3)) = Just (FixedReg ILIT(REG_R3))
674 magicIdRegMaybe (VanillaReg _ ILIT(4)) = Just (FixedReg ILIT(REG_R4))
677 magicIdRegMaybe (VanillaReg _ ILIT(5)) = Just (FixedReg ILIT(REG_R5))
680 magicIdRegMaybe (VanillaReg _ ILIT(6)) = Just (FixedReg ILIT(REG_R6))
683 magicIdRegMaybe (VanillaReg _ ILIT(7)) = Just (FixedReg ILIT(REG_R7))
686 magicIdRegMaybe (VanillaReg _ ILIT(8)) = Just (FixedReg ILIT(REG_R8))
689 magicIdRegMaybe (FloatReg ILIT(1)) = Just (FixedReg ILIT(REG_F1))
692 magicIdRegMaybe (FloatReg ILIT(2)) = Just (FixedReg ILIT(REG_F2))
695 magicIdRegMaybe (FloatReg ILIT(3)) = Just (FixedReg ILIT(REG_F3))
698 magicIdRegMaybe (FloatReg ILIT(4)) = Just (FixedReg ILIT(REG_F4))
701 magicIdRegMaybe (DoubleReg ILIT(1)) = Just (FixedReg ILIT(REG_D1))
704 magicIdRegMaybe (DoubleReg ILIT(2)) = Just (FixedReg ILIT(REG_D2))
707 magicIdRegMaybe Sp = Just (FixedReg ILIT(REG_Sp))
710 magicIdRegMaybe (LongReg _ ILIT(1)) = Just (FixedReg ILIT(REG_Lng1))
713 magicIdRegMaybe (LongReg _ ILIT(2)) = Just (FixedReg ILIT(REG_Lng2))
716 magicIdRegMaybe Su = Just (FixedReg ILIT(REG_Su))
719 magicIdRegMaybe SpLim = Just (FixedReg ILIT(REG_SpLim))
722 magicIdRegMaybe Hp = Just (FixedReg ILIT(REG_Hp))
725 magicIdRegMaybe HpLim = Just (FixedReg ILIT(REG_HpLim))
727 magicIdRegMaybe _ = Nothing
730 %************************************************************************
732 \subsection{Free, reserved, call-clobbered, and argument registers}
734 %************************************************************************
736 @freeRegs@ is the list of registers we can use in register allocation.
737 @freeReg@ (below) says if a particular register is free.
739 With a per-instruction clobber list, we might be able to get some of
740 these back, but it's probably not worth the hassle.
742 @callClobberedRegs@ ... the obvious.
744 @argRegs@: assuming a call with N arguments, what registers will be
745 used to hold arguments? (NB: it doesn't know whether the arguments
746 are integer or floating-point...)
749 reservedRegs :: [RegNo]
751 #if alpha_TARGET_ARCH
752 = [NCG_Reserved_I1, NCG_Reserved_I2,
753 NCG_Reserved_F1, NCG_Reserved_F2]
756 = [{-certainly cannot afford any!-}]
758 #if sparc_TARGET_ARCH
759 = [NCG_Reserved_I1, NCG_Reserved_I2,
760 NCG_Reserved_F1, NCG_Reserved_F2,
761 NCG_Reserved_D1, NCG_Reserved_D2]
764 -------------------------------
767 = freeMappedRegs IF_ARCH_alpha( [0..63],
768 IF_ARCH_i386( [0..15],
769 IF_ARCH_sparc( [0..63],)))
771 -------------------------------
772 callClobberedRegs :: [Reg]
775 #if alpha_TARGET_ARCH
776 [0, 1, 2, 3, 4, 5, 6, 7, 8,
777 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
778 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
779 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
780 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
781 #endif {- alpha_TARGET_ARCH -}
784 #endif {- i386_TARGET_ARCH -}
785 #if sparc_TARGET_ARCH
787 [oReg i | i <- [0..5]] ++
788 [gReg i | i <- [1..7]] ++
789 [fReg i | i <- [0..31]] )
790 #endif {- sparc_TARGET_ARCH -}
792 -------------------------------
793 argRegs :: Int -> [Reg]
797 argRegs _ = panic "MachRegs.argRegs: doesn't work on I386"
799 #if alpha_TARGET_ARCH
800 argRegs 1 = freeMappedRegs [16, fReg 16]
801 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
802 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
803 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
804 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
805 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
806 #endif {- alpha_TARGET_ARCH -}
807 #if sparc_TARGET_ARCH
808 argRegs 1 = freeMappedRegs (map oReg [0])
809 argRegs 2 = freeMappedRegs (map oReg [0,1])
810 argRegs 3 = freeMappedRegs (map oReg [0,1,2])
811 argRegs 4 = freeMappedRegs (map oReg [0,1,2,3])
812 argRegs 5 = freeMappedRegs (map oReg [0,1,2,3,4])
813 argRegs 6 = freeMappedRegs (map oReg [0,1,2,3,4,5])
814 #endif {- sparc_TARGET_ARCH -}
815 argRegs _ = panic "MachRegs.argRegs: don't know about >6 arguments!"
816 #endif {- i386_TARGET_ARCH -}
818 -------------------------------
820 #if alpha_TARGET_ARCH
821 allArgRegs :: [(Reg, Reg)]
823 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
824 #endif {- alpha_TARGET_ARCH -}
826 #if sparc_TARGET_ARCH
829 allArgRegs = map realReg [oReg i | i <- [0..5]]
830 #endif {- sparc_TARGET_ARCH -}
832 -------------------------------
833 freeMappedRegs :: [Int] -> [Reg]
839 = if _IS_TRUE_(freeReg i) then (MappedReg i) : acc else acc
843 freeReg :: FAST_INT -> FAST_BOOL
845 #if alpha_TARGET_ARCH
846 freeReg ILIT(26) = _FALSE_ -- return address (ra)
847 freeReg ILIT(28) = _FALSE_ -- reserved for the assembler (at)
848 freeReg ILIT(29) = _FALSE_ -- global pointer (gp)
849 freeReg ILIT(30) = _FALSE_ -- stack pointer (sp)
850 freeReg ILIT(31) = _FALSE_ -- always zero (zeroh)
851 freeReg ILIT(63) = _FALSE_ -- always zero (f31)
855 freeReg ILIT(esp) = _FALSE_ -- %esp is the C stack pointer
858 #if sparc_TARGET_ARCH
859 freeReg ILIT(g0) = _FALSE_ -- %g0 is always 0.
860 freeReg ILIT(g5) = _FALSE_ -- %g5 is reserved (ABI).
861 freeReg ILIT(g6) = _FALSE_ -- %g6 is reserved (ABI).
862 freeReg ILIT(g7) = _FALSE_ -- %g7 is reserved (ABI).
863 freeReg ILIT(i6) = _FALSE_ -- %i6 is our frame pointer.
864 freeReg ILIT(o6) = _FALSE_ -- %o6 is our stack pointer.
868 freeReg ILIT(REG_Base) = _FALSE_
871 freeReg ILIT(REG_R1) = _FALSE_
874 freeReg ILIT(REG_R2) = _FALSE_
877 freeReg ILIT(REG_R3) = _FALSE_
880 freeReg ILIT(REG_R4) = _FALSE_
883 freeReg ILIT(REG_R5) = _FALSE_
886 freeReg ILIT(REG_R6) = _FALSE_
889 freeReg ILIT(REG_R7) = _FALSE_
892 freeReg ILIT(REG_R8) = _FALSE_
895 freeReg ILIT(REG_F1) = _FALSE_
898 freeReg ILIT(REG_F2) = _FALSE_
901 freeReg ILIT(REG_F3) = _FALSE_
904 freeReg ILIT(REG_F4) = _FALSE_
907 freeReg ILIT(REG_D1) = _FALSE_
910 freeReg ILIT(REG_D2) = _FALSE_
913 freeReg ILIT(REG_Sp) = _FALSE_
916 freeReg ILIT(REG_Su) = _FALSE_
919 freeReg ILIT(REG_SpLim) = _FALSE_
922 freeReg ILIT(REG_Hp) = _FALSE_
925 freeReg ILIT(REG_HpLim) = _FALSE_
928 -- we hang onto two double regs for dedicated
929 -- use; this is not necessary on Alphas and
930 -- may not be on other non-SPARCs.
932 | n _EQ_ (ILIT(REG_D1) _ADD_ ILIT(1)) = _FALSE_
935 | n _EQ_ (ILIT(REG_D2) _ADD_ ILIT(1)) = _FALSE_