2 % (c) The AQUA Project, Glasgow University, 1996-1998
4 \section[MachRegs]{Machine-specific info about registers}
6 Also includes stuff about immediate operands, which are
7 often/usually quite entangled with registers.
9 (Immediates could be untangled from registers at some cost in tangled
10 modules --- the pleasure has been foregone.)
13 #include "nativeGen/NCG.h"
17 RegClass(..), regClass,
18 VRegUnique(..), pprVRegUnique, getHiVRegFromLo,
19 Reg(..), isRealReg, isVirtualReg, getVRegUnique,
20 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
31 get_MagicId_reg_or_addr,
33 get_Regtable_addr_from_offset,
41 , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh
44 , eax, ebx, ecx, edx, esi, esp
45 , fake0, fake1, fake2, fake3, fake4, fake5
49 , fpRel, gReg, iReg, lReg, oReg, largeOffsetError
50 , fp, sp, g0, g1, g2, o0, f0, f6, f8, f26, f27
55 #include "HsVersions.h"
57 import AbsCSyn ( MagicId(..) )
58 import CLabel ( CLabel, mkMainRegTableLabel )
59 import MachOp ( MachOp(..) )
60 import PrimRep ( PrimRep(..), isFloatingRep )
61 import Stix ( StixExpr(..), StixReg(..),
62 getUniqueNat, returnNat, thenNat, NatM )
63 import Unique ( mkPseudoUnique2, Uniquable(..), Unique )
65 import Outputable ( Outputable(..), pprPanic, panic )
66 import qualified Outputable
70 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
75 | ImmInteger Integer -- Sigh.
76 | ImmCLbl CLabel -- AbstractC Label (with baggage)
77 | ImmLab Bool Doc -- Simple string label (underscore-able)
78 -- Bool==True ==> in a different DLL
79 | ImmLit Doc -- Simple string
84 | LO Imm -- Possible restrictions...
87 strImmLit s = ImmLit (text s)
90 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
101 = AddrBaseIndex Base Index Displacement
104 type Base = Maybe Reg
105 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
106 type Displacement = Imm
109 #if sparc_TARGET_ARCH
114 addrOffset :: MachRegsAddr -> Int -> Maybe MachRegsAddr
118 #if alpha_TARGET_ARCH
119 _ -> panic "MachMisc.addrOffset not defined for Alpha"
122 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
123 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
124 AddrBaseIndex r i (ImmInteger n)
125 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
128 #if sparc_TARGET_ARCH
129 AddrRegImm r (ImmInt n)
130 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
131 | otherwise -> Nothing
134 AddrRegImm r (ImmInteger n)
135 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
136 | otherwise -> Nothing
137 where n2 = n + toInteger off
139 AddrRegReg r (RealReg 0)
140 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
141 | otherwise -> Nothing
148 #if alpha_TARGET_ARCH
150 fits8Bits :: Integer -> Bool
151 fits8Bits i = i >= -256 && i < 256
155 #if sparc_TARGET_ARCH
157 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
158 fits13Bits :: Integral a => a -> Bool
159 fits13Bits x = x >= -4096 && x < 4096
163 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
164 ++show i++");\nprobably because of large constant data structures;" ++
165 "\nworkaround: use -fvia-C on this module.\n")
170 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
172 @stgReg@: we map STG registers onto appropriate Stix Trees. Either
173 they map to real machine registers or stored as offsets from BaseReg.
174 Given a MagicId, get_MagicId_reg_or_addr produces either the real
175 register it is in, on this platform, or a StixExpr denoting the
176 address in the register table holding it. get_MagicId_addr always
177 produces the register table address for it.
180 get_MagicId_reg_or_addr :: MagicId -> Either Reg StixExpr
181 get_MagicId_addr :: MagicId -> StixExpr
182 get_Regtable_addr_from_offset :: Int -> StixExpr
184 get_MagicId_reg_or_addr mid
185 = case magicIdRegMaybe mid of
187 Nothing -> Right (get_MagicId_addr mid)
189 get_MagicId_addr BaseReg
190 = panic "MachRegs.get_MagicId_addr of BaseReg"
192 = get_Regtable_addr_from_offset (baseRegOffset mid)
194 get_Regtable_addr_from_offset offset_in_words
195 = case magicIdRegMaybe BaseReg of
196 Nothing -> panic "MachRegs.get_Regtable_addr_from_offset: BaseReg not in a reg"
197 Just rr -> StMachOp MO_Nat_Add
198 [StReg (StixMagicId BaseReg),
199 StInt (toInteger (offset_in_words*BYTES_PER_WORD))]
202 % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
204 @spRel@ gives us a stack relative addressing mode for volatile
205 temporaries and for excess call arguments. @fpRel@, where
206 applicable, is the same but for the frame pointer.
209 spRel :: Int -- desired stack offset in words, positive or negative
214 = AddrBaseIndex (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD))
216 = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD))
219 #if sparc_TARGET_ARCH
220 fpRel :: Int -> MachRegsAddr
221 -- Duznae work for offsets greater than 13 bits; we just hope for
224 = AddrRegImm fp (ImmInt (n * BYTES_PER_WORD))
228 %************************************************************************
230 \subsection[Reg]{Real registers}
232 %************************************************************************
234 RealRegs are machine regs which are available for allocation, in the
235 usual way. We know what class they are, because that's part of the
236 processor's architecture.
238 VirtualRegs are virtual registers. The register allocator will
239 eventually have to map them into RealRegs, or into spill slots.
240 VirtualRegs are allocated on the fly, usually to represent a single
241 value in the abstract assembly code (i.e. dynamic registers are
242 usually single assignment). With the new register allocator, the
243 single assignment restriction isn't necessary to get correct code,
244 although a better register allocation will result if single assignment
245 is used -- because the allocator maps a VirtualReg into a single
246 RealReg, even if the VirtualReg has multiple live ranges.
248 Virtual regs can be of either class, so that info is attached.
253 = VRegUniqueLo Unique -- lower part of a split quantity
254 | VRegUniqueHi Unique -- upper part thereof
257 instance Show VRegUnique where
258 show (VRegUniqueLo u) = show u
259 show (VRegUniqueHi u) = "_hi_" ++ show u
261 pprVRegUnique :: VRegUnique -> Outputable.SDoc
263 = Outputable.text . show
265 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
266 -- when supplied with the vreg for the lower-half of the quantity.
267 getHiVRegFromLo (VirtualRegI (VRegUniqueLo u))
268 = VirtualRegI (VRegUniqueHi u)
269 getHiVRegFromLo other
270 = pprPanic "getHiVRegFromLo" (ppr other)
280 | VirtualRegI VRegUnique
281 | VirtualRegF VRegUnique
282 | VirtualRegD VRegUnique
284 unRealReg (RealReg i) = i
285 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
287 getVRegUnique :: Reg -> VRegUnique
288 getVRegUnique (VirtualRegI vu) = vu
289 getVRegUnique (VirtualRegF vu) = vu
290 getVRegUnique (VirtualRegD vu) = vu
291 getVRegUnique rreg = pprPanic "getVRegUnique on RealReg" (ppr rreg)
293 mkVReg :: Unique -> PrimRep -> Reg
295 #if sparc_TARGET_ARCH
297 FloatRep -> VirtualRegF (VRegUniqueLo u)
298 DoubleRep -> VirtualRegD (VRegUniqueLo u)
299 other -> VirtualRegI (VRegUniqueLo u)
301 = if isFloatingRep pk then VirtualRegD (VRegUniqueLo u)
302 else VirtualRegI (VRegUniqueLo u)
305 isVirtualReg (RealReg _) = False
306 isVirtualReg (VirtualRegI _) = True
307 isVirtualReg (VirtualRegF _) = True
308 isVirtualReg (VirtualRegD _) = True
309 isRealReg = not . isVirtualReg
311 getNewRegNCG :: PrimRep -> NatM Reg
313 = getUniqueNat `thenNat` \ u -> returnNat (mkVReg u pk)
315 instance Eq Reg where
316 (==) (RealReg i1) (RealReg i2) = i1 == i2
317 (==) (VirtualRegI u1) (VirtualRegI u2) = u1 == u2
318 (==) (VirtualRegF u1) (VirtualRegF u2) = u1 == u2
319 (==) (VirtualRegD u1) (VirtualRegD u2) = u1 == u2
320 (==) reg1 reg2 = False
322 instance Ord Reg where
323 compare (RealReg i1) (RealReg i2) = compare i1 i2
324 compare (RealReg _) (VirtualRegI _) = LT
325 compare (RealReg _) (VirtualRegF _) = LT
326 compare (RealReg _) (VirtualRegD _) = LT
328 compare (VirtualRegI _) (RealReg _) = GT
329 compare (VirtualRegI u1) (VirtualRegI u2) = compare u1 u2
330 compare (VirtualRegI _) (VirtualRegF _) = LT
331 compare (VirtualRegI _) (VirtualRegD _) = LT
333 compare (VirtualRegF _) (RealReg _) = GT
334 compare (VirtualRegF _) (VirtualRegI _) = GT
335 compare (VirtualRegF u1) (VirtualRegF u2) = compare u1 u2
336 compare (VirtualRegF _) (VirtualRegD _) = LT
338 compare (VirtualRegD _) (RealReg _) = GT
339 compare (VirtualRegD _) (VirtualRegI _) = GT
340 compare (VirtualRegD _) (VirtualRegF _) = GT
341 compare (VirtualRegD u1) (VirtualRegD u2) = compare u1 u2
344 instance Show Reg where
345 show (RealReg i) = showReg i
346 show (VirtualRegI u) = "%vI_" ++ show u
347 show (VirtualRegF u) = "%vF_" ++ show u
348 show (VirtualRegD u) = "%vD_" ++ show u
350 instance Outputable Reg where
351 ppr r = Outputable.text (show r)
354 ** Machine-specific Reg stuff: **
356 The Alpha has 64 registers of interest; 32 integer registers and 32 floating
357 point registers. The mapping of STG registers to alpha machine registers
358 is defined in StgRegs.h. We are, of course, prepared for any eventuality.
360 #if alpha_TARGET_ARCH
364 v0, f0, ra, pv, gp, sp, zeroh :: Reg
366 f0 = realReg (fReg 0)
367 ra = FixedReg ILIT(26)
369 gp = FixedReg ILIT(29)
370 sp = FixedReg ILIT(30)
371 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
373 t9, t10, t11, t12 :: Reg
381 Intel x86 architecture:
382 - All registers except 7 (esp) are available for use.
383 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
384 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
385 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
386 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
387 fp registers, and 3-operand insns for them, and we translate this into
388 real stack-based x86 fp code after register allocation.
390 The fp registers are all Double registers; we don't have any RcFloat class
391 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
397 fake0, fake1, fake2, fake3, fake4, fake5,
398 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
414 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
415 regClass (VirtualRegI u) = RcInteger
416 regClass (VirtualRegD u) = RcDouble
417 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
418 (ppr (VirtualRegF u))
421 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
422 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
424 showReg :: Int -> String
426 = if n >= 0 && n < 14
428 else "%unknown_x86_real_reg_" ++ show n
433 The SPARC has 64 registers of interest; 32 integer registers and 32
434 floating point registers. The mapping of STG registers to SPARC
435 machine registers is defined in StgRegs.h. We are, of course,
436 prepared for any eventuality.
438 The whole fp-register pairing thing on sparcs is a huge nuisance. See
439 fptools/ghc/includes/MachRegs.h for a description of what's going on
443 #if sparc_TARGET_ARCH
445 gReg,lReg,iReg,oReg,fReg :: Int -> Int
452 nCG_FirstFloatReg :: Int
453 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
455 regClass (VirtualRegI u) = RcInteger
456 regClass (VirtualRegF u) = RcFloat
457 regClass (VirtualRegD u) = RcDouble
458 regClass (RealReg i) | i < 32 = RcInteger
459 | i < nCG_FirstFloatReg = RcDouble
460 | otherwise = RcFloat
462 showReg :: Int -> String
464 | n >= 0 && n < 8 = "%g" ++ show n
465 | n >= 8 && n < 16 = "%o" ++ show (n-8)
466 | n >= 16 && n < 24 = "%l" ++ show (n-16)
467 | n >= 24 && n < 32 = "%i" ++ show (n-24)
468 | n >= 32 && n < 64 = "%f" ++ show (n-32)
469 | otherwise = "%unknown_sparc_real_reg_" ++ show n
471 g0, g1, g2, fp, sp, o0, f0, f1, f6, f8, f22, f26, f27 :: Reg
473 f6 = RealReg (fReg 6)
474 f8 = RealReg (fReg 8)
475 f22 = RealReg (fReg 22)
476 f26 = RealReg (fReg 26)
477 f27 = RealReg (fReg 27)
480 -- g0 is useful for codegen; is always zero, and writes to it vanish.
481 g0 = RealReg (gReg 0)
482 g1 = RealReg (gReg 1)
483 g2 = RealReg (gReg 2)
485 -- FP, SP, int and float return (from C) regs.
486 fp = RealReg (iReg 6)
487 sp = RealReg (oReg 6)
488 o0 = RealReg (oReg 0)
489 f0 = RealReg (fReg 0)
490 f1 = RealReg (fReg 1)
495 Redefine the literals used for machine-registers with non-numeric
496 names in the header files. Gag me with a spoon, eh?
498 #if alpha_TARGET_ARCH
548 #if sparc_TARGET_ARCH
619 baseRegOffset :: MagicId -> Int
621 baseRegOffset (VanillaReg _ 1#) = OFFSET_R1
622 baseRegOffset (VanillaReg _ 2#) = OFFSET_R2
623 baseRegOffset (VanillaReg _ 3#) = OFFSET_R3
624 baseRegOffset (VanillaReg _ 4#) = OFFSET_R4
625 baseRegOffset (VanillaReg _ 5#) = OFFSET_R5
626 baseRegOffset (VanillaReg _ 6#) = OFFSET_R6
627 baseRegOffset (VanillaReg _ 7#) = OFFSET_R7
628 baseRegOffset (VanillaReg _ 8#) = OFFSET_R8
629 baseRegOffset (VanillaReg _ 9#) = OFFSET_R9
630 baseRegOffset (VanillaReg _ 10#) = OFFSET_R10
631 baseRegOffset (FloatReg 1#) = OFFSET_F1
632 baseRegOffset (FloatReg 2#) = OFFSET_F2
633 baseRegOffset (FloatReg 3#) = OFFSET_F3
634 baseRegOffset (FloatReg 4#) = OFFSET_F4
635 baseRegOffset (DoubleReg 1#) = OFFSET_D1
636 baseRegOffset (DoubleReg 2#) = OFFSET_D2
637 baseRegOffset Sp = OFFSET_Sp
638 baseRegOffset Su = OFFSET_Su
639 baseRegOffset SpLim = OFFSET_SpLim
641 baseRegOffset (LongReg _ 1#) = OFFSET_L1
643 baseRegOffset Hp = OFFSET_Hp
644 baseRegOffset HpLim = OFFSET_HpLim
645 baseRegOffset CurrentTSO = OFFSET_CurrentTSO
646 baseRegOffset CurrentNursery = OFFSET_CurrentNursery
647 baseRegOffset HpAlloc = OFFSET_HpAlloc
649 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
650 baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
651 baseRegOffset VoidReg = panic "baseRegOffset:VoidReg"
656 callerSaves :: MagicId -> Bool
658 #ifdef CALLER_SAVES_Base
659 callerSaves BaseReg = True
661 #ifdef CALLER_SAVES_R1
662 callerSaves (VanillaReg _ ILIT(1)) = True
664 #ifdef CALLER_SAVES_R2
665 callerSaves (VanillaReg _ ILIT(2)) = True
667 #ifdef CALLER_SAVES_R3
668 callerSaves (VanillaReg _ ILIT(3)) = True
670 #ifdef CALLER_SAVES_R4
671 callerSaves (VanillaReg _ ILIT(4)) = True
673 #ifdef CALLER_SAVES_R5
674 callerSaves (VanillaReg _ ILIT(5)) = True
676 #ifdef CALLER_SAVES_R6
677 callerSaves (VanillaReg _ ILIT(6)) = True
679 #ifdef CALLER_SAVES_R7
680 callerSaves (VanillaReg _ ILIT(7)) = True
682 #ifdef CALLER_SAVES_R8
683 callerSaves (VanillaReg _ ILIT(8)) = True
685 #ifdef CALLER_SAVES_F1
686 callerSaves (FloatReg 1#) = True
688 #ifdef CALLER_SAVES_F2
689 callerSaves (FloatReg 2#) = True
691 #ifdef CALLER_SAVES_F3
692 callerSaves (FloatReg 3#) = True
694 #ifdef CALLER_SAVES_F4
695 callerSaves (FloatReg 4#) = True
697 #ifdef CALLER_SAVES_D1
698 callerSaves (DoubleReg 1#) = True
700 #ifdef CALLER_SAVES_D2
701 callerSaves (DoubleReg 2#) = True
703 #ifdef CALLER_SAVES_L1
704 callerSaves (LongReg _ ILIT(1)) = True
706 #ifdef CALLER_SAVES_Sp
707 callerSaves Sp = True
709 #ifdef CALLER_SAVES_Su
710 callerSaves Su = True
712 #ifdef CALLER_SAVES_SpLim
713 callerSaves SpLim = True
715 #ifdef CALLER_SAVES_Hp
716 callerSaves Hp = True
718 #ifdef CALLER_SAVES_HpLim
719 callerSaves HpLim = True
721 #ifdef CALLER_SAVES_CurrentTSO
722 callerSaves CurrentTSO = True
724 #ifdef CALLER_SAVES_CurrentNursery
725 callerSaves CurrentNursery = True
727 callerSaves _ = False
731 magicIdRegMaybe :: MagicId -> Maybe Reg
734 magicIdRegMaybe BaseReg = Just (RealReg REG_Base)
737 magicIdRegMaybe (VanillaReg _ 1#) = Just (RealReg REG_R1)
740 magicIdRegMaybe (VanillaReg _ 2#) = Just (RealReg REG_R2)
743 magicIdRegMaybe (VanillaReg _ 3#) = Just (RealReg REG_R3)
746 magicIdRegMaybe (VanillaReg _ 4#) = Just (RealReg REG_R4)
749 magicIdRegMaybe (VanillaReg _ 5#) = Just (RealReg REG_R5)
752 magicIdRegMaybe (VanillaReg _ 6#) = Just (RealReg REG_R6)
755 magicIdRegMaybe (VanillaReg _ 7#) = Just (RealReg REG_R7)
758 magicIdRegMaybe (VanillaReg _ 8#) = Just (RealReg REG_R8)
761 magicIdRegMaybe (VanillaReg _ 9#) = Just (RealReg REG_R9)
764 magicIdRegMaybe (VanillaReg _ 10#) = Just (RealReg REG_R10)
767 magicIdRegMaybe (FloatReg 1#) = Just (RealReg REG_F1)
770 magicIdRegMaybe (FloatReg 2#) = Just (RealReg REG_F2)
773 magicIdRegMaybe (FloatReg 3#) = Just (RealReg REG_F3)
776 magicIdRegMaybe (FloatReg 4#) = Just (RealReg REG_F4)
779 magicIdRegMaybe (DoubleReg 1#) = Just (RealReg REG_D1)
782 magicIdRegMaybe (DoubleReg 2#) = Just (RealReg REG_D2)
785 magicIdRegMaybe Sp = Just (RealReg REG_Sp)
788 magicIdRegMaybe (LongReg _ ILIT(1)) = Just (RealReg REG_Lng1)
791 magicIdRegMaybe (LongReg _ ILIT(2)) = Just (RealReg REG_Lng2)
794 magicIdRegMaybe Su = Just (RealReg REG_Su)
797 magicIdRegMaybe SpLim = Just (RealReg REG_SpLim)
800 magicIdRegMaybe Hp = Just (RealReg REG_Hp)
803 magicIdRegMaybe HpLim = Just (RealReg REG_HpLim)
805 #ifdef REG_CurrentTSO
806 magicIdRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
808 #ifdef REG_CurrentNursery
809 magicIdRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
811 magicIdRegMaybe _ = Nothing
815 -------------------------------
816 -- allMachRegs is the complete set of machine regs.
817 allMachRegNos :: [Int]
819 = IF_ARCH_alpha( [0..63],
820 IF_ARCH_i386( [0..13],
821 IF_ARCH_sparc( ([0..31]
822 ++ [f0,f2 .. nCG_FirstFloatReg-1]
823 ++ [nCG_FirstFloatReg .. f31]),
825 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
826 -- i.e., these are the regs for which we are prepared to allow the
827 -- register allocator to attempt to map VRegs to.
828 allocatableRegs :: [Reg]
830 = let isFree i = isFastTrue (freeReg i)
831 in map RealReg (filter isFree allMachRegNos)
833 -------------------------------
834 -- these are the regs which we cannot assume stay alive over a
836 callClobberedRegs :: [Reg]
839 #if alpha_TARGET_ARCH
840 [0, 1, 2, 3, 4, 5, 6, 7, 8,
841 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
842 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
843 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
844 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
845 #endif {- alpha_TARGET_ARCH -}
847 -- caller-saves registers
848 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
849 #endif {- i386_TARGET_ARCH -}
850 #if sparc_TARGET_ARCH
853 [oReg i | i <- [0..5]] ++
854 [gReg i | i <- [1..7]] ++
855 [fReg i | i <- [0..31]] )
856 #endif {- sparc_TARGET_ARCH -}
858 -------------------------------
859 -- argRegs is the set of regs which are read for an n-argument call to C.
860 -- For archs which pass all args on the stack (x86), is empty.
861 -- Sparc passes up to the first 6 args in regs.
862 -- Dunno about Alpha.
863 argRegs :: Int -> [Reg]
866 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
869 #if alpha_TARGET_ARCH
871 argRegs 1 = freeMappedRegs [16, fReg 16]
872 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
873 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
874 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
875 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
876 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
877 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
878 #endif {- alpha_TARGET_ARCH -}
880 #if sparc_TARGET_ARCH
882 argRegs 1 = map (RealReg . oReg) [0]
883 argRegs 2 = map (RealReg . oReg) [0,1]
884 argRegs 3 = map (RealReg . oReg) [0,1,2]
885 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
886 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
887 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
888 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
889 #endif {- sparc_TARGET_ARCH -}
891 -------------------------------
892 -- all of the arg regs ??
893 #if alpha_TARGET_ARCH
894 allArgRegs :: [(Reg, Reg)]
895 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
896 #endif {- alpha_TARGET_ARCH -}
898 #if sparc_TARGET_ARCH
900 allArgRegs = map RealReg [oReg i | i <- [0..5]]
901 #endif {- sparc_TARGET_ARCH -}
905 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
910 freeReg :: Int -> FastBool
912 #if alpha_TARGET_ARCH
913 freeReg 26 = fastBool False -- return address (ra)
914 freeReg 28 = fastBool False -- reserved for the assembler (at)
915 freeReg 29 = fastBool False -- global pointer (gp)
916 freeReg 30 = fastBool False -- stack pointer (sp)
917 freeReg 31 = fastBool False -- always zero (zeroh)
918 freeReg 63 = fastBool False -- always zero (f31)
922 freeReg esp = fastBool False -- %esp is the C stack pointer
925 #if sparc_TARGET_ARCH
926 freeReg g0 = fastBool False -- %g0 is always 0.
927 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
928 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
929 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
930 freeReg i6 = fastBool False -- %i6 is our frame pointer.
931 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
932 freeReg o6 = fastBool False -- %o6 is our stack pointer.
933 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
934 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
935 freeReg f1 = fastBool False
939 freeReg REG_Base = fastBool False
942 freeReg REG_R1 = fastBool False
945 freeReg REG_R2 = fastBool False
948 freeReg REG_R3 = fastBool False
951 freeReg REG_R4 = fastBool False
954 freeReg REG_R5 = fastBool False
957 freeReg REG_R6 = fastBool False
960 freeReg REG_R7 = fastBool False
963 freeReg REG_R8 = fastBool False
966 freeReg REG_F1 = fastBool False
969 freeReg REG_F2 = fastBool False
972 freeReg REG_F3 = fastBool False
975 freeReg REG_F4 = fastBool False
978 freeReg REG_D1 = fastBool False
981 freeReg REG_D2 = fastBool False
984 freeReg REG_Sp = fastBool False
987 freeReg REG_Su = fastBool False
990 freeReg REG_SpLim = fastBool False
993 freeReg REG_Hp = fastBool False
996 freeReg REG_HpLim = fastBool False
998 freeReg n = fastBool True