1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
16 #include "nativeGen/NCG.h"
21 Imm(..), strImmLit, litToImm,
29 Reg(..), isRealReg, isVirtualReg,
30 RegClass(..), regClass,
35 get_GlobalReg_reg_or_addr,
38 -- * Machine-dependent register-related stuff
39 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
46 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
49 eax, ebx, ecx, edx, esi, edi, ebp, esp,
50 fake0, fake1, fake2, fake3, fake4, fake5,
53 #if x86_64_TARGET_ARCH
54 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
55 eax, ebx, ecx, edx, esi, edi, ebp, esp,
56 r8, r9, r10, r11, r12, r13, r14, r15,
57 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
58 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
60 addrModeRegs, allFPArgRegs,
64 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
65 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
67 #if powerpc_TARGET_ARCH
76 #include "HsVersions.h"
79 # define STOLEN_X86_REGS 4
80 -- HACK: go for the max
83 #include "../includes/MachRegs.h"
86 import MachOp ( MachRep(..) )
88 import CLabel ( CLabel, mkMainCapabilityLabel )
89 import Unique ( Unique )
91 import Outputable ( Outputable(..), pprPanic, panic )
92 import qualified Outputable
97 #if powerpc_TARGET_ARCH
98 #if __GLASGOW_HASKELL__ >= 504
99 import Data.Word ( Word8, Word16, Word32 )
100 import Data.Int ( Int8, Int16, Int32 )
102 import Word ( Word8, Word16, Word32 )
103 import Int ( Int8, Int16, Int32 )
107 -- -----------------------------------------------------------------------------
112 | ImmInteger Integer -- Sigh.
113 | ImmCLbl CLabel -- AbstractC Label (with baggage)
114 | ImmLit Doc -- Simple string
115 | ImmIndex CLabel Int
118 | ImmConstantSum Imm Imm
119 | ImmConstantDiff Imm Imm
120 #if sparc_TARGET_ARCH
121 | LO Imm {- Possible restrictions... -}
124 #if powerpc_TARGET_ARCH
127 | HA Imm {- high halfword adjusted -}
129 strImmLit s = ImmLit (text s)
131 litToImm :: CmmLit -> Imm
132 litToImm (CmmInt i _) = ImmInteger i
133 litToImm (CmmFloat f F32) = ImmFloat f
134 litToImm (CmmFloat f F64) = ImmDouble f
135 litToImm (CmmLabel l) = ImmCLbl l
136 litToImm (CmmLabelOff l off) = ImmIndex l off
137 litToImm (CmmLabelDiffOff l1 l2 off)
139 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
142 -- -----------------------------------------------------------------------------
146 #if alpha_TARGET_ARCH
152 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
153 = AddrBaseIndex Base Index Displacement
156 type Base = Maybe Reg
157 type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8
158 type Displacement = Imm
161 #if sparc_TARGET_ARCH
166 #if powerpc_TARGET_ARCH
171 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
172 addrModeRegs :: AddrMode -> [Reg]
173 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
175 b_regs = case b of { Just r -> [r]; _ -> [] }
176 i_regs = case i of { Just (r,_) -> [r]; _ -> [] }
181 addrOffset :: AddrMode -> Int -> Maybe AddrMode
185 #if alpha_TARGET_ARCH
186 _ -> panic "MachMisc.addrOffset not defined for Alpha"
188 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
189 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
191 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
192 AddrBaseIndex r i (ImmInteger n)
193 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
195 AddrBaseIndex r i (ImmCLbl lbl)
196 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
198 AddrBaseIndex r i (ImmIndex lbl ix)
199 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
201 _ -> Nothing -- in theory, shouldn't happen
203 #if sparc_TARGET_ARCH
204 AddrRegImm r (ImmInt n)
205 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
206 | otherwise -> Nothing
209 AddrRegImm r (ImmInteger n)
210 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
211 | otherwise -> Nothing
212 where n2 = n + toInteger off
214 AddrRegReg r (RealReg 0)
215 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
216 | otherwise -> Nothing
220 #if powerpc_TARGET_ARCH
221 AddrRegImm r (ImmInt n)
222 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
223 | otherwise -> Nothing
226 AddrRegImm r (ImmInteger n)
227 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
228 | otherwise -> Nothing
229 where n2 = n + toInteger off
235 #if alpha_TARGET_ARCH
237 fits8Bits :: Integer -> Bool
238 fits8Bits i = i >= -256 && i < 256
242 #if sparc_TARGET_ARCH
244 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
245 fits13Bits :: Integral a => a -> Bool
246 fits13Bits x = x >= -4096 && x < 4096
250 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
251 ++show i++");\nprobably because of large constant data structures;" ++
252 "\nworkaround: use -fvia-C on this module.\n")
256 #if powerpc_TARGET_ARCH
257 fits16Bits :: Integral a => a -> Bool
258 fits16Bits x = x >= -32768 && x < 32768
260 makeImmediate :: Integral a => MachRep -> Bool -> a -> Maybe Imm
262 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
264 narrow I32 False = fromIntegral (fromIntegral x :: Word32)
265 narrow I16 False = fromIntegral (fromIntegral x :: Word16)
266 narrow I8 False = fromIntegral (fromIntegral x :: Word8)
267 narrow I32 True = fromIntegral (fromIntegral x :: Int32)
268 narrow I16 True = fromIntegral (fromIntegral x :: Int16)
269 narrow I8 True = fromIntegral (fromIntegral x :: Int8)
271 narrowed = narrow rep signed
274 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
275 | otherwise = Nothing
277 | narrowed >= 0 && narrowed < 65536 = Just narrowed
278 | otherwise = Nothing
279 toI16 _ _ = Just narrowed
283 -- @spRel@ gives us a stack relative addressing mode for volatile
284 -- temporaries and for excess call arguments. @fpRel@, where
285 -- applicable, is the same but for the frame pointer.
287 spRel :: Int -- desired stack offset in words, positive or negative
291 #if defined(i386_TARGET_ARCH)
292 = AddrBaseIndex (Just esp) Nothing (ImmInt (n * wORD_SIZE))
293 #elif defined(x86_64_TARGET_ARCH)
294 = AddrBaseIndex (Just rsp) Nothing (ImmInt (n * wORD_SIZE))
296 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
299 #if sparc_TARGET_ARCH
300 fpRel :: Int -> AddrMode
301 -- Duznae work for offsets greater than 13 bits; we just hope for
304 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
308 -- -----------------------------------------------------------------------------
311 -- We map STG registers onto appropriate CmmExprs. Either they map
312 -- to real machine registers or stored as offsets from BaseReg. Given
313 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
314 -- register it is in, on this platform, or a StixExpr denoting the
315 -- address in the register table holding it. get_MagicId_addr always
316 -- produces the register table address for it.
318 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
319 get_GlobalReg_addr :: GlobalReg -> CmmExpr
320 get_Regtable_addr_from_offset :: MachRep -> Int -> CmmExpr
322 get_GlobalReg_reg_or_addr mid
323 = case globalRegMaybe mid of
325 Nothing -> Right (get_GlobalReg_addr mid)
327 get_GlobalReg_addr BaseReg = regTableOffset 0
328 get_GlobalReg_addr mid = get_Regtable_addr_from_offset
329 (globalRegRep mid) (baseRegOffset mid)
331 -- Calculate a literal representing an offset into the register table.
332 -- Used when we don't have an actual BaseReg to offset from.
334 CmmLit (CmmLabelOff mkMainCapabilityLabel (oFFSET_Capability_r + n))
336 get_Regtable_addr_from_offset rep offset
337 = case globalRegMaybe BaseReg of
338 Nothing -> regTableOffset offset
339 Just _ -> CmmRegOff (CmmGlobal BaseReg) offset
341 -- ---------------------------------------------------------------------------
344 -- RealRegs are machine regs which are available for allocation, in
345 -- the usual way. We know what class they are, because that's part of
346 -- the processor's architecture.
348 -- VirtualRegs are virtual registers. The register allocator will
349 -- eventually have to map them into RealRegs, or into spill slots.
350 -- VirtualRegs are allocated on the fly, usually to represent a single
351 -- value in the abstract assembly code (i.e. dynamic registers are
352 -- usually single assignment). With the new register allocator, the
353 -- single assignment restriction isn't necessary to get correct code,
354 -- although a better register allocation will result if single
355 -- assignment is used -- because the allocator maps a VirtualReg into
356 -- a single RealReg, even if the VirtualReg has multiple live ranges.
358 -- Virtual regs can be of either class, so that info is attached.
360 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
361 -- when supplied with the vreg for the lower-half of the quantity.
362 -- (NB. Not reversible).
363 getHiVRegFromLo (VirtualRegI u)
364 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
365 getHiVRegFromLo other
366 = pprPanic "getHiVRegFromLo" (ppr other)
377 = RealReg {-# UNPACK #-} !RegNo
378 | VirtualRegI {-# UNPACK #-} !Unique
379 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
380 | VirtualRegF {-# UNPACK #-} !Unique
381 | VirtualRegD {-# UNPACK #-} !Unique
384 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
385 -- in the register allocator.
386 instance Uniquable Reg where
387 getUnique (RealReg i) = mkUnique 'C' i
388 getUnique (VirtualRegI u) = u
389 getUnique (VirtualRegHi u) = u
390 getUnique (VirtualRegF u) = u
391 getUnique (VirtualRegD u) = u
393 mkVReg :: Unique -> MachRep -> Reg
396 #if sparc_TARGET_ARCH
402 other -> VirtualRegI u
404 isVirtualReg :: Reg -> Bool
405 isVirtualReg (RealReg _) = False
406 isVirtualReg (VirtualRegI _) = True
407 isVirtualReg (VirtualRegHi _) = True
408 isVirtualReg (VirtualRegF _) = True
409 isVirtualReg (VirtualRegD _) = True
411 isRealReg :: Reg -> Bool
412 isRealReg = not . isVirtualReg
414 instance Show Reg where
415 show (RealReg i) = showReg i
416 show (VirtualRegI u) = "%vI_" ++ show u
417 show (VirtualRegHi u) = "%vHi_" ++ show u
418 show (VirtualRegF u) = "%vF_" ++ show u
419 show (VirtualRegD u) = "%vD_" ++ show u
421 instance Outputable Reg where
422 ppr r = Outputable.text (show r)
425 -- -----------------------------------------------------------------------------
426 -- Machine-specific register stuff
428 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
429 -- point registers. The mapping of STG registers to alpha machine registers
430 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
432 #if alpha_TARGET_ARCH
436 v0, f0, ra, pv, gp, sp, zeroh :: Reg
438 f0 = realReg (fReg 0)
439 ra = FixedReg ILIT(26)
441 gp = FixedReg ILIT(29)
442 sp = FixedReg ILIT(30)
443 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
445 t9, t10, t11, t12 :: Reg
453 Intel x86 architecture:
454 - All registers except 7 (esp) are available for use.
455 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
456 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
457 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
458 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
459 fp registers, and 3-operand insns for them, and we translate this into
460 real stack-based x86 fp code after register allocation.
462 The fp registers are all Double registers; we don't have any RcFloat class
463 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
469 fake0, fake1, fake2, fake3, fake4, fake5,
470 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
486 -- On x86, we might want to have an 8-bit RegClass, which would
487 -- contain just regs 1-4 (the others don't have 8-bit versions).
488 -- However, we can get away without this at the moment because the
489 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
490 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
491 regClass (VirtualRegI u) = RcInteger
492 regClass (VirtualRegHi u) = RcInteger
493 regClass (VirtualRegD u) = RcDouble
494 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
495 (ppr (VirtualRegF u))
498 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
499 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
501 showReg :: RegNo -> String
503 = if n >= 0 && n < 14
505 else "%unknown_x86_real_reg_" ++ show n
510 AMD x86_64 architecture:
511 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
512 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
513 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
517 #if x86_64_TARGET_ARCH
519 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
520 r8, r9, r10, r11, r12, r13, r14, r15,
521 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
522 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
557 -- so we can re-use some x86 code:
567 xmm n = RealReg (16+n)
569 -- On x86, we might want to have an 8-bit RegClass, which would
570 -- contain just regs 1-4 (the others don't have 8-bit versions).
571 -- However, we can get away without this at the moment because the
572 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
573 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
574 regClass (VirtualRegI u) = RcInteger
575 regClass (VirtualRegHi u) = RcInteger
576 regClass (VirtualRegD u) = RcDouble
577 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
578 (ppr (VirtualRegF u))
581 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
583 showReg :: RegNo -> String
585 | n >= 16 = "%xmm" ++ show n
586 | n >= 8 = "%r" ++ show n
587 | otherwise = regNames !! n
592 The SPARC has 64 registers of interest; 32 integer registers and 32
593 floating point registers. The mapping of STG registers to SPARC
594 machine registers is defined in StgRegs.h. We are, of course,
595 prepared for any eventuality.
597 The whole fp-register pairing thing on sparcs is a huge nuisance. See
598 fptools/ghc/includes/MachRegs.h for a description of what's going on
602 #if sparc_TARGET_ARCH
604 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
611 nCG_FirstFloatReg :: RegNo
612 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
614 regClass (VirtualRegI u) = RcInteger
615 regClass (VirtualRegF u) = RcFloat
616 regClass (VirtualRegD u) = RcDouble
617 regClass (RealReg i) | i < 32 = RcInteger
618 | i < nCG_FirstFloatReg = RcDouble
619 | otherwise = RcFloat
621 showReg :: RegNo -> String
623 | n >= 0 && n < 8 = "%g" ++ show n
624 | n >= 8 && n < 16 = "%o" ++ show (n-8)
625 | n >= 16 && n < 24 = "%l" ++ show (n-16)
626 | n >= 24 && n < 32 = "%i" ++ show (n-24)
627 | n >= 32 && n < 64 = "%f" ++ show (n-32)
628 | otherwise = "%unknown_sparc_real_reg_" ++ show n
630 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
632 f6 = RealReg (fReg 6)
633 f8 = RealReg (fReg 8)
634 f22 = RealReg (fReg 22)
635 f26 = RealReg (fReg 26)
636 f27 = RealReg (fReg 27)
639 -- g0 is useful for codegen; is always zero, and writes to it vanish.
640 g0 = RealReg (gReg 0)
641 g1 = RealReg (gReg 1)
642 g2 = RealReg (gReg 2)
644 -- FP, SP, int and float return (from C) regs.
645 fp = RealReg (iReg 6)
646 sp = RealReg (oReg 6)
647 o0 = RealReg (oReg 0)
648 o1 = RealReg (oReg 1)
649 f0 = RealReg (fReg 0)
650 f1 = RealReg (fReg 1)
655 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
659 #if powerpc_TARGET_ARCH
663 regClass (VirtualRegI u) = RcInteger
664 regClass (VirtualRegHi u) = RcInteger
665 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
666 (ppr (VirtualRegF u))
667 regClass (VirtualRegD u) = RcDouble
668 regClass (RealReg i) | i < 32 = RcInteger
669 | otherwise = RcDouble
671 showReg :: RegNo -> String
673 | n >= 0 && n <= 31 = "%r" ++ show n
674 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
675 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
682 f1 = RealReg $ fReg 1
683 f20 = RealReg $ fReg 20
684 f21 = RealReg $ fReg 21
688 Redefine the literals used for machine-registers with non-numeric
689 names in the header files. Gag me with a spoon, eh?
692 #if alpha_TARGET_ARCH
743 #if x86_64_TARGET_ARCH
778 #if sparc_TARGET_ARCH
846 #if powerpc_TARGET_ARCH
880 #ifdef darwin_TARGET_OS
950 -- allMachRegs is the complete set of machine regs.
951 allMachRegNos :: [RegNo]
953 = IF_ARCH_alpha( [0..63],
954 IF_ARCH_i386( [0..13],
955 IF_ARCH_x86_64( [0..31],
956 IF_ARCH_sparc( ([0..31]
957 ++ [f0,f2 .. nCG_FirstFloatReg-1]
958 ++ [nCG_FirstFloatReg .. f31]),
959 IF_ARCH_powerpc([0..63],
962 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
963 -- i.e., these are the regs for which we are prepared to allow the
964 -- register allocator to attempt to map VRegs to.
965 allocatableRegs :: [RegNo]
967 = let isFree i = isFastTrue (freeReg i)
968 in filter isFree allMachRegNos
970 -- these are the regs which we cannot assume stay alive over a
972 callClobberedRegs :: [Reg]
975 #if alpha_TARGET_ARCH
976 [0, 1, 2, 3, 4, 5, 6, 7, 8,
977 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
978 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
979 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
980 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
981 #endif /* alpha_TARGET_ARCH */
983 -- caller-saves registers
984 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
985 #endif /* i386_TARGET_ARCH */
986 #if x86_64_TARGET_ARCH
987 -- caller-saves registers
988 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
989 -- all xmm regs are caller-saves
990 #endif /* x86_64_TARGET_ARCH */
991 #if sparc_TARGET_ARCH
994 [oReg i | i <- [0..5]] ++
995 [gReg i | i <- [1..7]] ++
996 [fReg i | i <- [0..31]] )
997 #endif /* sparc_TARGET_ARCH */
998 #if powerpc_TARGET_ARCH
1000 map RealReg (0:[2..12] ++ map fReg [0..13])
1001 #elif linux_TARGET_OS
1002 map RealReg (0:[2..13] ++ map fReg [0..13])
1004 #endif /* powerpc_TARGET_ARCH */
1007 -- argRegs is the set of regs which are read for an n-argument call to C.
1008 -- For archs which pass all args on the stack (x86), is empty.
1009 -- Sparc passes up to the first 6 args in regs.
1010 -- Dunno about Alpha.
1011 argRegs :: RegNo -> [Reg]
1013 #if i386_TARGET_ARCH
1014 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1017 #if x86_64_TARGET_ARCH
1018 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1021 #if alpha_TARGET_ARCH
1023 argRegs 1 = freeMappedRegs [16, fReg 16]
1024 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1025 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1026 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1027 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1028 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1029 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1030 #endif /* alpha_TARGET_ARCH */
1032 #if sparc_TARGET_ARCH
1034 argRegs 1 = map (RealReg . oReg) [0]
1035 argRegs 2 = map (RealReg . oReg) [0,1]
1036 argRegs 3 = map (RealReg . oReg) [0,1,2]
1037 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1038 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1039 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1040 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1041 #endif /* sparc_TARGET_ARCH */
1043 #if powerpc_TARGET_ARCH
1045 argRegs 1 = map RealReg [3]
1046 argRegs 2 = map RealReg [3,4]
1047 argRegs 3 = map RealReg [3..5]
1048 argRegs 4 = map RealReg [3..6]
1049 argRegs 5 = map RealReg [3..7]
1050 argRegs 6 = map RealReg [3..8]
1051 argRegs 7 = map RealReg [3..9]
1052 argRegs 8 = map RealReg [3..10]
1053 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1054 #endif /* powerpc_TARGET_ARCH */
1057 -- all of the arg regs ??
1058 #if alpha_TARGET_ARCH
1059 allArgRegs :: [(Reg, Reg)]
1060 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1061 #endif /* alpha_TARGET_ARCH */
1063 #if sparc_TARGET_ARCH
1065 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1066 #endif /* sparc_TARGET_ARCH */
1068 #if i386_TARGET_ARCH
1070 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1073 #if x86_64_TARGET_ARCH
1075 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1076 allFPArgRegs :: [Reg]
1077 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1080 #if powerpc_TARGET_ARCH
1082 allArgRegs = map RealReg [3..10]
1083 allFPArgRegs :: [Reg]
1084 #if darwin_TARGET_OS
1085 allFPArgRegs = map (RealReg . fReg) [1..13]
1086 #elif linux_TARGET_OS
1087 allFPArgRegs = map (RealReg . fReg) [1..8]
1089 #endif /* powerpc_TARGET_ARCH */
1093 freeReg :: RegNo -> FastBool
1095 #if alpha_TARGET_ARCH
1096 freeReg 26 = fastBool False -- return address (ra)
1097 freeReg 28 = fastBool False -- reserved for the assembler (at)
1098 freeReg 29 = fastBool False -- global pointer (gp)
1099 freeReg 30 = fastBool False -- stack pointer (sp)
1100 freeReg 31 = fastBool False -- always zero (zeroh)
1101 freeReg 63 = fastBool False -- always zero (f31)
1104 #if i386_TARGET_ARCH
1105 freeReg esp = fastBool False -- %esp is the C stack pointer
1108 #if x86_64_TARGET_ARCH
1109 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1112 #if sparc_TARGET_ARCH
1113 freeReg g0 = fastBool False -- %g0 is always 0.
1114 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1115 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1116 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1117 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1118 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1119 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1120 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1121 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1122 freeReg f1 = fastBool False
1125 #if powerpc_TARGET_ARCH
1126 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1127 freeReg 1 = fastBool False -- The Stack Pointer
1128 #if !darwin_TARGET_OS
1129 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1130 freeReg 2 = fastBool False
1135 freeReg REG_Base = fastBool False
1138 freeReg REG_R1 = fastBool False
1141 freeReg REG_R2 = fastBool False
1144 freeReg REG_R3 = fastBool False
1147 freeReg REG_R4 = fastBool False
1150 freeReg REG_R5 = fastBool False
1153 freeReg REG_R6 = fastBool False
1156 freeReg REG_R7 = fastBool False
1159 freeReg REG_R8 = fastBool False
1162 freeReg REG_F1 = fastBool False
1165 freeReg REG_F2 = fastBool False
1168 freeReg REG_F3 = fastBool False
1171 freeReg REG_F4 = fastBool False
1174 freeReg REG_D1 = fastBool False
1177 freeReg REG_D2 = fastBool False
1180 freeReg REG_Sp = fastBool False
1183 freeReg REG_Su = fastBool False
1186 freeReg REG_SpLim = fastBool False
1189 freeReg REG_Hp = fastBool False
1192 freeReg REG_HpLim = fastBool False
1194 freeReg n = fastBool True
1197 -- -----------------------------------------------------------------------------
1198 -- Information about global registers
1200 baseRegOffset :: GlobalReg -> Int
1202 baseRegOffset (VanillaReg 1) = oFFSET_StgRegTable_rR1
1203 baseRegOffset (VanillaReg 2) = oFFSET_StgRegTable_rR2
1204 baseRegOffset (VanillaReg 3) = oFFSET_StgRegTable_rR3
1205 baseRegOffset (VanillaReg 4) = oFFSET_StgRegTable_rR4
1206 baseRegOffset (VanillaReg 5) = oFFSET_StgRegTable_rR5
1207 baseRegOffset (VanillaReg 6) = oFFSET_StgRegTable_rR6
1208 baseRegOffset (VanillaReg 7) = oFFSET_StgRegTable_rR7
1209 baseRegOffset (VanillaReg 8) = oFFSET_StgRegTable_rR8
1210 baseRegOffset (VanillaReg 9) = oFFSET_StgRegTable_rR9
1211 baseRegOffset (VanillaReg 10) = oFFSET_StgRegTable_rR10
1212 baseRegOffset (FloatReg 1) = oFFSET_StgRegTable_rF1
1213 baseRegOffset (FloatReg 2) = oFFSET_StgRegTable_rF2
1214 baseRegOffset (FloatReg 3) = oFFSET_StgRegTable_rF3
1215 baseRegOffset (FloatReg 4) = oFFSET_StgRegTable_rF4
1216 baseRegOffset (DoubleReg 1) = oFFSET_StgRegTable_rD1
1217 baseRegOffset (DoubleReg 2) = oFFSET_StgRegTable_rD2
1218 baseRegOffset Sp = oFFSET_StgRegTable_rSp
1219 baseRegOffset SpLim = oFFSET_StgRegTable_rSpLim
1220 baseRegOffset (LongReg 1) = oFFSET_StgRegTable_rL1
1221 baseRegOffset Hp = oFFSET_StgRegTable_rHp
1222 baseRegOffset HpLim = oFFSET_StgRegTable_rHpLim
1223 baseRegOffset CurrentTSO = oFFSET_StgRegTable_rCurrentTSO
1224 baseRegOffset CurrentNursery = oFFSET_StgRegTable_rCurrentNursery
1225 baseRegOffset HpAlloc = oFFSET_StgRegTable_rHpAlloc
1226 baseRegOffset GCEnter1 = oFFSET_stgGCEnter1
1227 baseRegOffset GCFun = oFFSET_stgGCFun
1229 baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
1230 baseRegOffset _ = panic "baseRegOffset:other"
1234 -- | Returns 'True' if this global register is stored in a caller-saves
1235 -- machine register.
1237 callerSaves :: GlobalReg -> Bool
1239 #ifdef CALLER_SAVES_Base
1240 callerSaves BaseReg = True
1242 #ifdef CALLER_SAVES_R1
1243 callerSaves (VanillaReg _ ILIT(1)) = True
1245 #ifdef CALLER_SAVES_R2
1246 callerSaves (VanillaReg _ ILIT(2)) = True
1248 #ifdef CALLER_SAVES_R3
1249 callerSaves (VanillaReg _ ILIT(3)) = True
1251 #ifdef CALLER_SAVES_R4
1252 callerSaves (VanillaReg _ ILIT(4)) = True
1254 #ifdef CALLER_SAVES_R5
1255 callerSaves (VanillaReg _ ILIT(5)) = True
1257 #ifdef CALLER_SAVES_R6
1258 callerSaves (VanillaReg _ ILIT(6)) = True
1260 #ifdef CALLER_SAVES_R7
1261 callerSaves (VanillaReg _ ILIT(7)) = True
1263 #ifdef CALLER_SAVES_R8
1264 callerSaves (VanillaReg _ ILIT(8)) = True
1266 #ifdef CALLER_SAVES_F1
1267 callerSaves (FloatReg 1#) = True
1269 #ifdef CALLER_SAVES_F2
1270 callerSaves (FloatReg 2#) = True
1272 #ifdef CALLER_SAVES_F3
1273 callerSaves (FloatReg 3#) = True
1275 #ifdef CALLER_SAVES_F4
1276 callerSaves (FloatReg 4#) = True
1278 #ifdef CALLER_SAVES_D1
1279 callerSaves (DoubleReg 1#) = True
1281 #ifdef CALLER_SAVES_D2
1282 callerSaves (DoubleReg 2#) = True
1284 #ifdef CALLER_SAVES_L1
1285 callerSaves (LongReg _ ILIT(1)) = True
1287 #ifdef CALLER_SAVES_Sp
1288 callerSaves Sp = True
1290 #ifdef CALLER_SAVES_SpLim
1291 callerSaves SpLim = True
1293 #ifdef CALLER_SAVES_Hp
1294 callerSaves Hp = True
1296 #ifdef CALLER_SAVES_HpLim
1297 callerSaves HpLim = True
1299 #ifdef CALLER_SAVES_CurrentTSO
1300 callerSaves CurrentTSO = True
1302 #ifdef CALLER_SAVES_CurrentNursery
1303 callerSaves CurrentNursery = True
1305 callerSaves _ = False
1308 -- | Returns 'Nothing' if this global register is not stored
1309 -- in a real machine register, otherwise returns @'Just' reg@, where
1310 -- reg is the machine register it is stored in.
1312 globalRegMaybe :: GlobalReg -> Maybe Reg
1315 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1318 globalRegMaybe (VanillaReg 1) = Just (RealReg REG_R1)
1321 globalRegMaybe (VanillaReg 2) = Just (RealReg REG_R2)
1324 globalRegMaybe (VanillaReg 3) = Just (RealReg REG_R3)
1327 globalRegMaybe (VanillaReg 4) = Just (RealReg REG_R4)
1330 globalRegMaybe (VanillaReg 5) = Just (RealReg REG_R5)
1333 globalRegMaybe (VanillaReg 6) = Just (RealReg REG_R6)
1336 globalRegMaybe (VanillaReg 7) = Just (RealReg REG_R7)
1339 globalRegMaybe (VanillaReg 8) = Just (RealReg REG_R8)
1342 globalRegMaybe (VanillaReg 9) = Just (RealReg REG_R9)
1345 globalRegMaybe (VanillaReg 10) = Just (RealReg REG_R10)
1348 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1351 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1354 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1357 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1360 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1363 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1366 globalRegMaybe Sp = Just (RealReg REG_Sp)
1369 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1372 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1375 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1378 globalRegMaybe Hp = Just (RealReg REG_Hp)
1381 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1383 #ifdef REG_CurrentTSO
1384 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1386 #ifdef REG_CurrentNursery
1387 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1389 globalRegMaybe _ = Nothing