1 -----------------------------------------------------------------------------
3 -- Machine-specific parts of the register allocator
5 -- (c) The University of Glasgow 1996-2004
7 -----------------------------------------------------------------------------
9 #include "nativeGen/NCG.h"
24 #include "HsVersions.h"
26 import Cmm ( BlockId )
27 #if powerpc_TARGET_ARCH || i386_TARGET_ARCH || x86_64_TARGET_ARCH
28 import MachOp ( MachRep(..) )
33 import Constants ( rESERVED_C_STACK_BYTES )
36 -- -----------------------------------------------------------------------------
39 -- @regUsage@ returns the sets of src and destination registers used
40 -- by a particular instruction. Machine registers that are
41 -- pre-allocated to stgRegs are filtered out, because they are
42 -- uninteresting from a register allocation standpoint. (We wouldn't
43 -- want them to end up on the free list!) As far as we are concerned,
44 -- the fixed registers simply don't exist (for allocation purposes,
47 -- regUsage doesn't need to do any trickery for jumps and such. Just
48 -- state precisely the regs read and written by that insn. The
49 -- consequences of control flow transfers, as far as register
50 -- allocation goes, are taken care of by the register allocator.
52 data RegUsage = RU [Reg] [Reg]
57 regUsage :: Instr -> RegUsage
59 interesting (VirtualRegI _) = True
60 interesting (VirtualRegHi _) = True
61 interesting (VirtualRegF _) = True
62 interesting (VirtualRegD _) = True
63 interesting (RealReg i) = isFastTrue (freeReg i)
67 regUsage instr = case instr of
68 LD B reg addr -> usage (regAddr addr, [reg, t9])
69 LD Bu reg addr -> usage (regAddr addr, [reg, t9])
70 -- LD W reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
71 -- LD Wu reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
72 LD sz reg addr -> usage (regAddr addr, [reg])
73 LDA reg addr -> usage (regAddr addr, [reg])
74 LDAH reg addr -> usage (regAddr addr, [reg])
75 LDGP reg addr -> usage (regAddr addr, [reg])
76 LDI sz reg imm -> usage ([], [reg])
77 ST B reg addr -> usage (reg : regAddr addr, [t9, t10])
78 -- ST W reg addr -> usage (reg : regAddr addr, [t9, t10]) : UNUSED
79 ST sz reg addr -> usage (reg : regAddr addr, [])
80 CLR reg -> usage ([], [reg])
81 ABS sz ri reg -> usage (regRI ri, [reg])
82 NEG sz ov ri reg -> usage (regRI ri, [reg])
83 ADD sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
84 SADD sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
85 SUB sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
86 SSUB sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
87 MUL sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
88 DIV sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
89 REM sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
90 NOT ri reg -> usage (regRI ri, [reg])
91 AND r1 ar r2 -> usage (r1 : regRI ar, [r2])
92 ANDNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
93 OR r1 ar r2 -> usage (r1 : regRI ar, [r2])
94 ORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
95 XOR r1 ar r2 -> usage (r1 : regRI ar, [r2])
96 XORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
97 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
98 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
99 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
100 ZAP r1 ar r2 -> usage (r1 : regRI ar, [r2])
101 ZAPNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
102 CMP co r1 ar r2 -> usage (r1 : regRI ar, [r2])
103 FCLR reg -> usage ([], [reg])
104 FABS r1 r2 -> usage ([r1], [r2])
105 FNEG sz r1 r2 -> usage ([r1], [r2])
106 FADD sz r1 r2 r3 -> usage ([r1, r2], [r3])
107 FDIV sz r1 r2 r3 -> usage ([r1, r2], [r3])
108 FMUL sz r1 r2 r3 -> usage ([r1, r2], [r3])
109 FSUB sz r1 r2 r3 -> usage ([r1, r2], [r3])
110 CVTxy sz1 sz2 r1 r2 -> usage ([r1], [r2])
111 FCMP sz co r1 r2 r3 -> usage ([r1, r2], [r3])
112 FMOV r1 r2 -> usage ([r1], [r2])
115 -- We assume that all local jumps will be BI/BF/BR. JMP must be out-of-line.
116 BI cond reg lbl -> usage ([reg], [])
117 BF cond reg lbl -> usage ([reg], [])
118 JMP reg addr hint -> RU (mkRegSet (filter interesting (regAddr addr))) freeRegSet
120 BSR _ n -> RU (argRegSet n) callClobberedRegSet
121 JSR reg addr n -> RU (argRegSet n) callClobberedRegSet
126 usage (src, dst) = RU (mkRegSet (filter interesting src))
127 (mkRegSet (filter interesting dst))
129 interesting (FixedReg _) = False
132 regAddr (AddrReg r1) = [r1]
133 regAddr (AddrRegImm r1 _) = [r1]
134 regAddr (AddrImm _) = []
136 regRI (RIReg r) = [r]
139 #endif /* alpha_TARGET_ARCH */
140 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
141 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
143 regUsage instr = case instr of
144 MOV sz src dst -> usageRW src dst
145 MOVZxL sz src dst -> usageRW src dst
146 MOVSxL sz src dst -> usageRW src dst
147 LEA sz src dst -> usageRW src dst
148 ADD sz src dst -> usageRM src dst
149 ADC sz src dst -> usageRM src dst
150 SUB sz src dst -> usageRM src dst
151 IMUL sz src dst -> usageRM src dst
152 IMUL2 sz src -> mkRU (eax:use_R src) [eax,edx]
153 MUL sz src dst -> usageRM src dst
154 DIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
155 IDIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
156 AND sz src dst -> usageRM src dst
157 OR sz src dst -> usageRM src dst
158 XOR sz src dst -> usageRM src dst
159 NOT sz op -> usageM op
160 NEGI sz op -> usageM op
161 SHL sz imm dst -> usageRM imm dst
162 SAR sz imm dst -> usageRM imm dst
163 SHR sz imm dst -> usageRM imm dst
164 BT sz imm src -> mkRU (use_R src) []
166 PUSH sz op -> mkRU (use_R op) []
167 POP sz op -> mkRU [] (def_W op)
168 TEST sz src dst -> mkRU (use_R src ++ use_R dst) []
169 CMP sz src dst -> mkRU (use_R src ++ use_R dst) []
170 SETCC cond op -> mkRU [] (def_W op)
171 JXX cond lbl -> mkRU [] []
172 JMP op -> mkRU (use_R op) []
173 JMP_TBL op ids -> mkRU (use_R op) []
174 CALL (Left imm) params -> mkRU params callClobberedRegs
175 CALL (Right reg) params -> mkRU (reg:params) callClobberedRegs
176 CLTD sz -> mkRU [eax] [edx]
180 GMOV src dst -> mkRU [src] [dst]
181 GLD sz src dst -> mkRU (use_EA src) [dst]
182 GST sz src dst -> mkRU (src : use_EA dst) []
184 GLDZ dst -> mkRU [] [dst]
185 GLD1 dst -> mkRU [] [dst]
187 GFTOI src dst -> mkRU [src] [dst]
188 GDTOI src dst -> mkRU [src] [dst]
190 GITOF src dst -> mkRU [src] [dst]
191 GITOD src dst -> mkRU [src] [dst]
193 GADD sz s1 s2 dst -> mkRU [s1,s2] [dst]
194 GSUB sz s1 s2 dst -> mkRU [s1,s2] [dst]
195 GMUL sz s1 s2 dst -> mkRU [s1,s2] [dst]
196 GDIV sz s1 s2 dst -> mkRU [s1,s2] [dst]
198 GCMP sz src1 src2 -> mkRU [src1,src2] []
199 GABS sz src dst -> mkRU [src] [dst]
200 GNEG sz src dst -> mkRU [src] [dst]
201 GSQRT sz src dst -> mkRU [src] [dst]
202 GSIN sz src dst -> mkRU [src] [dst]
203 GCOS sz src dst -> mkRU [src] [dst]
204 GTAN sz src dst -> mkRU [src] [dst]
207 #if x86_64_TARGET_ARCH
208 CVTSS2SD src dst -> mkRU [src] [dst]
209 CVTSD2SS src dst -> mkRU [src] [dst]
210 CVTSS2SI src dst -> mkRU (use_R src) [dst]
211 CVTSD2SI src dst -> mkRU (use_R src) [dst]
212 CVTSI2SS src dst -> mkRU (use_R src) [dst]
213 CVTSI2SD src dst -> mkRU (use_R src) [dst]
214 FDIV sz src dst -> usageRM src dst
217 FETCHGOT reg -> mkRU [] [reg]
222 _other -> panic "regUsage: unrecognised instr"
225 #if x86_64_TARGET_ARCH
226 -- call parameters: include %eax, because it is used
227 -- to pass the number of SSE reg arguments to varargs fns.
228 params = eax : allArgRegs ++ allFPArgRegs
231 -- 2 operand form; first operand Read; second Written
232 usageRW :: Operand -> Operand -> RegUsage
233 usageRW op (OpReg reg) = mkRU (use_R op) [reg]
234 usageRW op (OpAddr ea) = mkRU (use_R op ++ use_EA ea) []
236 -- 2 operand form; first operand Read; second Modified
237 usageRM :: Operand -> Operand -> RegUsage
238 usageRM op (OpReg reg) = mkRU (use_R op ++ [reg]) [reg]
239 usageRM op (OpAddr ea) = mkRU (use_R op ++ use_EA ea) []
241 -- 1 operand form; operand Modified
242 usageM :: Operand -> RegUsage
243 usageM (OpReg reg) = mkRU [reg] [reg]
244 usageM (OpAddr ea) = mkRU (use_EA ea) []
246 -- Registers defd when an operand is written.
247 def_W (OpReg reg) = [reg]
248 def_W (OpAddr ea) = []
250 -- Registers used when an operand is read.
251 use_R (OpReg reg) = [reg]
252 use_R (OpImm imm) = []
253 use_R (OpAddr ea) = use_EA ea
255 -- Registers used to compute an effective address.
256 use_EA (ImmAddr _ _) = []
257 use_EA (AddrBaseIndex base index _) =
258 use_base base $! use_index index
259 where use_base (EABaseReg r) x = r : x
261 use_index EAIndexNone = []
262 use_index (EAIndex i _) = [i]
264 mkRU src dst = RU (filter interesting src)
265 (filter interesting dst)
267 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH */
268 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
269 #if sparc_TARGET_ARCH
271 regUsage instr = case instr of
272 LD sz addr reg -> usage (regAddr addr, [reg])
273 ST sz reg addr -> usage (reg : regAddr addr, [])
274 ADD x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
275 SUB x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
276 UMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
277 SMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
278 RDY rd -> usage ([], [rd])
279 AND b r1 ar r2 -> usage (r1 : regRI ar, [r2])
280 ANDN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
281 OR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
282 ORN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
283 XOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
284 XNOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
285 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
286 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
287 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
288 SETHI imm reg -> usage ([], [reg])
289 FABS s r1 r2 -> usage ([r1], [r2])
290 FADD s r1 r2 r3 -> usage ([r1, r2], [r3])
291 FCMP e s r1 r2 -> usage ([r1, r2], [])
292 FDIV s r1 r2 r3 -> usage ([r1, r2], [r3])
293 FMOV s r1 r2 -> usage ([r1], [r2])
294 FMUL s r1 r2 r3 -> usage ([r1, r2], [r3])
295 FNEG s r1 r2 -> usage ([r1], [r2])
296 FSQRT s r1 r2 -> usage ([r1], [r2])
297 FSUB s r1 r2 r3 -> usage ([r1, r2], [r3])
298 FxTOy s1 s2 r1 r2 -> usage ([r1], [r2])
300 -- We assume that all local jumps will be BI/BF. JMP must be out-of-line.
301 JMP dst addr -> usage (regAddr addr, [])
303 CALL (Left imm) n True -> noUsage
304 CALL (Left imm) n False -> usage (argRegs n, callClobberedRegs)
305 CALL (Right reg) n True -> usage ([reg], [])
306 CALL (Right reg) n False -> usage (reg : (argRegs n), callClobberedRegs)
310 usage (src, dst) = RU (regSetFromList (filter interesting src))
311 (regSetFromList (filter interesting dst))
313 regAddr (AddrRegReg r1 r2) = [r1, r2]
314 regAddr (AddrRegImm r1 _) = [r1]
316 regRI (RIReg r) = [r]
319 #endif /* sparc_TARGET_ARCH */
320 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
321 #if powerpc_TARGET_ARCH
323 regUsage instr = case instr of
324 LD sz reg addr -> usage (regAddr addr, [reg])
325 LA sz reg addr -> usage (regAddr addr, [reg])
326 ST sz reg addr -> usage (reg : regAddr addr, [])
327 STU sz reg addr -> usage (reg : regAddr addr, [])
328 LIS reg imm -> usage ([], [reg])
329 LI reg imm -> usage ([], [reg])
330 MR reg1 reg2 -> usage ([reg2], [reg1])
331 CMP sz reg ri -> usage (reg : regRI ri,[])
332 CMPL sz reg ri -> usage (reg : regRI ri,[])
333 BCC cond lbl -> noUsage
334 MTCTR reg -> usage ([reg],[])
335 BCTR targets -> noUsage
336 BL imm params -> usage (params, callClobberedRegs)
337 BCTRL params -> usage (params, callClobberedRegs)
338 ADD reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
339 ADDC reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
340 ADDE reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
341 ADDIS reg1 reg2 imm -> usage ([reg2], [reg1])
342 SUBF reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
343 MULLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
344 DIVW reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
345 DIVWU reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
346 MULLW_MayOflo reg1 reg2 reg3
347 -> usage ([reg2,reg3], [reg1])
348 AND reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
349 OR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
350 XOR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
351 XORIS reg1 reg2 imm -> usage ([reg2], [reg1])
352 EXTS siz reg1 reg2 -> usage ([reg2], [reg1])
353 NEG reg1 reg2 -> usage ([reg2], [reg1])
354 NOT reg1 reg2 -> usage ([reg2], [reg1])
355 SLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
356 SRW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
357 SRAW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
358 RLWINM reg1 reg2 sh mb me
359 -> usage ([reg2], [reg1])
360 FADD sz r1 r2 r3 -> usage ([r2,r3], [r1])
361 FSUB sz r1 r2 r3 -> usage ([r2,r3], [r1])
362 FMUL sz r1 r2 r3 -> usage ([r2,r3], [r1])
363 FDIV sz r1 r2 r3 -> usage ([r2,r3], [r1])
364 FNEG r1 r2 -> usage ([r2], [r1])
365 FCMP r1 r2 -> usage ([r1,r2], [])
366 FCTIWZ r1 r2 -> usage ([r2], [r1])
367 FRSP r1 r2 -> usage ([r2], [r1])
368 MFCR reg -> usage ([], [reg])
369 MFLR reg -> usage ([], [reg])
370 FETCHPC reg -> usage ([], [reg])
373 usage (src, dst) = RU (filter interesting src)
374 (filter interesting dst)
375 regAddr (AddrRegReg r1 r2) = [r1, r2]
376 regAddr (AddrRegImm r1 _) = [r1]
378 regRI (RIReg r) = [r]
380 #endif /* powerpc_TARGET_ARCH */
383 -- -----------------------------------------------------------------------------
384 -- Determine the possible destinations from the current instruction.
386 -- (we always assume that the next instruction is also a valid destination;
387 -- if this isn't the case then the jump should be at the end of the basic
390 jumpDests :: Instr -> [BlockId] -> [BlockId]
393 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
395 JMP_TBL _ ids -> ids ++ acc
396 #elif powerpc_TARGET_ARCH
398 BCTR targets -> targets ++ acc
403 -- -----------------------------------------------------------------------------
404 -- 'patchRegs' function
406 -- 'patchRegs' takes an instruction and applies the given mapping to
407 -- all the register references.
409 patchRegs :: Instr -> (Reg -> Reg) -> Instr
411 #if alpha_TARGET_ARCH
413 patchRegs instr env = case instr of
414 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
415 LDA reg addr -> LDA (env reg) (fixAddr addr)
416 LDAH reg addr -> LDAH (env reg) (fixAddr addr)
417 LDGP reg addr -> LDGP (env reg) (fixAddr addr)
418 LDI sz reg imm -> LDI sz (env reg) imm
419 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
420 CLR reg -> CLR (env reg)
421 ABS sz ar reg -> ABS sz (fixRI ar) (env reg)
422 NEG sz ov ar reg -> NEG sz ov (fixRI ar) (env reg)
423 ADD sz ov r1 ar r2 -> ADD sz ov (env r1) (fixRI ar) (env r2)
424 SADD sz sc r1 ar r2 -> SADD sz sc (env r1) (fixRI ar) (env r2)
425 SUB sz ov r1 ar r2 -> SUB sz ov (env r1) (fixRI ar) (env r2)
426 SSUB sz sc r1 ar r2 -> SSUB sz sc (env r1) (fixRI ar) (env r2)
427 MUL sz ov r1 ar r2 -> MUL sz ov (env r1) (fixRI ar) (env r2)
428 DIV sz un r1 ar r2 -> DIV sz un (env r1) (fixRI ar) (env r2)
429 REM sz un r1 ar r2 -> REM sz un (env r1) (fixRI ar) (env r2)
430 NOT ar reg -> NOT (fixRI ar) (env reg)
431 AND r1 ar r2 -> AND (env r1) (fixRI ar) (env r2)
432 ANDNOT r1 ar r2 -> ANDNOT (env r1) (fixRI ar) (env r2)
433 OR r1 ar r2 -> OR (env r1) (fixRI ar) (env r2)
434 ORNOT r1 ar r2 -> ORNOT (env r1) (fixRI ar) (env r2)
435 XOR r1 ar r2 -> XOR (env r1) (fixRI ar) (env r2)
436 XORNOT r1 ar r2 -> XORNOT (env r1) (fixRI ar) (env r2)
437 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
438 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
439 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
440 ZAP r1 ar r2 -> ZAP (env r1) (fixRI ar) (env r2)
441 ZAPNOT r1 ar r2 -> ZAPNOT (env r1) (fixRI ar) (env r2)
442 CMP co r1 ar r2 -> CMP co (env r1) (fixRI ar) (env r2)
443 FCLR reg -> FCLR (env reg)
444 FABS r1 r2 -> FABS (env r1) (env r2)
445 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
446 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
447 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
448 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
449 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
450 CVTxy s1 s2 r1 r2 -> CVTxy s1 s2 (env r1) (env r2)
451 FCMP s co r1 r2 r3 -> FCMP s co (env r1) (env r2) (env r3)
452 FMOV r1 r2 -> FMOV (env r1) (env r2)
453 BI cond reg lbl -> BI cond (env reg) lbl
454 BF cond reg lbl -> BF cond (env reg) lbl
455 JMP reg addr hint -> JMP (env reg) (fixAddr addr) hint
456 JSR reg addr i -> JSR (env reg) (fixAddr addr) i
459 fixAddr (AddrReg r1) = AddrReg (env r1)
460 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
461 fixAddr other = other
463 fixRI (RIReg r) = RIReg (env r)
466 #endif /* alpha_TARGET_ARCH */
467 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
468 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
470 patchRegs instr env = case instr of
471 MOV sz src dst -> patch2 (MOV sz) src dst
472 MOVZxL sz src dst -> patch2 (MOVZxL sz) src dst
473 MOVSxL sz src dst -> patch2 (MOVSxL sz) src dst
474 LEA sz src dst -> patch2 (LEA sz) src dst
475 ADD sz src dst -> patch2 (ADD sz) src dst
476 ADC sz src dst -> patch2 (ADC sz) src dst
477 SUB sz src dst -> patch2 (SUB sz) src dst
478 IMUL sz src dst -> patch2 (IMUL sz) src dst
479 IMUL2 sz src -> patch1 (IMUL2 sz) src
480 MUL sz src dst -> patch2 (MUL sz) src dst
481 IDIV sz op -> patch1 (IDIV sz) op
482 DIV sz op -> patch1 (DIV sz) op
483 AND sz src dst -> patch2 (AND sz) src dst
484 OR sz src dst -> patch2 (OR sz) src dst
485 XOR sz src dst -> patch2 (XOR sz) src dst
486 NOT sz op -> patch1 (NOT sz) op
487 NEGI sz op -> patch1 (NEGI sz) op
488 SHL sz imm dst -> patch1 (SHL sz imm) dst
489 SAR sz imm dst -> patch1 (SAR sz imm) dst
490 SHR sz imm dst -> patch1 (SHR sz imm) dst
491 BT sz imm src -> patch1 (BT sz imm) src
492 TEST sz src dst -> patch2 (TEST sz) src dst
493 CMP sz src dst -> patch2 (CMP sz) src dst
494 PUSH sz op -> patch1 (PUSH sz) op
495 POP sz op -> patch1 (POP sz) op
496 SETCC cond op -> patch1 (SETCC cond) op
497 JMP op -> patch1 JMP op
498 JMP_TBL op ids -> patch1 JMP_TBL op $ ids
501 GMOV src dst -> GMOV (env src) (env dst)
502 GLD sz src dst -> GLD sz (lookupAddr src) (env dst)
503 GST sz src dst -> GST sz (env src) (lookupAddr dst)
505 GLDZ dst -> GLDZ (env dst)
506 GLD1 dst -> GLD1 (env dst)
508 GFTOI src dst -> GFTOI (env src) (env dst)
509 GDTOI src dst -> GDTOI (env src) (env dst)
511 GITOF src dst -> GITOF (env src) (env dst)
512 GITOD src dst -> GITOD (env src) (env dst)
514 GADD sz s1 s2 dst -> GADD sz (env s1) (env s2) (env dst)
515 GSUB sz s1 s2 dst -> GSUB sz (env s1) (env s2) (env dst)
516 GMUL sz s1 s2 dst -> GMUL sz (env s1) (env s2) (env dst)
517 GDIV sz s1 s2 dst -> GDIV sz (env s1) (env s2) (env dst)
519 GCMP sz src1 src2 -> GCMP sz (env src1) (env src2)
520 GABS sz src dst -> GABS sz (env src) (env dst)
521 GNEG sz src dst -> GNEG sz (env src) (env dst)
522 GSQRT sz src dst -> GSQRT sz (env src) (env dst)
523 GSIN sz src dst -> GSIN sz (env src) (env dst)
524 GCOS sz src dst -> GCOS sz (env src) (env dst)
525 GTAN sz src dst -> GTAN sz (env src) (env dst)
528 #if x86_64_TARGET_ARCH
529 CVTSS2SD src dst -> CVTSS2SD (env src) (env dst)
530 CVTSD2SS src dst -> CVTSD2SS (env src) (env dst)
531 CVTSS2SI src dst -> CVTSS2SI (patchOp src) (env dst)
532 CVTSD2SI src dst -> CVTSD2SI (patchOp src) (env dst)
533 CVTSI2SS src dst -> CVTSI2SS (patchOp src) (env dst)
534 CVTSI2SD src dst -> CVTSI2SD (patchOp src) (env dst)
535 FDIV sz src dst -> FDIV sz (patchOp src) (patchOp dst)
538 CALL (Left imm) _ -> instr
539 CALL (Right reg) p -> CALL (Right (env reg)) p
541 FETCHGOT reg -> FETCHGOT (env reg)
549 _other -> panic "patchRegs: unrecognised instr"
552 patch1 insn op = insn $! patchOp op
553 patch2 insn src dst = (insn $! patchOp src) $! patchOp dst
555 patchOp (OpReg reg) = OpReg $! env reg
556 patchOp (OpImm imm) = OpImm imm
557 patchOp (OpAddr ea) = OpAddr $! lookupAddr ea
559 lookupAddr (ImmAddr imm off) = ImmAddr imm off
560 lookupAddr (AddrBaseIndex base index disp)
561 = ((AddrBaseIndex $! lookupBase base) $! lookupIndex index) disp
563 lookupBase EABaseNone = EABaseNone
564 lookupBase EABaseRip = EABaseRip
565 lookupBase (EABaseReg r) = EABaseReg (env r)
567 lookupIndex EAIndexNone = EAIndexNone
568 lookupIndex (EAIndex r i) = EAIndex (env r) i
570 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH*/
571 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
572 #if sparc_TARGET_ARCH
574 patchRegs instr env = case instr of
575 LD sz addr reg -> LD sz (fixAddr addr) (env reg)
576 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
577 ADD x cc r1 ar r2 -> ADD x cc (env r1) (fixRI ar) (env r2)
578 SUB x cc r1 ar r2 -> SUB x cc (env r1) (fixRI ar) (env r2)
579 UMUL cc r1 ar r2 -> UMUL cc (env r1) (fixRI ar) (env r2)
580 SMUL cc r1 ar r2 -> SMUL cc (env r1) (fixRI ar) (env r2)
581 RDY rd -> RDY (env rd)
582 AND b r1 ar r2 -> AND b (env r1) (fixRI ar) (env r2)
583 ANDN b r1 ar r2 -> ANDN b (env r1) (fixRI ar) (env r2)
584 OR b r1 ar r2 -> OR b (env r1) (fixRI ar) (env r2)
585 ORN b r1 ar r2 -> ORN b (env r1) (fixRI ar) (env r2)
586 XOR b r1 ar r2 -> XOR b (env r1) (fixRI ar) (env r2)
587 XNOR b r1 ar r2 -> XNOR b (env r1) (fixRI ar) (env r2)
588 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
589 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
590 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
591 SETHI imm reg -> SETHI imm (env reg)
592 FABS s r1 r2 -> FABS s (env r1) (env r2)
593 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
594 FCMP e s r1 r2 -> FCMP e s (env r1) (env r2)
595 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
596 FMOV s r1 r2 -> FMOV s (env r1) (env r2)
597 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
598 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
599 FSQRT s r1 r2 -> FSQRT s (env r1) (env r2)
600 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
601 FxTOy s1 s2 r1 r2 -> FxTOy s1 s2 (env r1) (env r2)
602 JMP dsts addr -> JMP dsts (fixAddr addr)
603 CALL (Left i) n t -> CALL (Left i) n t
604 CALL (Right r) n t -> CALL (Right (env r)) n t
607 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
608 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
610 fixRI (RIReg r) = RIReg (env r)
613 #endif /* sparc_TARGET_ARCH */
614 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
615 #if powerpc_TARGET_ARCH
617 patchRegs instr env = case instr of
618 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
619 LA sz reg addr -> LA sz (env reg) (fixAddr addr)
620 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
621 STU sz reg addr -> STU sz (env reg) (fixAddr addr)
622 LIS reg imm -> LIS (env reg) imm
623 LI reg imm -> LI (env reg) imm
624 MR reg1 reg2 -> MR (env reg1) (env reg2)
625 CMP sz reg ri -> CMP sz (env reg) (fixRI ri)
626 CMPL sz reg ri -> CMPL sz (env reg) (fixRI ri)
627 BCC cond lbl -> BCC cond lbl
628 MTCTR reg -> MTCTR (env reg)
629 BCTR targets -> BCTR targets
630 BL imm argRegs -> BL imm argRegs -- argument regs
631 BCTRL argRegs -> BCTRL argRegs -- cannot be remapped
632 ADD reg1 reg2 ri -> ADD (env reg1) (env reg2) (fixRI ri)
633 ADDC reg1 reg2 reg3-> ADDC (env reg1) (env reg2) (env reg3)
634 ADDE reg1 reg2 reg3-> ADDE (env reg1) (env reg2) (env reg3)
635 ADDIS reg1 reg2 imm -> ADDIS (env reg1) (env reg2) imm
636 SUBF reg1 reg2 reg3-> SUBF (env reg1) (env reg2) (env reg3)
637 MULLW reg1 reg2 ri -> MULLW (env reg1) (env reg2) (fixRI ri)
638 DIVW reg1 reg2 reg3-> DIVW (env reg1) (env reg2) (env reg3)
639 DIVWU reg1 reg2 reg3-> DIVWU (env reg1) (env reg2) (env reg3)
640 MULLW_MayOflo reg1 reg2 reg3
641 -> MULLW_MayOflo (env reg1) (env reg2) (env reg3)
642 AND reg1 reg2 ri -> AND (env reg1) (env reg2) (fixRI ri)
643 OR reg1 reg2 ri -> OR (env reg1) (env reg2) (fixRI ri)
644 XOR reg1 reg2 ri -> XOR (env reg1) (env reg2) (fixRI ri)
645 XORIS reg1 reg2 imm -> XORIS (env reg1) (env reg2) imm
646 EXTS sz reg1 reg2 -> EXTS sz (env reg1) (env reg2)
647 NEG reg1 reg2 -> NEG (env reg1) (env reg2)
648 NOT reg1 reg2 -> NOT (env reg1) (env reg2)
649 SLW reg1 reg2 ri -> SLW (env reg1) (env reg2) (fixRI ri)
650 SRW reg1 reg2 ri -> SRW (env reg1) (env reg2) (fixRI ri)
651 SRAW reg1 reg2 ri -> SRAW (env reg1) (env reg2) (fixRI ri)
652 RLWINM reg1 reg2 sh mb me
653 -> RLWINM (env reg1) (env reg2) sh mb me
654 FADD sz r1 r2 r3 -> FADD sz (env r1) (env r2) (env r3)
655 FSUB sz r1 r2 r3 -> FSUB sz (env r1) (env r2) (env r3)
656 FMUL sz r1 r2 r3 -> FMUL sz (env r1) (env r2) (env r3)
657 FDIV sz r1 r2 r3 -> FDIV sz (env r1) (env r2) (env r3)
658 FNEG r1 r2 -> FNEG (env r1) (env r2)
659 FCMP r1 r2 -> FCMP (env r1) (env r2)
660 FCTIWZ r1 r2 -> FCTIWZ (env r1) (env r2)
661 FRSP r1 r2 -> FRSP (env r1) (env r2)
662 MFCR reg -> MFCR (env reg)
663 MFLR reg -> MFLR (env reg)
664 FETCHPC reg -> FETCHPC (env reg)
667 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
668 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
670 fixRI (RIReg r) = RIReg (env r)
672 #endif /* powerpc_TARGET_ARCH */
674 -- -----------------------------------------------------------------------------
675 -- Detecting reg->reg moves
677 -- The register allocator attempts to eliminate reg->reg moves whenever it can,
678 -- by assigning the src and dest temporaries to the same real register.
680 isRegRegMove :: Instr -> Maybe (Reg,Reg)
681 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
683 isRegRegMove (MOV _ (OpReg r1) (OpReg r2)) = Just (r1,r2)
684 #elif powerpc_TARGET_ARCH
685 isRegRegMove (MR dst src) = Just (src,dst)
687 #warning ToDo: isRegRegMove
689 isRegRegMove _ = Nothing
691 -- -----------------------------------------------------------------------------
692 -- Generating spill instructions
695 :: Reg -- register to spill (should be a real)
696 -> Int -- current stack delta
697 -> Int -- spill slot to use
699 mkSpillInstr reg delta slot
700 = ASSERT(isRealReg reg)
702 off = spillSlotToOffset slot
704 #ifdef alpha_TARGET_ARCH
705 {-Alpha: spill below the stack pointer (?)-}
706 ST sz dyn (spRel (- (off `div` 8)))
708 #ifdef i386_TARGET_ARCH
709 let off_w = (off-delta) `div` 4
710 in case regClass reg of
711 RcInteger -> MOV I32 (OpReg reg) (OpAddr (spRel off_w))
712 _ -> GST F80 reg (spRel off_w) {- RcFloat/RcDouble -}
714 #ifdef x86_64_TARGET_ARCH
715 let off_w = (off-delta) `div` 8
716 in case regClass reg of
717 RcInteger -> MOV I64 (OpReg reg) (OpAddr (spRel off_w))
718 RcDouble -> MOV F64 (OpReg reg) (OpAddr (spRel off_w))
719 -- ToDo: will it work to always spill as a double?
720 -- does that cause a stall if the data was a float?
722 #ifdef sparc_TARGET_ARCH
723 {-SPARC: spill below frame pointer leaving 2 words/spill-}
724 let{off_w = 1 + (off `div` 4);
725 sz = case regClass vreg of {
729 in ST sz dyn (fpRel (- off_w))
731 #ifdef powerpc_TARGET_ARCH
732 let sz = case regClass reg of
735 in ST sz reg (AddrRegImm sp (ImmInt (off-delta)))
740 :: Reg -- register to load (should be a real)
741 -> Int -- current stack delta
742 -> Int -- spill slot to use
744 mkLoadInstr reg delta slot
745 = ASSERT(isRealReg reg)
747 off = spillSlotToOffset slot
749 #if alpha_TARGET_ARCH
750 LD sz dyn (spRel (- (off `div` 8)))
753 let off_w = (off-delta) `div` 4
754 in case regClass reg of {
755 RcInteger -> MOV I32 (OpAddr (spRel off_w)) (OpReg reg);
756 _ -> GLD F80 (spRel off_w) reg} {- RcFloat/RcDouble -}
758 #if x86_64_TARGET_ARCH
759 let off_w = (off-delta) `div` 8
760 in case regClass reg of
761 RcInteger -> MOV I64 (OpAddr (spRel off_w)) (OpReg reg)
762 _ -> MOV F64 (OpAddr (spRel off_w)) (OpReg reg)
764 #if sparc_TARGET_ARCH
765 let{off_w = 1 + (off `div` 4);
766 sz = case regClass vreg of {
770 in LD sz (fpRel (- off_w)) dyn
772 #if powerpc_TARGET_ARCH
773 let sz = case regClass reg of
776 in LD sz reg (AddrRegImm sp (ImmInt (off-delta)))
781 spillSlotSize = IF_ARCH_i386(12, 8)
784 maxSpillSlots = ((rESERVED_C_STACK_BYTES - 64) `div` spillSlotSize) - 1
786 -- convert a spill slot number to a *byte* offset, with no sign:
787 -- decide on a per arch basis whether you are spilling above or below
788 -- the C stack pointer.
789 spillSlotToOffset :: Int -> Int
790 spillSlotToOffset slot
791 | slot >= 0 && slot < maxSpillSlots
792 = 64 + spillSlotSize * slot
794 = pprPanic "spillSlotToOffset:"
795 (text "invalid spill location: " <> int slot)