1 -----------------------------------------------------------------------------
3 -- Machine-specific parts of the register allocator
5 -- (c) The University of Glasgow 1996-2004
7 -----------------------------------------------------------------------------
9 #include "nativeGen/NCG.h"
24 #include "HsVersions.h"
26 import Cmm ( BlockId )
27 #if powerpc_TARGET_ARCH || i386_TARGET_ARCH || x86_64_TARGET_ARCH
28 import MachOp ( MachRep(..) )
33 import Constants ( rESERVED_C_STACK_BYTES )
36 -- -----------------------------------------------------------------------------
39 -- @regUsage@ returns the sets of src and destination registers used
40 -- by a particular instruction. Machine registers that are
41 -- pre-allocated to stgRegs are filtered out, because they are
42 -- uninteresting from a register allocation standpoint. (We wouldn't
43 -- want them to end up on the free list!) As far as we are concerned,
44 -- the fixed registers simply don't exist (for allocation purposes,
47 -- regUsage doesn't need to do any trickery for jumps and such. Just
48 -- state precisely the regs read and written by that insn. The
49 -- consequences of control flow transfers, as far as register
50 -- allocation goes, are taken care of by the register allocator.
52 data RegUsage = RU [Reg] [Reg]
57 regUsage :: Instr -> RegUsage
59 interesting (VirtualRegI _) = True
60 interesting (VirtualRegHi _) = True
61 interesting (VirtualRegF _) = True
62 interesting (VirtualRegD _) = True
63 interesting (RealReg i) = isFastTrue (freeReg i)
67 regUsage instr = case instr of
68 LD B reg addr -> usage (regAddr addr, [reg, t9])
69 LD Bu reg addr -> usage (regAddr addr, [reg, t9])
70 -- LD W reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
71 -- LD Wu reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
72 LD sz reg addr -> usage (regAddr addr, [reg])
73 LDA reg addr -> usage (regAddr addr, [reg])
74 LDAH reg addr -> usage (regAddr addr, [reg])
75 LDGP reg addr -> usage (regAddr addr, [reg])
76 LDI sz reg imm -> usage ([], [reg])
77 ST B reg addr -> usage (reg : regAddr addr, [t9, t10])
78 -- ST W reg addr -> usage (reg : regAddr addr, [t9, t10]) : UNUSED
79 ST sz reg addr -> usage (reg : regAddr addr, [])
80 CLR reg -> usage ([], [reg])
81 ABS sz ri reg -> usage (regRI ri, [reg])
82 NEG sz ov ri reg -> usage (regRI ri, [reg])
83 ADD sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
84 SADD sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
85 SUB sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
86 SSUB sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
87 MUL sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
88 DIV sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
89 REM sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
90 NOT ri reg -> usage (regRI ri, [reg])
91 AND r1 ar r2 -> usage (r1 : regRI ar, [r2])
92 ANDNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
93 OR r1 ar r2 -> usage (r1 : regRI ar, [r2])
94 ORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
95 XOR r1 ar r2 -> usage (r1 : regRI ar, [r2])
96 XORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
97 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
98 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
99 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
100 ZAP r1 ar r2 -> usage (r1 : regRI ar, [r2])
101 ZAPNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
102 CMP co r1 ar r2 -> usage (r1 : regRI ar, [r2])
103 FCLR reg -> usage ([], [reg])
104 FABS r1 r2 -> usage ([r1], [r2])
105 FNEG sz r1 r2 -> usage ([r1], [r2])
106 FADD sz r1 r2 r3 -> usage ([r1, r2], [r3])
107 FDIV sz r1 r2 r3 -> usage ([r1, r2], [r3])
108 FMUL sz r1 r2 r3 -> usage ([r1, r2], [r3])
109 FSUB sz r1 r2 r3 -> usage ([r1, r2], [r3])
110 CVTxy sz1 sz2 r1 r2 -> usage ([r1], [r2])
111 FCMP sz co r1 r2 r3 -> usage ([r1, r2], [r3])
112 FMOV r1 r2 -> usage ([r1], [r2])
115 -- We assume that all local jumps will be BI/BF/BR. JMP must be out-of-line.
116 BI cond reg lbl -> usage ([reg], [])
117 BF cond reg lbl -> usage ([reg], [])
118 JMP reg addr hint -> RU (mkRegSet (filter interesting (regAddr addr))) freeRegSet
120 BSR _ n -> RU (argRegSet n) callClobberedRegSet
121 JSR reg addr n -> RU (argRegSet n) callClobberedRegSet
126 usage (src, dst) = RU (mkRegSet (filter interesting src))
127 (mkRegSet (filter interesting dst))
129 interesting (FixedReg _) = False
132 regAddr (AddrReg r1) = [r1]
133 regAddr (AddrRegImm r1 _) = [r1]
134 regAddr (AddrImm _) = []
136 regRI (RIReg r) = [r]
139 #endif /* alpha_TARGET_ARCH */
140 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
141 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
143 regUsage instr = case instr of
144 MOV sz src dst -> usageRW src dst
145 MOVZxL sz src dst -> usageRW src dst
146 MOVSxL sz src dst -> usageRW src dst
147 LEA sz src dst -> usageRW src dst
148 ADD sz src dst -> usageRM src dst
149 ADC sz src dst -> usageRM src dst
150 SUB sz src dst -> usageRM src dst
151 IMUL sz src dst -> usageRM src dst
152 IMUL64 sd1 sd2 -> mkRU [sd1,sd2] [sd1,sd2]
153 MUL sz src dst -> usageRM src dst
154 DIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
155 IDIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
156 AND sz src dst -> usageRM src dst
157 OR sz src dst -> usageRM src dst
158 XOR sz src dst -> usageRM src dst
159 NOT sz op -> usageM op
160 NEGI sz op -> usageM op
161 SHL sz imm dst -> usageRM imm dst
162 SAR sz imm dst -> usageRM imm dst
163 SHR sz imm dst -> usageRM imm dst
164 BT sz imm src -> mkRU (use_R src) []
166 PUSH sz op -> mkRU (use_R op) []
167 POP sz op -> mkRU [] (def_W op)
168 TEST sz src dst -> mkRU (use_R src ++ use_R dst) []
169 CMP sz src dst -> mkRU (use_R src ++ use_R dst) []
170 SETCC cond op -> mkRU [] (def_W op)
171 JXX cond lbl -> mkRU [] []
172 JMP op -> mkRU (use_R op) []
173 JMP_TBL op ids -> mkRU (use_R op) []
175 CALL (Left imm) -> mkRU [] callClobberedRegs
176 CALL (Right reg) -> mkRU [reg] callClobberedRegs
178 CALL (Left imm) -> mkRU params callClobberedRegs
179 CALL (Right reg) -> mkRU (reg:params) callClobberedRegs
181 CLTD sz -> mkRU [eax] [edx]
185 GMOV src dst -> mkRU [src] [dst]
186 GLD sz src dst -> mkRU (use_EA src) [dst]
187 GST sz src dst -> mkRU (src : use_EA dst) []
189 GLDZ dst -> mkRU [] [dst]
190 GLD1 dst -> mkRU [] [dst]
192 GFTOI src dst -> mkRU [src] [dst]
193 GDTOI src dst -> mkRU [src] [dst]
195 GITOF src dst -> mkRU [src] [dst]
196 GITOD src dst -> mkRU [src] [dst]
198 GADD sz s1 s2 dst -> mkRU [s1,s2] [dst]
199 GSUB sz s1 s2 dst -> mkRU [s1,s2] [dst]
200 GMUL sz s1 s2 dst -> mkRU [s1,s2] [dst]
201 GDIV sz s1 s2 dst -> mkRU [s1,s2] [dst]
203 GCMP sz src1 src2 -> mkRU [src1,src2] []
204 GABS sz src dst -> mkRU [src] [dst]
205 GNEG sz src dst -> mkRU [src] [dst]
206 GSQRT sz src dst -> mkRU [src] [dst]
207 GSIN sz src dst -> mkRU [src] [dst]
208 GCOS sz src dst -> mkRU [src] [dst]
209 GTAN sz src dst -> mkRU [src] [dst]
212 #if x86_64_TARGET_ARCH
213 CVTSS2SD src dst -> mkRU [src] [dst]
214 CVTSD2SS src dst -> mkRU [src] [dst]
215 CVTSS2SI src dst -> mkRU (use_R src) [dst]
216 CVTSD2SI src dst -> mkRU (use_R src) [dst]
217 CVTSI2SS src dst -> mkRU (use_R src) [dst]
218 CVTSI2SD src dst -> mkRU (use_R src) [dst]
219 FDIV sz src dst -> usageRM src dst
222 FETCHGOT reg -> mkRU [] [reg]
227 _other -> panic "regUsage: unrecognised instr"
230 #if x86_64_TARGET_ARCH
231 -- call parameters: include %eax, because it is used
232 -- to pass the number of SSE reg arguments to varargs fns.
233 params = eax : allArgRegs ++ allFPArgRegs
236 -- 2 operand form; first operand Read; second Written
237 usageRW :: Operand -> Operand -> RegUsage
238 usageRW op (OpReg reg) = mkRU (use_R op) [reg]
239 usageRW op (OpAddr ea) = mkRU (use_R op ++ use_EA ea) []
241 -- 2 operand form; first operand Read; second Modified
242 usageRM :: Operand -> Operand -> RegUsage
243 usageRM op (OpReg reg) = mkRU (use_R op ++ [reg]) [reg]
244 usageRM op (OpAddr ea) = mkRU (use_R op ++ use_EA ea) []
246 -- 1 operand form; operand Modified
247 usageM :: Operand -> RegUsage
248 usageM (OpReg reg) = mkRU [reg] [reg]
249 usageM (OpAddr ea) = mkRU (use_EA ea) []
251 -- Registers defd when an operand is written.
252 def_W (OpReg reg) = [reg]
253 def_W (OpAddr ea) = []
255 -- Registers used when an operand is read.
256 use_R (OpReg reg) = [reg]
257 use_R (OpImm imm) = []
258 use_R (OpAddr ea) = use_EA ea
260 -- Registers used to compute an effective address.
261 use_EA (ImmAddr _ _) = []
262 use_EA (AddrBaseIndex Nothing Nothing _) = []
263 use_EA (AddrBaseIndex (Just b) Nothing _) = [b]
264 use_EA (AddrBaseIndex Nothing (Just (i,_)) _) = [i]
265 use_EA (AddrBaseIndex (Just b) (Just (i,_)) _) = [b,i]
267 mkRU src dst = RU (filter interesting src)
268 (filter interesting dst)
270 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH */
271 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
272 #if sparc_TARGET_ARCH
274 regUsage instr = case instr of
275 LD sz addr reg -> usage (regAddr addr, [reg])
276 ST sz reg addr -> usage (reg : regAddr addr, [])
277 ADD x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
278 SUB x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
279 UMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
280 SMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
281 RDY rd -> usage ([], [rd])
282 AND b r1 ar r2 -> usage (r1 : regRI ar, [r2])
283 ANDN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
284 OR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
285 ORN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
286 XOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
287 XNOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
288 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
289 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
290 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
291 SETHI imm reg -> usage ([], [reg])
292 FABS s r1 r2 -> usage ([r1], [r2])
293 FADD s r1 r2 r3 -> usage ([r1, r2], [r3])
294 FCMP e s r1 r2 -> usage ([r1, r2], [])
295 FDIV s r1 r2 r3 -> usage ([r1, r2], [r3])
296 FMOV s r1 r2 -> usage ([r1], [r2])
297 FMUL s r1 r2 r3 -> usage ([r1, r2], [r3])
298 FNEG s r1 r2 -> usage ([r1], [r2])
299 FSQRT s r1 r2 -> usage ([r1], [r2])
300 FSUB s r1 r2 r3 -> usage ([r1, r2], [r3])
301 FxTOy s1 s2 r1 r2 -> usage ([r1], [r2])
303 -- We assume that all local jumps will be BI/BF. JMP must be out-of-line.
304 JMP dst addr -> usage (regAddr addr, [])
306 CALL (Left imm) n True -> noUsage
307 CALL (Left imm) n False -> usage (argRegs n, callClobberedRegs)
308 CALL (Right reg) n True -> usage ([reg], [])
309 CALL (Right reg) n False -> usage (reg : (argRegs n), callClobberedRegs)
313 usage (src, dst) = RU (regSetFromList (filter interesting src))
314 (regSetFromList (filter interesting dst))
316 regAddr (AddrRegReg r1 r2) = [r1, r2]
317 regAddr (AddrRegImm r1 _) = [r1]
319 regRI (RIReg r) = [r]
322 #endif /* sparc_TARGET_ARCH */
323 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
324 #if powerpc_TARGET_ARCH
326 regUsage instr = case instr of
327 LD sz reg addr -> usage (regAddr addr, [reg])
328 LA sz reg addr -> usage (regAddr addr, [reg])
329 ST sz reg addr -> usage (reg : regAddr addr, [])
330 STU sz reg addr -> usage (reg : regAddr addr, [])
331 LIS reg imm -> usage ([], [reg])
332 LI reg imm -> usage ([], [reg])
333 MR reg1 reg2 -> usage ([reg2], [reg1])
334 CMP sz reg ri -> usage (reg : regRI ri,[])
335 CMPL sz reg ri -> usage (reg : regRI ri,[])
336 BCC cond lbl -> noUsage
337 MTCTR reg -> usage ([reg],[])
338 BCTR targets -> noUsage
339 BL imm params -> usage (params, callClobberedRegs)
340 BCTRL params -> usage (params, callClobberedRegs)
341 ADD reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
342 ADDC reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
343 ADDE reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
344 ADDIS reg1 reg2 imm -> usage ([reg2], [reg1])
345 SUBF reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
346 MULLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
347 DIVW reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
348 DIVWU reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
349 MULLW_MayOflo reg1 reg2 reg3
350 -> usage ([reg2,reg3], [reg1])
351 AND reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
352 OR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
353 XOR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
354 XORIS reg1 reg2 imm -> usage ([reg2], [reg1])
355 EXTS siz reg1 reg2 -> usage ([reg2], [reg1])
356 NEG reg1 reg2 -> usage ([reg2], [reg1])
357 NOT reg1 reg2 -> usage ([reg2], [reg1])
358 SLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
359 SRW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
360 SRAW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
361 RLWINM reg1 reg2 sh mb me
362 -> usage ([reg2], [reg1])
363 FADD sz r1 r2 r3 -> usage ([r2,r3], [r1])
364 FSUB sz r1 r2 r3 -> usage ([r2,r3], [r1])
365 FMUL sz r1 r2 r3 -> usage ([r2,r3], [r1])
366 FDIV sz r1 r2 r3 -> usage ([r2,r3], [r1])
367 FNEG r1 r2 -> usage ([r2], [r1])
368 FCMP r1 r2 -> usage ([r1,r2], [])
369 FCTIWZ r1 r2 -> usage ([r2], [r1])
370 FRSP r1 r2 -> usage ([r2], [r1])
371 MFCR reg -> usage ([], [reg])
372 MFLR reg -> usage ([], [reg])
373 FETCHPC reg -> usage ([], [reg])
376 usage (src, dst) = RU (filter interesting src)
377 (filter interesting dst)
378 regAddr (AddrRegReg r1 r2) = [r1, r2]
379 regAddr (AddrRegImm r1 _) = [r1]
381 regRI (RIReg r) = [r]
383 #endif /* powerpc_TARGET_ARCH */
386 -- -----------------------------------------------------------------------------
387 -- Determine the possible destinations from the current instruction.
389 -- (we always assume that the next instruction is also a valid destination;
390 -- if this isn't the case then the jump should be at the end of the basic
393 jumpDests :: Instr -> [BlockId] -> [BlockId]
396 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
398 JMP_TBL _ ids -> ids ++ acc
399 #elif powerpc_TARGET_ARCH
401 BCTR targets -> targets ++ acc
406 -- -----------------------------------------------------------------------------
407 -- 'patchRegs' function
409 -- 'patchRegs' takes an instruction and applies the given mapping to
410 -- all the register references.
412 patchRegs :: Instr -> (Reg -> Reg) -> Instr
414 #if alpha_TARGET_ARCH
416 patchRegs instr env = case instr of
417 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
418 LDA reg addr -> LDA (env reg) (fixAddr addr)
419 LDAH reg addr -> LDAH (env reg) (fixAddr addr)
420 LDGP reg addr -> LDGP (env reg) (fixAddr addr)
421 LDI sz reg imm -> LDI sz (env reg) imm
422 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
423 CLR reg -> CLR (env reg)
424 ABS sz ar reg -> ABS sz (fixRI ar) (env reg)
425 NEG sz ov ar reg -> NEG sz ov (fixRI ar) (env reg)
426 ADD sz ov r1 ar r2 -> ADD sz ov (env r1) (fixRI ar) (env r2)
427 SADD sz sc r1 ar r2 -> SADD sz sc (env r1) (fixRI ar) (env r2)
428 SUB sz ov r1 ar r2 -> SUB sz ov (env r1) (fixRI ar) (env r2)
429 SSUB sz sc r1 ar r2 -> SSUB sz sc (env r1) (fixRI ar) (env r2)
430 MUL sz ov r1 ar r2 -> MUL sz ov (env r1) (fixRI ar) (env r2)
431 DIV sz un r1 ar r2 -> DIV sz un (env r1) (fixRI ar) (env r2)
432 REM sz un r1 ar r2 -> REM sz un (env r1) (fixRI ar) (env r2)
433 NOT ar reg -> NOT (fixRI ar) (env reg)
434 AND r1 ar r2 -> AND (env r1) (fixRI ar) (env r2)
435 ANDNOT r1 ar r2 -> ANDNOT (env r1) (fixRI ar) (env r2)
436 OR r1 ar r2 -> OR (env r1) (fixRI ar) (env r2)
437 ORNOT r1 ar r2 -> ORNOT (env r1) (fixRI ar) (env r2)
438 XOR r1 ar r2 -> XOR (env r1) (fixRI ar) (env r2)
439 XORNOT r1 ar r2 -> XORNOT (env r1) (fixRI ar) (env r2)
440 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
441 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
442 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
443 ZAP r1 ar r2 -> ZAP (env r1) (fixRI ar) (env r2)
444 ZAPNOT r1 ar r2 -> ZAPNOT (env r1) (fixRI ar) (env r2)
445 CMP co r1 ar r2 -> CMP co (env r1) (fixRI ar) (env r2)
446 FCLR reg -> FCLR (env reg)
447 FABS r1 r2 -> FABS (env r1) (env r2)
448 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
449 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
450 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
451 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
452 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
453 CVTxy s1 s2 r1 r2 -> CVTxy s1 s2 (env r1) (env r2)
454 FCMP s co r1 r2 r3 -> FCMP s co (env r1) (env r2) (env r3)
455 FMOV r1 r2 -> FMOV (env r1) (env r2)
456 BI cond reg lbl -> BI cond (env reg) lbl
457 BF cond reg lbl -> BF cond (env reg) lbl
458 JMP reg addr hint -> JMP (env reg) (fixAddr addr) hint
459 JSR reg addr i -> JSR (env reg) (fixAddr addr) i
462 fixAddr (AddrReg r1) = AddrReg (env r1)
463 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
464 fixAddr other = other
466 fixRI (RIReg r) = RIReg (env r)
469 #endif /* alpha_TARGET_ARCH */
470 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
471 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
473 patchRegs instr env = case instr of
474 MOV sz src dst -> patch2 (MOV sz) src dst
475 MOVZxL sz src dst -> patch2 (MOVZxL sz) src dst
476 MOVSxL sz src dst -> patch2 (MOVSxL sz) src dst
477 LEA sz src dst -> patch2 (LEA sz) src dst
478 ADD sz src dst -> patch2 (ADD sz) src dst
479 ADC sz src dst -> patch2 (ADC sz) src dst
480 SUB sz src dst -> patch2 (SUB sz) src dst
481 IMUL sz src dst -> patch2 (IMUL sz) src dst
482 IMUL64 sd1 sd2 -> IMUL64 (env sd1) (env sd2)
483 MUL sz src dst -> patch2 (MUL sz) src dst
484 IDIV sz op -> patch1 (IDIV sz) op
485 DIV sz op -> patch1 (DIV sz) op
486 AND sz src dst -> patch2 (AND sz) src dst
487 OR sz src dst -> patch2 (OR sz) src dst
488 XOR sz src dst -> patch2 (XOR sz) src dst
489 NOT sz op -> patch1 (NOT sz) op
490 NEGI sz op -> patch1 (NEGI sz) op
491 SHL sz imm dst -> patch1 (SHL sz imm) dst
492 SAR sz imm dst -> patch1 (SAR sz imm) dst
493 SHR sz imm dst -> patch1 (SHR sz imm) dst
494 BT sz imm src -> patch1 (BT sz imm) src
495 TEST sz src dst -> patch2 (TEST sz) src dst
496 CMP sz src dst -> patch2 (CMP sz) src dst
497 PUSH sz op -> patch1 (PUSH sz) op
498 POP sz op -> patch1 (POP sz) op
499 SETCC cond op -> patch1 (SETCC cond) op
500 JMP op -> patch1 JMP op
501 JMP_TBL op ids -> patch1 JMP_TBL op $ ids
504 GMOV src dst -> GMOV (env src) (env dst)
505 GLD sz src dst -> GLD sz (lookupAddr src) (env dst)
506 GST sz src dst -> GST sz (env src) (lookupAddr dst)
508 GLDZ dst -> GLDZ (env dst)
509 GLD1 dst -> GLD1 (env dst)
511 GFTOI src dst -> GFTOI (env src) (env dst)
512 GDTOI src dst -> GDTOI (env src) (env dst)
514 GITOF src dst -> GITOF (env src) (env dst)
515 GITOD src dst -> GITOD (env src) (env dst)
517 GADD sz s1 s2 dst -> GADD sz (env s1) (env s2) (env dst)
518 GSUB sz s1 s2 dst -> GSUB sz (env s1) (env s2) (env dst)
519 GMUL sz s1 s2 dst -> GMUL sz (env s1) (env s2) (env dst)
520 GDIV sz s1 s2 dst -> GDIV sz (env s1) (env s2) (env dst)
522 GCMP sz src1 src2 -> GCMP sz (env src1) (env src2)
523 GABS sz src dst -> GABS sz (env src) (env dst)
524 GNEG sz src dst -> GNEG sz (env src) (env dst)
525 GSQRT sz src dst -> GSQRT sz (env src) (env dst)
526 GSIN sz src dst -> GSIN sz (env src) (env dst)
527 GCOS sz src dst -> GCOS sz (env src) (env dst)
528 GTAN sz src dst -> GTAN sz (env src) (env dst)
531 #if x86_64_TARGET_ARCH
532 CVTSS2SD src dst -> CVTSS2SD (env src) (env dst)
533 CVTSD2SS src dst -> CVTSD2SS (env src) (env dst)
534 CVTSS2SI src dst -> CVTSS2SI (patchOp src) (env dst)
535 CVTSD2SI src dst -> CVTSD2SI (patchOp src) (env dst)
536 CVTSI2SS src dst -> CVTSI2SS (patchOp src) (env dst)
537 CVTSI2SD src dst -> CVTSI2SD (patchOp src) (env dst)
538 FDIV sz src dst -> FDIV sz (patchOp src) (patchOp dst)
541 CALL (Left imm) -> instr
542 CALL (Right reg) -> CALL (Right (env reg))
544 FETCHGOT reg -> FETCHGOT (env reg)
552 _other -> panic "patchRegs: unrecognised instr"
555 patch1 insn op = insn $! patchOp op
556 patch2 insn src dst = (insn $! patchOp src) $! patchOp dst
558 patchOp (OpReg reg) = OpReg (env reg)
559 patchOp (OpImm imm) = OpImm imm
560 patchOp (OpAddr ea) = OpAddr (lookupAddr ea)
562 lookupAddr (ImmAddr imm off) = ImmAddr imm off
563 lookupAddr (AddrBaseIndex base index disp)
564 = AddrBaseIndex (lookupBase base) (lookupIndex index) disp
566 lookupBase Nothing = Nothing
567 lookupBase (Just r) = Just (env r)
569 lookupIndex Nothing = Nothing
570 lookupIndex (Just (r,i)) = Just (env r, i)
572 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH*/
573 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
574 #if sparc_TARGET_ARCH
576 patchRegs instr env = case instr of
577 LD sz addr reg -> LD sz (fixAddr addr) (env reg)
578 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
579 ADD x cc r1 ar r2 -> ADD x cc (env r1) (fixRI ar) (env r2)
580 SUB x cc r1 ar r2 -> SUB x cc (env r1) (fixRI ar) (env r2)
581 UMUL cc r1 ar r2 -> UMUL cc (env r1) (fixRI ar) (env r2)
582 SMUL cc r1 ar r2 -> SMUL cc (env r1) (fixRI ar) (env r2)
583 RDY rd -> RDY (env rd)
584 AND b r1 ar r2 -> AND b (env r1) (fixRI ar) (env r2)
585 ANDN b r1 ar r2 -> ANDN b (env r1) (fixRI ar) (env r2)
586 OR b r1 ar r2 -> OR b (env r1) (fixRI ar) (env r2)
587 ORN b r1 ar r2 -> ORN b (env r1) (fixRI ar) (env r2)
588 XOR b r1 ar r2 -> XOR b (env r1) (fixRI ar) (env r2)
589 XNOR b r1 ar r2 -> XNOR b (env r1) (fixRI ar) (env r2)
590 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
591 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
592 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
593 SETHI imm reg -> SETHI imm (env reg)
594 FABS s r1 r2 -> FABS s (env r1) (env r2)
595 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
596 FCMP e s r1 r2 -> FCMP e s (env r1) (env r2)
597 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
598 FMOV s r1 r2 -> FMOV s (env r1) (env r2)
599 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
600 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
601 FSQRT s r1 r2 -> FSQRT s (env r1) (env r2)
602 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
603 FxTOy s1 s2 r1 r2 -> FxTOy s1 s2 (env r1) (env r2)
604 JMP dsts addr -> JMP dsts (fixAddr addr)
605 CALL (Left i) n t -> CALL (Left i) n t
606 CALL (Right r) n t -> CALL (Right (env r)) n t
609 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
610 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
612 fixRI (RIReg r) = RIReg (env r)
615 #endif /* sparc_TARGET_ARCH */
616 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
617 #if powerpc_TARGET_ARCH
619 patchRegs instr env = case instr of
620 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
621 LA sz reg addr -> LA sz (env reg) (fixAddr addr)
622 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
623 STU sz reg addr -> STU sz (env reg) (fixAddr addr)
624 LIS reg imm -> LIS (env reg) imm
625 LI reg imm -> LI (env reg) imm
626 MR reg1 reg2 -> MR (env reg1) (env reg2)
627 CMP sz reg ri -> CMP sz (env reg) (fixRI ri)
628 CMPL sz reg ri -> CMPL sz (env reg) (fixRI ri)
629 BCC cond lbl -> BCC cond lbl
630 MTCTR reg -> MTCTR (env reg)
631 BCTR targets -> BCTR targets
632 BL imm argRegs -> BL imm argRegs -- argument regs
633 BCTRL argRegs -> BCTRL argRegs -- cannot be remapped
634 ADD reg1 reg2 ri -> ADD (env reg1) (env reg2) (fixRI ri)
635 ADDC reg1 reg2 reg3-> ADDC (env reg1) (env reg2) (env reg3)
636 ADDE reg1 reg2 reg3-> ADDE (env reg1) (env reg2) (env reg3)
637 ADDIS reg1 reg2 imm -> ADDIS (env reg1) (env reg2) imm
638 SUBF reg1 reg2 reg3-> SUBF (env reg1) (env reg2) (env reg3)
639 MULLW reg1 reg2 ri -> MULLW (env reg1) (env reg2) (fixRI ri)
640 DIVW reg1 reg2 reg3-> DIVW (env reg1) (env reg2) (env reg3)
641 DIVWU reg1 reg2 reg3-> DIVWU (env reg1) (env reg2) (env reg3)
642 MULLW_MayOflo reg1 reg2 reg3
643 -> MULLW_MayOflo (env reg1) (env reg2) (env reg3)
644 AND reg1 reg2 ri -> AND (env reg1) (env reg2) (fixRI ri)
645 OR reg1 reg2 ri -> OR (env reg1) (env reg2) (fixRI ri)
646 XOR reg1 reg2 ri -> XOR (env reg1) (env reg2) (fixRI ri)
647 XORIS reg1 reg2 imm -> XORIS (env reg1) (env reg2) imm
648 EXTS sz reg1 reg2 -> EXTS sz (env reg1) (env reg2)
649 NEG reg1 reg2 -> NEG (env reg1) (env reg2)
650 NOT reg1 reg2 -> NOT (env reg1) (env reg2)
651 SLW reg1 reg2 ri -> SLW (env reg1) (env reg2) (fixRI ri)
652 SRW reg1 reg2 ri -> SRW (env reg1) (env reg2) (fixRI ri)
653 SRAW reg1 reg2 ri -> SRAW (env reg1) (env reg2) (fixRI ri)
654 RLWINM reg1 reg2 sh mb me
655 -> RLWINM (env reg1) (env reg2) sh mb me
656 FADD sz r1 r2 r3 -> FADD sz (env r1) (env r2) (env r3)
657 FSUB sz r1 r2 r3 -> FSUB sz (env r1) (env r2) (env r3)
658 FMUL sz r1 r2 r3 -> FMUL sz (env r1) (env r2) (env r3)
659 FDIV sz r1 r2 r3 -> FDIV sz (env r1) (env r2) (env r3)
660 FNEG r1 r2 -> FNEG (env r1) (env r2)
661 FCMP r1 r2 -> FCMP (env r1) (env r2)
662 FCTIWZ r1 r2 -> FCTIWZ (env r1) (env r2)
663 FRSP r1 r2 -> FRSP (env r1) (env r2)
664 MFCR reg -> MFCR (env reg)
665 MFLR reg -> MFLR (env reg)
666 FETCHPC reg -> FETCHPC (env reg)
669 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
670 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
672 fixRI (RIReg r) = RIReg (env r)
674 #endif /* powerpc_TARGET_ARCH */
676 -- -----------------------------------------------------------------------------
677 -- Detecting reg->reg moves
679 -- The register allocator attempts to eliminate reg->reg moves whenever it can,
680 -- by assigning the src and dest temporaries to the same real register.
682 isRegRegMove :: Instr -> Maybe (Reg,Reg)
683 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
685 isRegRegMove (MOV _ (OpReg r1) (OpReg r2)) = Just (r1,r2)
686 #elif powerpc_TARGET_ARCH
687 isRegRegMove (MR dst src) = Just (src,dst)
689 #warning ToDo: isRegRegMove
691 isRegRegMove _ = Nothing
693 -- -----------------------------------------------------------------------------
694 -- Generating spill instructions
697 :: Reg -- register to spill (should be a real)
698 -> Int -- current stack delta
699 -> Int -- spill slot to use
701 mkSpillInstr reg delta slot
702 = ASSERT(isRealReg reg)
704 off = spillSlotToOffset slot
706 #ifdef alpha_TARGET_ARCH
707 {-Alpha: spill below the stack pointer (?)-}
708 ST sz dyn (spRel (- (off `div` 8)))
710 #ifdef i386_TARGET_ARCH
711 let off_w = (off-delta) `div` 4
712 in case regClass reg of
713 RcInteger -> MOV I32 (OpReg reg) (OpAddr (spRel off_w))
714 _ -> GST F80 reg (spRel off_w) {- RcFloat/RcDouble -}
716 #ifdef x86_64_TARGET_ARCH
717 let off_w = (off-delta) `div` 8
718 in case regClass reg of
719 RcInteger -> MOV I64 (OpReg reg) (OpAddr (spRel off_w))
720 RcDouble -> MOV F64 (OpReg reg) (OpAddr (spRel off_w))
721 -- ToDo: will it work to always spill as a double?
722 -- does that cause a stall if the data was a float?
724 #ifdef sparc_TARGET_ARCH
725 {-SPARC: spill below frame pointer leaving 2 words/spill-}
726 let{off_w = 1 + (off `div` 4);
727 sz = case regClass vreg of {
731 in ST sz dyn (fpRel (- off_w))
733 #ifdef powerpc_TARGET_ARCH
734 let sz = case regClass reg of
737 in ST sz reg (AddrRegImm sp (ImmInt (off-delta)))
742 :: Reg -- register to load (should be a real)
743 -> Int -- current stack delta
744 -> Int -- spill slot to use
746 mkLoadInstr reg delta slot
747 = ASSERT(isRealReg reg)
749 off = spillSlotToOffset slot
751 #if alpha_TARGET_ARCH
752 LD sz dyn (spRel (- (off `div` 8)))
755 let off_w = (off-delta) `div` 4
756 in case regClass reg of {
757 RcInteger -> MOV I32 (OpAddr (spRel off_w)) (OpReg reg);
758 _ -> GLD F80 (spRel off_w) reg} {- RcFloat/RcDouble -}
760 #if x86_64_TARGET_ARCH
761 let off_w = (off-delta) `div` 8
762 in case regClass reg of
763 RcInteger -> MOV I64 (OpAddr (spRel off_w)) (OpReg reg)
764 _ -> MOV F64 (OpAddr (spRel off_w)) (OpReg reg)
766 #if sparc_TARGET_ARCH
767 let{off_w = 1 + (off `div` 4);
768 sz = case regClass vreg of {
772 in LD sz (fpRel (- off_w)) dyn
774 #if powerpc_TARGET_ARCH
775 let sz = case regClass reg of
778 in LD sz reg (AddrRegImm sp (ImmInt (off-delta)))
783 spillSlotSize = IF_ARCH_i386(12, 8)
786 maxSpillSlots = ((rESERVED_C_STACK_BYTES - 64) `div` spillSlotSize) - 1
788 -- convert a spill slot number to a *byte* offset, with no sign:
789 -- decide on a per arch basis whether you are spilling above or below
790 -- the C stack pointer.
791 spillSlotToOffset :: Int -> Int
792 spillSlotToOffset slot
793 | slot >= 0 && slot < maxSpillSlots
794 = 64 + spillSlotSize * slot
796 = pprPanic "spillSlotToOffset:"
797 (text "invalid spill location: " <> int slot)