1 -----------------------------------------------------------------------------
3 -- Machine-specific parts of the register allocator
5 -- (c) The University of Glasgow 1996-2004
7 -----------------------------------------------------------------------------
9 #include "nativeGen/NCG.h"
24 #include "HsVersions.h"
26 import Cmm ( BlockId )
27 #if powerpc_TARGET_ARCH || i386_TARGET_ARCH
28 import MachOp ( MachRep(..) )
33 import Constants ( rESERVED_C_STACK_BYTES )
36 -- -----------------------------------------------------------------------------
39 -- @regUsage@ returns the sets of src and destination registers used
40 -- by a particular instruction. Machine registers that are
41 -- pre-allocated to stgRegs are filtered out, because they are
42 -- uninteresting from a register allocation standpoint. (We wouldn't
43 -- want them to end up on the free list!) As far as we are concerned,
44 -- the fixed registers simply don't exist (for allocation purposes,
47 -- regUsage doesn't need to do any trickery for jumps and such. Just
48 -- state precisely the regs read and written by that insn. The
49 -- consequences of control flow transfers, as far as register
50 -- allocation goes, are taken care of by the register allocator.
52 data RegUsage = RU [Reg] [Reg]
57 regUsage :: Instr -> RegUsage
59 interesting (VirtualRegI _) = True
60 interesting (VirtualRegHi _) = True
61 interesting (VirtualRegF _) = True
62 interesting (VirtualRegD _) = True
63 interesting (RealReg i) = isFastTrue (freeReg i)
67 regUsage instr = case instr of
68 LD B reg addr -> usage (regAddr addr, [reg, t9])
69 LD Bu reg addr -> usage (regAddr addr, [reg, t9])
70 -- LD W reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
71 -- LD Wu reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
72 LD sz reg addr -> usage (regAddr addr, [reg])
73 LDA reg addr -> usage (regAddr addr, [reg])
74 LDAH reg addr -> usage (regAddr addr, [reg])
75 LDGP reg addr -> usage (regAddr addr, [reg])
76 LDI sz reg imm -> usage ([], [reg])
77 ST B reg addr -> usage (reg : regAddr addr, [t9, t10])
78 -- ST W reg addr -> usage (reg : regAddr addr, [t9, t10]) : UNUSED
79 ST sz reg addr -> usage (reg : regAddr addr, [])
80 CLR reg -> usage ([], [reg])
81 ABS sz ri reg -> usage (regRI ri, [reg])
82 NEG sz ov ri reg -> usage (regRI ri, [reg])
83 ADD sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
84 SADD sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
85 SUB sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
86 SSUB sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
87 MUL sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
88 DIV sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
89 REM sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
90 NOT ri reg -> usage (regRI ri, [reg])
91 AND r1 ar r2 -> usage (r1 : regRI ar, [r2])
92 ANDNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
93 OR r1 ar r2 -> usage (r1 : regRI ar, [r2])
94 ORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
95 XOR r1 ar r2 -> usage (r1 : regRI ar, [r2])
96 XORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
97 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
98 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
99 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
100 ZAP r1 ar r2 -> usage (r1 : regRI ar, [r2])
101 ZAPNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
102 CMP co r1 ar r2 -> usage (r1 : regRI ar, [r2])
103 FCLR reg -> usage ([], [reg])
104 FABS r1 r2 -> usage ([r1], [r2])
105 FNEG sz r1 r2 -> usage ([r1], [r2])
106 FADD sz r1 r2 r3 -> usage ([r1, r2], [r3])
107 FDIV sz r1 r2 r3 -> usage ([r1, r2], [r3])
108 FMUL sz r1 r2 r3 -> usage ([r1, r2], [r3])
109 FSUB sz r1 r2 r3 -> usage ([r1, r2], [r3])
110 CVTxy sz1 sz2 r1 r2 -> usage ([r1], [r2])
111 FCMP sz co r1 r2 r3 -> usage ([r1, r2], [r3])
112 FMOV r1 r2 -> usage ([r1], [r2])
115 -- We assume that all local jumps will be BI/BF/BR. JMP must be out-of-line.
116 BI cond reg lbl -> usage ([reg], [])
117 BF cond reg lbl -> usage ([reg], [])
118 JMP reg addr hint -> RU (mkRegSet (filter interesting (regAddr addr))) freeRegSet
120 BSR _ n -> RU (argRegSet n) callClobberedRegSet
121 JSR reg addr n -> RU (argRegSet n) callClobberedRegSet
126 usage (src, dst) = RU (mkRegSet (filter interesting src))
127 (mkRegSet (filter interesting dst))
129 interesting (FixedReg _) = False
132 regAddr (AddrReg r1) = [r1]
133 regAddr (AddrRegImm r1 _) = [r1]
134 regAddr (AddrImm _) = []
136 regRI (RIReg r) = [r]
139 #endif /* alpha_TARGET_ARCH */
140 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
143 regUsage instr = case instr of
144 MOV sz src dst -> usageRW src dst
145 MOVZxL sz src dst -> usageRW src dst
146 MOVSxL sz src dst -> usageRW src dst
147 LEA sz src dst -> usageRW src dst
148 ADD sz src dst -> usageRM src dst
149 ADC sz src dst -> usageRM src dst
150 SUB sz src dst -> usageRM src dst
151 IMUL sz src dst -> usageRM src dst
152 IMUL64 sd1 sd2 -> mkRU [sd1,sd2] [sd1,sd2]
153 MUL sz src dst -> usageRM src dst
154 DIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
155 IDIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
156 AND sz src dst -> usageRM src dst
157 OR sz src dst -> usageRM src dst
158 XOR sz src dst -> usageRM src dst
159 NOT sz op -> usageM op
160 NEGI sz op -> usageM op
161 SHL sz imm dst -> usageRM imm dst
162 SAR sz imm dst -> usageRM imm dst
163 SHR sz imm dst -> usageRM imm dst
164 BT sz imm src -> mkRU (use_R src) []
166 PUSH sz op -> mkRU (use_R op) []
167 POP sz op -> mkRU [] (def_W op)
168 TEST sz src dst -> mkRU (use_R src ++ use_R dst) []
169 CMP sz src dst -> mkRU (use_R src ++ use_R dst) []
170 SETCC cond op -> mkRU [] (def_W op)
171 JXX cond lbl -> mkRU [] []
172 JMP op -> mkRU (use_R op) []
173 JMP_TBL op ids -> mkRU (use_R op) []
174 CALL (Left imm) -> mkRU [] callClobberedRegs
175 CALL (Right reg) -> mkRU [reg] callClobberedRegs
176 CLTD -> mkRU [eax] [edx]
179 GMOV src dst -> mkRU [src] [dst]
180 GLD sz src dst -> mkRU (use_EA src) [dst]
181 GST sz src dst -> mkRU (src : use_EA dst) []
183 GLDZ dst -> mkRU [] [dst]
184 GLD1 dst -> mkRU [] [dst]
186 GFTOI src dst -> mkRU [src] [dst]
187 GDTOI src dst -> mkRU [src] [dst]
189 GITOF src dst -> mkRU [src] [dst]
190 GITOD src dst -> mkRU [src] [dst]
192 GADD sz s1 s2 dst -> mkRU [s1,s2] [dst]
193 GSUB sz s1 s2 dst -> mkRU [s1,s2] [dst]
194 GMUL sz s1 s2 dst -> mkRU [s1,s2] [dst]
195 GDIV sz s1 s2 dst -> mkRU [s1,s2] [dst]
197 GCMP sz src1 src2 -> mkRU [src1,src2] []
198 GABS sz src dst -> mkRU [src] [dst]
199 GNEG sz src dst -> mkRU [src] [dst]
200 GSQRT sz src dst -> mkRU [src] [dst]
201 GSIN sz src dst -> mkRU [src] [dst]
202 GCOS sz src dst -> mkRU [src] [dst]
203 GTAN sz src dst -> mkRU [src] [dst]
205 FETCHGOT reg -> mkRU [] [reg]
210 _other -> panic "regUsage: unrecognised instr"
213 -- 2 operand form; first operand Read; second Written
214 usageRW :: Operand -> Operand -> RegUsage
215 usageRW op (OpReg reg) = mkRU (use_R op) [reg]
216 usageRW op (OpAddr ea) = mkRU (use_R op ++ use_EA ea) []
218 -- 2 operand form; first operand Read; second Modified
219 usageRM :: Operand -> Operand -> RegUsage
220 usageRM op (OpReg reg) = mkRU (use_R op ++ [reg]) [reg]
221 usageRM op (OpAddr ea) = mkRU (use_R op ++ use_EA ea) []
223 -- 1 operand form; operand Modified
224 usageM :: Operand -> RegUsage
225 usageM (OpReg reg) = mkRU [reg] [reg]
226 usageM (OpAddr ea) = mkRU (use_EA ea) []
228 -- Registers defd when an operand is written.
229 def_W (OpReg reg) = [reg]
230 def_W (OpAddr ea) = []
232 -- Registers used when an operand is read.
233 use_R (OpReg reg) = [reg]
234 use_R (OpImm imm) = []
235 use_R (OpAddr ea) = use_EA ea
237 -- Registers used to compute an effective address.
238 use_EA (ImmAddr _ _) = []
239 use_EA (AddrBaseIndex Nothing Nothing _) = []
240 use_EA (AddrBaseIndex (Just b) Nothing _) = [b]
241 use_EA (AddrBaseIndex Nothing (Just (i,_)) _) = [i]
242 use_EA (AddrBaseIndex (Just b) (Just (i,_)) _) = [b,i]
244 mkRU src dst = RU (filter interesting src)
245 (filter interesting dst)
247 #endif /* i386_TARGET_ARCH */
248 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
249 #if sparc_TARGET_ARCH
251 regUsage instr = case instr of
252 LD sz addr reg -> usage (regAddr addr, [reg])
253 ST sz reg addr -> usage (reg : regAddr addr, [])
254 ADD x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
255 SUB x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
256 UMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
257 SMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
258 RDY rd -> usage ([], [rd])
259 AND b r1 ar r2 -> usage (r1 : regRI ar, [r2])
260 ANDN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
261 OR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
262 ORN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
263 XOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
264 XNOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
265 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
266 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
267 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
268 SETHI imm reg -> usage ([], [reg])
269 FABS s r1 r2 -> usage ([r1], [r2])
270 FADD s r1 r2 r3 -> usage ([r1, r2], [r3])
271 FCMP e s r1 r2 -> usage ([r1, r2], [])
272 FDIV s r1 r2 r3 -> usage ([r1, r2], [r3])
273 FMOV s r1 r2 -> usage ([r1], [r2])
274 FMUL s r1 r2 r3 -> usage ([r1, r2], [r3])
275 FNEG s r1 r2 -> usage ([r1], [r2])
276 FSQRT s r1 r2 -> usage ([r1], [r2])
277 FSUB s r1 r2 r3 -> usage ([r1, r2], [r3])
278 FxTOy s1 s2 r1 r2 -> usage ([r1], [r2])
280 -- We assume that all local jumps will be BI/BF. JMP must be out-of-line.
281 JMP dst addr -> usage (regAddr addr, [])
283 CALL (Left imm) n True -> noUsage
284 CALL (Left imm) n False -> usage (argRegs n, callClobberedRegs)
285 CALL (Right reg) n True -> usage ([reg], [])
286 CALL (Right reg) n False -> usage (reg : (argRegs n), callClobberedRegs)
290 usage (src, dst) = RU (regSetFromList (filter interesting src))
291 (regSetFromList (filter interesting dst))
293 regAddr (AddrRegReg r1 r2) = [r1, r2]
294 regAddr (AddrRegImm r1 _) = [r1]
296 regRI (RIReg r) = [r]
299 #endif /* sparc_TARGET_ARCH */
300 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
301 #if powerpc_TARGET_ARCH
303 regUsage instr = case instr of
304 LD sz reg addr -> usage (regAddr addr, [reg])
305 LA sz reg addr -> usage (regAddr addr, [reg])
306 ST sz reg addr -> usage (reg : regAddr addr, [])
307 STU sz reg addr -> usage (reg : regAddr addr, [])
308 LIS reg imm -> usage ([], [reg])
309 LI reg imm -> usage ([], [reg])
310 MR reg1 reg2 -> usage ([reg2], [reg1])
311 CMP sz reg ri -> usage (reg : regRI ri,[])
312 CMPL sz reg ri -> usage (reg : regRI ri,[])
313 BCC cond lbl -> noUsage
314 MTCTR reg -> usage ([reg],[])
315 BCTR targets -> noUsage
316 BL imm params -> usage (params, callClobberedRegs)
317 BCTRL params -> usage (params, callClobberedRegs)
318 ADD reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
319 ADDC reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
320 ADDE reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
321 ADDIS reg1 reg2 imm -> usage ([reg2], [reg1])
322 SUBF reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
323 MULLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
324 DIVW reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
325 DIVWU reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
326 MULLW_MayOflo reg1 reg2 reg3
327 -> usage ([reg2,reg3], [reg1])
328 AND reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
329 OR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
330 XOR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
331 XORIS reg1 reg2 imm -> usage ([reg2], [reg1])
332 EXTS siz reg1 reg2 -> usage ([reg2], [reg1])
333 NEG reg1 reg2 -> usage ([reg2], [reg1])
334 NOT reg1 reg2 -> usage ([reg2], [reg1])
335 SLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
336 SRW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
337 SRAW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
338 RLWINM reg1 reg2 sh mb me
339 -> usage ([reg2], [reg1])
340 FADD sz r1 r2 r3 -> usage ([r2,r3], [r1])
341 FSUB sz r1 r2 r3 -> usage ([r2,r3], [r1])
342 FMUL sz r1 r2 r3 -> usage ([r2,r3], [r1])
343 FDIV sz r1 r2 r3 -> usage ([r2,r3], [r1])
344 FNEG r1 r2 -> usage ([r2], [r1])
345 FCMP r1 r2 -> usage ([r1,r2], [])
346 FCTIWZ r1 r2 -> usage ([r2], [r1])
347 FRSP r1 r2 -> usage ([r2], [r1])
348 MFCR reg -> usage ([], [reg])
349 MFLR reg -> usage ([], [reg])
350 FETCHPC reg -> usage ([], [reg])
353 usage (src, dst) = RU (filter interesting src)
354 (filter interesting dst)
355 regAddr (AddrRegReg r1 r2) = [r1, r2]
356 regAddr (AddrRegImm r1 _) = [r1]
358 regRI (RIReg r) = [r]
360 #endif /* powerpc_TARGET_ARCH */
363 -- -----------------------------------------------------------------------------
364 -- Determine the possible destinations from the current instruction.
366 -- (we always assume that the next instruction is also a valid destination;
367 -- if this isn't the case then the jump should be at the end of the basic
370 jumpDests :: Instr -> [BlockId] -> [BlockId]
375 JMP_TBL _ ids -> ids ++ acc
376 #elif powerpc_TARGET_ARCH
378 BCTR targets -> targets ++ acc
383 -- -----------------------------------------------------------------------------
384 -- 'patchRegs' function
386 -- 'patchRegs' takes an instruction and applies the given mapping to
387 -- all the register references.
389 patchRegs :: Instr -> (Reg -> Reg) -> Instr
391 #if alpha_TARGET_ARCH
393 patchRegs instr env = case instr of
394 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
395 LDA reg addr -> LDA (env reg) (fixAddr addr)
396 LDAH reg addr -> LDAH (env reg) (fixAddr addr)
397 LDGP reg addr -> LDGP (env reg) (fixAddr addr)
398 LDI sz reg imm -> LDI sz (env reg) imm
399 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
400 CLR reg -> CLR (env reg)
401 ABS sz ar reg -> ABS sz (fixRI ar) (env reg)
402 NEG sz ov ar reg -> NEG sz ov (fixRI ar) (env reg)
403 ADD sz ov r1 ar r2 -> ADD sz ov (env r1) (fixRI ar) (env r2)
404 SADD sz sc r1 ar r2 -> SADD sz sc (env r1) (fixRI ar) (env r2)
405 SUB sz ov r1 ar r2 -> SUB sz ov (env r1) (fixRI ar) (env r2)
406 SSUB sz sc r1 ar r2 -> SSUB sz sc (env r1) (fixRI ar) (env r2)
407 MUL sz ov r1 ar r2 -> MUL sz ov (env r1) (fixRI ar) (env r2)
408 DIV sz un r1 ar r2 -> DIV sz un (env r1) (fixRI ar) (env r2)
409 REM sz un r1 ar r2 -> REM sz un (env r1) (fixRI ar) (env r2)
410 NOT ar reg -> NOT (fixRI ar) (env reg)
411 AND r1 ar r2 -> AND (env r1) (fixRI ar) (env r2)
412 ANDNOT r1 ar r2 -> ANDNOT (env r1) (fixRI ar) (env r2)
413 OR r1 ar r2 -> OR (env r1) (fixRI ar) (env r2)
414 ORNOT r1 ar r2 -> ORNOT (env r1) (fixRI ar) (env r2)
415 XOR r1 ar r2 -> XOR (env r1) (fixRI ar) (env r2)
416 XORNOT r1 ar r2 -> XORNOT (env r1) (fixRI ar) (env r2)
417 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
418 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
419 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
420 ZAP r1 ar r2 -> ZAP (env r1) (fixRI ar) (env r2)
421 ZAPNOT r1 ar r2 -> ZAPNOT (env r1) (fixRI ar) (env r2)
422 CMP co r1 ar r2 -> CMP co (env r1) (fixRI ar) (env r2)
423 FCLR reg -> FCLR (env reg)
424 FABS r1 r2 -> FABS (env r1) (env r2)
425 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
426 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
427 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
428 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
429 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
430 CVTxy s1 s2 r1 r2 -> CVTxy s1 s2 (env r1) (env r2)
431 FCMP s co r1 r2 r3 -> FCMP s co (env r1) (env r2) (env r3)
432 FMOV r1 r2 -> FMOV (env r1) (env r2)
433 BI cond reg lbl -> BI cond (env reg) lbl
434 BF cond reg lbl -> BF cond (env reg) lbl
435 JMP reg addr hint -> JMP (env reg) (fixAddr addr) hint
436 JSR reg addr i -> JSR (env reg) (fixAddr addr) i
439 fixAddr (AddrReg r1) = AddrReg (env r1)
440 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
441 fixAddr other = other
443 fixRI (RIReg r) = RIReg (env r)
446 #endif /* alpha_TARGET_ARCH */
447 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
450 patchRegs instr env = case instr of
451 MOV sz src dst -> patch2 (MOV sz) src dst
452 MOVZxL sz src dst -> patch2 (MOVZxL sz) src dst
453 MOVSxL sz src dst -> patch2 (MOVSxL sz) src dst
454 LEA sz src dst -> patch2 (LEA sz) src dst
455 ADD sz src dst -> patch2 (ADD sz) src dst
456 ADC sz src dst -> patch2 (ADC sz) src dst
457 SUB sz src dst -> patch2 (SUB sz) src dst
458 IMUL sz src dst -> patch2 (IMUL sz) src dst
459 IMUL64 sd1 sd2 -> IMUL64 (env sd1) (env sd2)
460 MUL sz src dst -> patch2 (MUL sz) src dst
461 IDIV sz op -> patch1 (IDIV sz) op
462 DIV sz op -> patch1 (DIV sz) op
463 AND sz src dst -> patch2 (AND sz) src dst
464 OR sz src dst -> patch2 (OR sz) src dst
465 XOR sz src dst -> patch2 (XOR sz) src dst
466 NOT sz op -> patch1 (NOT sz) op
467 NEGI sz op -> patch1 (NEGI sz) op
468 SHL sz imm dst -> patch1 (SHL sz imm) dst
469 SAR sz imm dst -> patch1 (SAR sz imm) dst
470 SHR sz imm dst -> patch1 (SHR sz imm) dst
471 BT sz imm src -> patch1 (BT sz imm) src
472 TEST sz src dst -> patch2 (TEST sz) src dst
473 CMP sz src dst -> patch2 (CMP sz) src dst
474 PUSH sz op -> patch1 (PUSH sz) op
475 POP sz op -> patch1 (POP sz) op
476 SETCC cond op -> patch1 (SETCC cond) op
477 JMP op -> patch1 JMP op
478 JMP_TBL op ids -> patch1 JMP_TBL op $ ids
480 GMOV src dst -> GMOV (env src) (env dst)
481 GLD sz src dst -> GLD sz (lookupAddr src) (env dst)
482 GST sz src dst -> GST sz (env src) (lookupAddr dst)
484 GLDZ dst -> GLDZ (env dst)
485 GLD1 dst -> GLD1 (env dst)
487 GFTOI src dst -> GFTOI (env src) (env dst)
488 GDTOI src dst -> GDTOI (env src) (env dst)
490 GITOF src dst -> GITOF (env src) (env dst)
491 GITOD src dst -> GITOD (env src) (env dst)
493 GADD sz s1 s2 dst -> GADD sz (env s1) (env s2) (env dst)
494 GSUB sz s1 s2 dst -> GSUB sz (env s1) (env s2) (env dst)
495 GMUL sz s1 s2 dst -> GMUL sz (env s1) (env s2) (env dst)
496 GDIV sz s1 s2 dst -> GDIV sz (env s1) (env s2) (env dst)
498 GCMP sz src1 src2 -> GCMP sz (env src1) (env src2)
499 GABS sz src dst -> GABS sz (env src) (env dst)
500 GNEG sz src dst -> GNEG sz (env src) (env dst)
501 GSQRT sz src dst -> GSQRT sz (env src) (env dst)
502 GSIN sz src dst -> GSIN sz (env src) (env dst)
503 GCOS sz src dst -> GCOS sz (env src) (env dst)
504 GTAN sz src dst -> GTAN sz (env src) (env dst)
506 CALL (Left imm) -> instr
507 CALL (Right reg) -> CALL (Right (env reg))
509 FETCHGOT reg -> FETCHGOT (env reg)
517 _other -> panic "patchRegs: unrecognised instr"
520 patch1 insn op = insn $! patchOp op
521 patch2 insn src dst = (insn $! patchOp src) $! patchOp dst
523 patchOp (OpReg reg) = OpReg (env reg)
524 patchOp (OpImm imm) = OpImm imm
525 patchOp (OpAddr ea) = OpAddr (lookupAddr ea)
527 lookupAddr (ImmAddr imm off) = ImmAddr imm off
528 lookupAddr (AddrBaseIndex base index disp)
529 = AddrBaseIndex (lookupBase base) (lookupIndex index) disp
531 lookupBase Nothing = Nothing
532 lookupBase (Just r) = Just (env r)
534 lookupIndex Nothing = Nothing
535 lookupIndex (Just (r,i)) = Just (env r, i)
537 #endif /* i386_TARGET_ARCH */
538 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
539 #if sparc_TARGET_ARCH
541 patchRegs instr env = case instr of
542 LD sz addr reg -> LD sz (fixAddr addr) (env reg)
543 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
544 ADD x cc r1 ar r2 -> ADD x cc (env r1) (fixRI ar) (env r2)
545 SUB x cc r1 ar r2 -> SUB x cc (env r1) (fixRI ar) (env r2)
546 UMUL cc r1 ar r2 -> UMUL cc (env r1) (fixRI ar) (env r2)
547 SMUL cc r1 ar r2 -> SMUL cc (env r1) (fixRI ar) (env r2)
548 RDY rd -> RDY (env rd)
549 AND b r1 ar r2 -> AND b (env r1) (fixRI ar) (env r2)
550 ANDN b r1 ar r2 -> ANDN b (env r1) (fixRI ar) (env r2)
551 OR b r1 ar r2 -> OR b (env r1) (fixRI ar) (env r2)
552 ORN b r1 ar r2 -> ORN b (env r1) (fixRI ar) (env r2)
553 XOR b r1 ar r2 -> XOR b (env r1) (fixRI ar) (env r2)
554 XNOR b r1 ar r2 -> XNOR b (env r1) (fixRI ar) (env r2)
555 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
556 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
557 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
558 SETHI imm reg -> SETHI imm (env reg)
559 FABS s r1 r2 -> FABS s (env r1) (env r2)
560 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
561 FCMP e s r1 r2 -> FCMP e s (env r1) (env r2)
562 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
563 FMOV s r1 r2 -> FMOV s (env r1) (env r2)
564 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
565 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
566 FSQRT s r1 r2 -> FSQRT s (env r1) (env r2)
567 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
568 FxTOy s1 s2 r1 r2 -> FxTOy s1 s2 (env r1) (env r2)
569 JMP dsts addr -> JMP dsts (fixAddr addr)
570 CALL (Left i) n t -> CALL (Left i) n t
571 CALL (Right r) n t -> CALL (Right (env r)) n t
574 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
575 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
577 fixRI (RIReg r) = RIReg (env r)
580 #endif /* sparc_TARGET_ARCH */
581 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
582 #if powerpc_TARGET_ARCH
584 patchRegs instr env = case instr of
585 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
586 LA sz reg addr -> LA sz (env reg) (fixAddr addr)
587 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
588 STU sz reg addr -> STU sz (env reg) (fixAddr addr)
589 LIS reg imm -> LIS (env reg) imm
590 LI reg imm -> LI (env reg) imm
591 MR reg1 reg2 -> MR (env reg1) (env reg2)
592 CMP sz reg ri -> CMP sz (env reg) (fixRI ri)
593 CMPL sz reg ri -> CMPL sz (env reg) (fixRI ri)
594 BCC cond lbl -> BCC cond lbl
595 MTCTR reg -> MTCTR (env reg)
596 BCTR targets -> BCTR targets
597 BL imm argRegs -> BL imm argRegs -- argument regs
598 BCTRL argRegs -> BCTRL argRegs -- cannot be remapped
599 ADD reg1 reg2 ri -> ADD (env reg1) (env reg2) (fixRI ri)
600 ADDC reg1 reg2 reg3-> ADDC (env reg1) (env reg2) (env reg3)
601 ADDE reg1 reg2 reg3-> ADDE (env reg1) (env reg2) (env reg3)
602 ADDIS reg1 reg2 imm -> ADDIS (env reg1) (env reg2) imm
603 SUBF reg1 reg2 reg3-> SUBF (env reg1) (env reg2) (env reg3)
604 MULLW reg1 reg2 ri -> MULLW (env reg1) (env reg2) (fixRI ri)
605 DIVW reg1 reg2 reg3-> DIVW (env reg1) (env reg2) (env reg3)
606 DIVWU reg1 reg2 reg3-> DIVWU (env reg1) (env reg2) (env reg3)
607 MULLW_MayOflo reg1 reg2 reg3
608 -> MULLW_MayOflo (env reg1) (env reg2) (env reg3)
609 AND reg1 reg2 ri -> AND (env reg1) (env reg2) (fixRI ri)
610 OR reg1 reg2 ri -> OR (env reg1) (env reg2) (fixRI ri)
611 XOR reg1 reg2 ri -> XOR (env reg1) (env reg2) (fixRI ri)
612 XORIS reg1 reg2 imm -> XORIS (env reg1) (env reg2) imm
613 EXTS sz reg1 reg2 -> EXTS sz (env reg1) (env reg2)
614 NEG reg1 reg2 -> NEG (env reg1) (env reg2)
615 NOT reg1 reg2 -> NOT (env reg1) (env reg2)
616 SLW reg1 reg2 ri -> SLW (env reg1) (env reg2) (fixRI ri)
617 SRW reg1 reg2 ri -> SRW (env reg1) (env reg2) (fixRI ri)
618 SRAW reg1 reg2 ri -> SRAW (env reg1) (env reg2) (fixRI ri)
619 RLWINM reg1 reg2 sh mb me
620 -> RLWINM (env reg1) (env reg2) sh mb me
621 FADD sz r1 r2 r3 -> FADD sz (env r1) (env r2) (env r3)
622 FSUB sz r1 r2 r3 -> FSUB sz (env r1) (env r2) (env r3)
623 FMUL sz r1 r2 r3 -> FMUL sz (env r1) (env r2) (env r3)
624 FDIV sz r1 r2 r3 -> FDIV sz (env r1) (env r2) (env r3)
625 FNEG r1 r2 -> FNEG (env r1) (env r2)
626 FCMP r1 r2 -> FCMP (env r1) (env r2)
627 FCTIWZ r1 r2 -> FCTIWZ (env r1) (env r2)
628 FRSP r1 r2 -> FRSP (env r1) (env r2)
629 MFCR reg -> MFCR (env reg)
630 MFLR reg -> MFLR (env reg)
631 FETCHPC reg -> FETCHPC (env reg)
634 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
635 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
637 fixRI (RIReg r) = RIReg (env r)
639 #endif /* powerpc_TARGET_ARCH */
641 -- -----------------------------------------------------------------------------
642 -- Detecting reg->reg moves
644 -- The register allocator attempts to eliminate reg->reg moves whenever it can,
645 -- by assigning the src and dest temporaries to the same real register.
647 isRegRegMove :: Instr -> Maybe (Reg,Reg)
648 #ifdef i386_TARGET_ARCH
650 isRegRegMove (MOV _ (OpReg r1) (OpReg r2)) = Just (r1,r2)
651 #elif powerpc_TARGET_ARCH
652 isRegRegMove (MR dst src) = Just (src,dst)
654 #warning ToDo: isRegRegMove
656 isRegRegMove _ = Nothing
658 -- -----------------------------------------------------------------------------
659 -- Generating spill instructions
662 :: Reg -- register to spill (should be a real)
663 -> Int -- current stack delta
664 -> Int -- spill slot to use
666 mkSpillInstr reg delta slot
667 = ASSERT(isRealReg reg)
669 off = spillSlotToOffset slot
671 #ifdef alpha_TARGET_ARCH
672 {-Alpha: spill below the stack pointer (?)-}
673 ST sz dyn (spRel (- (off `div` 8)))
675 #ifdef i386_TARGET_ARCH
676 let off_w = (off-delta) `div` 4
677 in case regClass reg of
678 RcInteger -> MOV I32 (OpReg reg) (OpAddr (spRel off_w))
679 _ -> GST F80 reg (spRel off_w) {- RcFloat/RcDouble -}
681 #ifdef sparc_TARGET_ARCH
682 {-SPARC: spill below frame pointer leaving 2 words/spill-}
683 let{off_w = 1 + (off `div` 4);
684 sz = case regClass vreg of {
688 in ST sz dyn (fpRel (- off_w))
690 #ifdef powerpc_TARGET_ARCH
691 let sz = case regClass reg of
694 in ST sz reg (AddrRegImm sp (ImmInt (off-delta)))
699 :: Reg -- register to load (should be a real)
700 -> Int -- current stack delta
701 -> Int -- spill slot to use
703 mkLoadInstr reg delta slot
704 = ASSERT(isRealReg reg)
706 off = spillSlotToOffset slot
708 #ifdef alpha_TARGET_ARCH
709 LD sz dyn (spRel (- (off `div` 8)))
711 #ifdef i386_TARGET_ARCH
712 let off_w = (off-delta) `div` 4
713 in case regClass reg of {
714 RcInteger -> MOV I32 (OpAddr (spRel off_w)) (OpReg reg);
715 _ -> GLD F80 (spRel off_w) reg} {- RcFloat/RcDouble -}
717 #ifdef sparc_TARGET_ARCH
718 let{off_w = 1 + (off `div` 4);
719 sz = case regClass vreg of {
723 in LD sz (fpRel (- off_w)) dyn
725 #ifdef powerpc_TARGET_ARCH
726 let sz = case regClass reg of
729 in LD sz reg (AddrRegImm sp (ImmInt (off-delta)))
734 spillSlotSize = IF_ARCH_i386(12, 8)
737 maxSpillSlots = ((rESERVED_C_STACK_BYTES - 64) `div` spillSlotSize) - 1
739 -- convert a spill slot number to a *byte* offset, with no sign:
740 -- decide on a per arch basis whether you are spilling above or below
741 -- the C stack pointer.
742 spillSlotToOffset :: Int -> Int
743 spillSlotToOffset slot
744 | slot >= 0 && slot < maxSpillSlots
745 = 64 + spillSlotSize * slot
747 = pprPanic "spillSlotToOffset:"
748 (text "invalid spill location: " <> int slot)