1 -----------------------------------------------------------------------------
3 -- Machine-specific parts of the register allocator
5 -- (c) The University of Glasgow 1996-2004
7 -----------------------------------------------------------------------------
9 #include "nativeGen/NCG.h"
24 #include "HsVersions.h"
26 import Cmm ( BlockId )
27 #if powerpc_TARGET_ARCH || i386_TARGET_ARCH || x86_64_TARGET_ARCH
28 import MachOp ( MachRep(..) )
33 import Constants ( rESERVED_C_STACK_BYTES )
36 -- -----------------------------------------------------------------------------
39 -- @regUsage@ returns the sets of src and destination registers used
40 -- by a particular instruction. Machine registers that are
41 -- pre-allocated to stgRegs are filtered out, because they are
42 -- uninteresting from a register allocation standpoint. (We wouldn't
43 -- want them to end up on the free list!) As far as we are concerned,
44 -- the fixed registers simply don't exist (for allocation purposes,
47 -- regUsage doesn't need to do any trickery for jumps and such. Just
48 -- state precisely the regs read and written by that insn. The
49 -- consequences of control flow transfers, as far as register
50 -- allocation goes, are taken care of by the register allocator.
52 data RegUsage = RU [Reg] [Reg]
57 regUsage :: Instr -> RegUsage
59 interesting (VirtualRegI _) = True
60 interesting (VirtualRegHi _) = True
61 interesting (VirtualRegF _) = True
62 interesting (VirtualRegD _) = True
63 interesting (RealReg i) = isFastTrue (freeReg i)
67 regUsage instr = case instr of
68 LD B reg addr -> usage (regAddr addr, [reg, t9])
69 LD Bu reg addr -> usage (regAddr addr, [reg, t9])
70 -- LD W reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
71 -- LD Wu reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
72 LD sz reg addr -> usage (regAddr addr, [reg])
73 LDA reg addr -> usage (regAddr addr, [reg])
74 LDAH reg addr -> usage (regAddr addr, [reg])
75 LDGP reg addr -> usage (regAddr addr, [reg])
76 LDI sz reg imm -> usage ([], [reg])
77 ST B reg addr -> usage (reg : regAddr addr, [t9, t10])
78 -- ST W reg addr -> usage (reg : regAddr addr, [t9, t10]) : UNUSED
79 ST sz reg addr -> usage (reg : regAddr addr, [])
80 CLR reg -> usage ([], [reg])
81 ABS sz ri reg -> usage (regRI ri, [reg])
82 NEG sz ov ri reg -> usage (regRI ri, [reg])
83 ADD sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
84 SADD sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
85 SUB sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
86 SSUB sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
87 MUL sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
88 DIV sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
89 REM sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
90 NOT ri reg -> usage (regRI ri, [reg])
91 AND r1 ar r2 -> usage (r1 : regRI ar, [r2])
92 ANDNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
93 OR r1 ar r2 -> usage (r1 : regRI ar, [r2])
94 ORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
95 XOR r1 ar r2 -> usage (r1 : regRI ar, [r2])
96 XORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
97 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
98 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
99 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
100 ZAP r1 ar r2 -> usage (r1 : regRI ar, [r2])
101 ZAPNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
102 CMP co r1 ar r2 -> usage (r1 : regRI ar, [r2])
103 FCLR reg -> usage ([], [reg])
104 FABS r1 r2 -> usage ([r1], [r2])
105 FNEG sz r1 r2 -> usage ([r1], [r2])
106 FADD sz r1 r2 r3 -> usage ([r1, r2], [r3])
107 FDIV sz r1 r2 r3 -> usage ([r1, r2], [r3])
108 FMUL sz r1 r2 r3 -> usage ([r1, r2], [r3])
109 FSUB sz r1 r2 r3 -> usage ([r1, r2], [r3])
110 CVTxy sz1 sz2 r1 r2 -> usage ([r1], [r2])
111 FCMP sz co r1 r2 r3 -> usage ([r1, r2], [r3])
112 FMOV r1 r2 -> usage ([r1], [r2])
115 -- We assume that all local jumps will be BI/BF/BR. JMP must be out-of-line.
116 BI cond reg lbl -> usage ([reg], [])
117 BF cond reg lbl -> usage ([reg], [])
118 JMP reg addr hint -> RU (mkRegSet (filter interesting (regAddr addr))) freeRegSet
120 BSR _ n -> RU (argRegSet n) callClobberedRegSet
121 JSR reg addr n -> RU (argRegSet n) callClobberedRegSet
126 usage (src, dst) = RU (mkRegSet (filter interesting src))
127 (mkRegSet (filter interesting dst))
129 interesting (FixedReg _) = False
132 regAddr (AddrReg r1) = [r1]
133 regAddr (AddrRegImm r1 _) = [r1]
134 regAddr (AddrImm _) = []
136 regRI (RIReg r) = [r]
139 #endif /* alpha_TARGET_ARCH */
140 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
141 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
143 regUsage instr = case instr of
144 MOV sz src dst -> usageRW src dst
145 MOVZxL sz src dst -> usageRW src dst
146 MOVSxL sz src dst -> usageRW src dst
147 LEA sz src dst -> usageRW src dst
148 ADD sz src dst -> usageRM src dst
149 ADC sz src dst -> usageRM src dst
150 SUB sz src dst -> usageRM src dst
151 IMUL sz src dst -> usageRM src dst
152 IMUL2 sz src -> mkRU (eax:use_R src) [eax,edx]
153 MUL sz src dst -> usageRM src dst
154 DIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
155 IDIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
156 AND sz src dst -> usageRM src dst
157 OR sz src dst -> usageRM src dst
158 XOR sz src dst -> usageRM src dst
159 NOT sz op -> usageM op
160 NEGI sz op -> usageM op
161 SHL sz imm dst -> usageRM imm dst
162 SAR sz imm dst -> usageRM imm dst
163 SHR sz imm dst -> usageRM imm dst
164 BT sz imm src -> mkRU (use_R src) []
166 PUSH sz op -> mkRU (use_R op) []
167 POP sz op -> mkRU [] (def_W op)
168 TEST sz src dst -> mkRU (use_R src ++ use_R dst) []
169 CMP sz src dst -> mkRU (use_R src ++ use_R dst) []
170 SETCC cond op -> mkRU [] (def_W op)
171 JXX cond lbl -> mkRU [] []
172 JMP op -> mkRU (use_R op) []
173 JMP_TBL op ids -> mkRU (use_R op) []
175 CALL (Left imm) -> mkRU [] callClobberedRegs
176 CALL (Right reg) -> mkRU [reg] callClobberedRegs
178 CALL (Left imm) -> mkRU params callClobberedRegs
179 CALL (Right reg) -> mkRU (reg:params) callClobberedRegs
181 CLTD sz -> mkRU [eax] [edx]
185 GMOV src dst -> mkRU [src] [dst]
186 GLD sz src dst -> mkRU (use_EA src) [dst]
187 GST sz src dst -> mkRU (src : use_EA dst) []
189 GLDZ dst -> mkRU [] [dst]
190 GLD1 dst -> mkRU [] [dst]
192 GFTOI src dst -> mkRU [src] [dst]
193 GDTOI src dst -> mkRU [src] [dst]
195 GITOF src dst -> mkRU [src] [dst]
196 GITOD src dst -> mkRU [src] [dst]
198 GADD sz s1 s2 dst -> mkRU [s1,s2] [dst]
199 GSUB sz s1 s2 dst -> mkRU [s1,s2] [dst]
200 GMUL sz s1 s2 dst -> mkRU [s1,s2] [dst]
201 GDIV sz s1 s2 dst -> mkRU [s1,s2] [dst]
203 GCMP sz src1 src2 -> mkRU [src1,src2] []
204 GABS sz src dst -> mkRU [src] [dst]
205 GNEG sz src dst -> mkRU [src] [dst]
206 GSQRT sz src dst -> mkRU [src] [dst]
207 GSIN sz src dst -> mkRU [src] [dst]
208 GCOS sz src dst -> mkRU [src] [dst]
209 GTAN sz src dst -> mkRU [src] [dst]
212 #if x86_64_TARGET_ARCH
213 CVTSS2SD src dst -> mkRU [src] [dst]
214 CVTSD2SS src dst -> mkRU [src] [dst]
215 CVTSS2SI src dst -> mkRU (use_R src) [dst]
216 CVTSD2SI src dst -> mkRU (use_R src) [dst]
217 CVTSI2SS src dst -> mkRU (use_R src) [dst]
218 CVTSI2SD src dst -> mkRU (use_R src) [dst]
219 FDIV sz src dst -> usageRM src dst
222 FETCHGOT reg -> mkRU [] [reg]
227 _other -> panic "regUsage: unrecognised instr"
230 #if x86_64_TARGET_ARCH
231 -- call parameters: include %eax, because it is used
232 -- to pass the number of SSE reg arguments to varargs fns.
233 params = eax : allArgRegs ++ allFPArgRegs
236 -- 2 operand form; first operand Read; second Written
237 usageRW :: Operand -> Operand -> RegUsage
238 usageRW op (OpReg reg) = mkRU (use_R op) [reg]
239 usageRW op (OpAddr ea) = mkRU (use_R op ++ use_EA ea) []
241 -- 2 operand form; first operand Read; second Modified
242 usageRM :: Operand -> Operand -> RegUsage
243 usageRM op (OpReg reg) = mkRU (use_R op ++ [reg]) [reg]
244 usageRM op (OpAddr ea) = mkRU (use_R op ++ use_EA ea) []
246 -- 1 operand form; operand Modified
247 usageM :: Operand -> RegUsage
248 usageM (OpReg reg) = mkRU [reg] [reg]
249 usageM (OpAddr ea) = mkRU (use_EA ea) []
251 -- Registers defd when an operand is written.
252 def_W (OpReg reg) = [reg]
253 def_W (OpAddr ea) = []
255 -- Registers used when an operand is read.
256 use_R (OpReg reg) = [reg]
257 use_R (OpImm imm) = []
258 use_R (OpAddr ea) = use_EA ea
260 -- Registers used to compute an effective address.
261 use_EA (ImmAddr _ _) = []
262 use_EA (AddrBaseIndex base index _) =
263 use_base base $! use_index index
264 where use_base (EABaseReg r) x = r : x
266 use_index EAIndexNone = []
267 use_index (EAIndex i _) = [i]
269 mkRU src dst = RU (filter interesting src)
270 (filter interesting dst)
272 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH */
273 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
274 #if sparc_TARGET_ARCH
276 regUsage instr = case instr of
277 LD sz addr reg -> usage (regAddr addr, [reg])
278 ST sz reg addr -> usage (reg : regAddr addr, [])
279 ADD x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
280 SUB x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
281 UMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
282 SMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
283 RDY rd -> usage ([], [rd])
284 AND b r1 ar r2 -> usage (r1 : regRI ar, [r2])
285 ANDN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
286 OR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
287 ORN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
288 XOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
289 XNOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
290 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
291 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
292 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
293 SETHI imm reg -> usage ([], [reg])
294 FABS s r1 r2 -> usage ([r1], [r2])
295 FADD s r1 r2 r3 -> usage ([r1, r2], [r3])
296 FCMP e s r1 r2 -> usage ([r1, r2], [])
297 FDIV s r1 r2 r3 -> usage ([r1, r2], [r3])
298 FMOV s r1 r2 -> usage ([r1], [r2])
299 FMUL s r1 r2 r3 -> usage ([r1, r2], [r3])
300 FNEG s r1 r2 -> usage ([r1], [r2])
301 FSQRT s r1 r2 -> usage ([r1], [r2])
302 FSUB s r1 r2 r3 -> usage ([r1, r2], [r3])
303 FxTOy s1 s2 r1 r2 -> usage ([r1], [r2])
305 -- We assume that all local jumps will be BI/BF. JMP must be out-of-line.
306 JMP dst addr -> usage (regAddr addr, [])
308 CALL (Left imm) n True -> noUsage
309 CALL (Left imm) n False -> usage (argRegs n, callClobberedRegs)
310 CALL (Right reg) n True -> usage ([reg], [])
311 CALL (Right reg) n False -> usage (reg : (argRegs n), callClobberedRegs)
315 usage (src, dst) = RU (regSetFromList (filter interesting src))
316 (regSetFromList (filter interesting dst))
318 regAddr (AddrRegReg r1 r2) = [r1, r2]
319 regAddr (AddrRegImm r1 _) = [r1]
321 regRI (RIReg r) = [r]
324 #endif /* sparc_TARGET_ARCH */
325 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
326 #if powerpc_TARGET_ARCH
328 regUsage instr = case instr of
329 LD sz reg addr -> usage (regAddr addr, [reg])
330 LA sz reg addr -> usage (regAddr addr, [reg])
331 ST sz reg addr -> usage (reg : regAddr addr, [])
332 STU sz reg addr -> usage (reg : regAddr addr, [])
333 LIS reg imm -> usage ([], [reg])
334 LI reg imm -> usage ([], [reg])
335 MR reg1 reg2 -> usage ([reg2], [reg1])
336 CMP sz reg ri -> usage (reg : regRI ri,[])
337 CMPL sz reg ri -> usage (reg : regRI ri,[])
338 BCC cond lbl -> noUsage
339 MTCTR reg -> usage ([reg],[])
340 BCTR targets -> noUsage
341 BL imm params -> usage (params, callClobberedRegs)
342 BCTRL params -> usage (params, callClobberedRegs)
343 ADD reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
344 ADDC reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
345 ADDE reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
346 ADDIS reg1 reg2 imm -> usage ([reg2], [reg1])
347 SUBF reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
348 MULLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
349 DIVW reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
350 DIVWU reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
351 MULLW_MayOflo reg1 reg2 reg3
352 -> usage ([reg2,reg3], [reg1])
353 AND reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
354 OR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
355 XOR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
356 XORIS reg1 reg2 imm -> usage ([reg2], [reg1])
357 EXTS siz reg1 reg2 -> usage ([reg2], [reg1])
358 NEG reg1 reg2 -> usage ([reg2], [reg1])
359 NOT reg1 reg2 -> usage ([reg2], [reg1])
360 SLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
361 SRW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
362 SRAW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
363 RLWINM reg1 reg2 sh mb me
364 -> usage ([reg2], [reg1])
365 FADD sz r1 r2 r3 -> usage ([r2,r3], [r1])
366 FSUB sz r1 r2 r3 -> usage ([r2,r3], [r1])
367 FMUL sz r1 r2 r3 -> usage ([r2,r3], [r1])
368 FDIV sz r1 r2 r3 -> usage ([r2,r3], [r1])
369 FNEG r1 r2 -> usage ([r2], [r1])
370 FCMP r1 r2 -> usage ([r1,r2], [])
371 FCTIWZ r1 r2 -> usage ([r2], [r1])
372 FRSP r1 r2 -> usage ([r2], [r1])
373 MFCR reg -> usage ([], [reg])
374 MFLR reg -> usage ([], [reg])
375 FETCHPC reg -> usage ([], [reg])
378 usage (src, dst) = RU (filter interesting src)
379 (filter interesting dst)
380 regAddr (AddrRegReg r1 r2) = [r1, r2]
381 regAddr (AddrRegImm r1 _) = [r1]
383 regRI (RIReg r) = [r]
385 #endif /* powerpc_TARGET_ARCH */
388 -- -----------------------------------------------------------------------------
389 -- Determine the possible destinations from the current instruction.
391 -- (we always assume that the next instruction is also a valid destination;
392 -- if this isn't the case then the jump should be at the end of the basic
395 jumpDests :: Instr -> [BlockId] -> [BlockId]
398 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
400 JMP_TBL _ ids -> ids ++ acc
401 #elif powerpc_TARGET_ARCH
403 BCTR targets -> targets ++ acc
408 -- -----------------------------------------------------------------------------
409 -- 'patchRegs' function
411 -- 'patchRegs' takes an instruction and applies the given mapping to
412 -- all the register references.
414 patchRegs :: Instr -> (Reg -> Reg) -> Instr
416 #if alpha_TARGET_ARCH
418 patchRegs instr env = case instr of
419 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
420 LDA reg addr -> LDA (env reg) (fixAddr addr)
421 LDAH reg addr -> LDAH (env reg) (fixAddr addr)
422 LDGP reg addr -> LDGP (env reg) (fixAddr addr)
423 LDI sz reg imm -> LDI sz (env reg) imm
424 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
425 CLR reg -> CLR (env reg)
426 ABS sz ar reg -> ABS sz (fixRI ar) (env reg)
427 NEG sz ov ar reg -> NEG sz ov (fixRI ar) (env reg)
428 ADD sz ov r1 ar r2 -> ADD sz ov (env r1) (fixRI ar) (env r2)
429 SADD sz sc r1 ar r2 -> SADD sz sc (env r1) (fixRI ar) (env r2)
430 SUB sz ov r1 ar r2 -> SUB sz ov (env r1) (fixRI ar) (env r2)
431 SSUB sz sc r1 ar r2 -> SSUB sz sc (env r1) (fixRI ar) (env r2)
432 MUL sz ov r1 ar r2 -> MUL sz ov (env r1) (fixRI ar) (env r2)
433 DIV sz un r1 ar r2 -> DIV sz un (env r1) (fixRI ar) (env r2)
434 REM sz un r1 ar r2 -> REM sz un (env r1) (fixRI ar) (env r2)
435 NOT ar reg -> NOT (fixRI ar) (env reg)
436 AND r1 ar r2 -> AND (env r1) (fixRI ar) (env r2)
437 ANDNOT r1 ar r2 -> ANDNOT (env r1) (fixRI ar) (env r2)
438 OR r1 ar r2 -> OR (env r1) (fixRI ar) (env r2)
439 ORNOT r1 ar r2 -> ORNOT (env r1) (fixRI ar) (env r2)
440 XOR r1 ar r2 -> XOR (env r1) (fixRI ar) (env r2)
441 XORNOT r1 ar r2 -> XORNOT (env r1) (fixRI ar) (env r2)
442 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
443 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
444 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
445 ZAP r1 ar r2 -> ZAP (env r1) (fixRI ar) (env r2)
446 ZAPNOT r1 ar r2 -> ZAPNOT (env r1) (fixRI ar) (env r2)
447 CMP co r1 ar r2 -> CMP co (env r1) (fixRI ar) (env r2)
448 FCLR reg -> FCLR (env reg)
449 FABS r1 r2 -> FABS (env r1) (env r2)
450 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
451 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
452 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
453 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
454 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
455 CVTxy s1 s2 r1 r2 -> CVTxy s1 s2 (env r1) (env r2)
456 FCMP s co r1 r2 r3 -> FCMP s co (env r1) (env r2) (env r3)
457 FMOV r1 r2 -> FMOV (env r1) (env r2)
458 BI cond reg lbl -> BI cond (env reg) lbl
459 BF cond reg lbl -> BF cond (env reg) lbl
460 JMP reg addr hint -> JMP (env reg) (fixAddr addr) hint
461 JSR reg addr i -> JSR (env reg) (fixAddr addr) i
464 fixAddr (AddrReg r1) = AddrReg (env r1)
465 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
466 fixAddr other = other
468 fixRI (RIReg r) = RIReg (env r)
471 #endif /* alpha_TARGET_ARCH */
472 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
473 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
475 patchRegs instr env = case instr of
476 MOV sz src dst -> patch2 (MOV sz) src dst
477 MOVZxL sz src dst -> patch2 (MOVZxL sz) src dst
478 MOVSxL sz src dst -> patch2 (MOVSxL sz) src dst
479 LEA sz src dst -> patch2 (LEA sz) src dst
480 ADD sz src dst -> patch2 (ADD sz) src dst
481 ADC sz src dst -> patch2 (ADC sz) src dst
482 SUB sz src dst -> patch2 (SUB sz) src dst
483 IMUL sz src dst -> patch2 (IMUL sz) src dst
484 IMUL2 sz src -> patch1 (IMUL2 sz) src
485 MUL sz src dst -> patch2 (MUL sz) src dst
486 IDIV sz op -> patch1 (IDIV sz) op
487 DIV sz op -> patch1 (DIV sz) op
488 AND sz src dst -> patch2 (AND sz) src dst
489 OR sz src dst -> patch2 (OR sz) src dst
490 XOR sz src dst -> patch2 (XOR sz) src dst
491 NOT sz op -> patch1 (NOT sz) op
492 NEGI sz op -> patch1 (NEGI sz) op
493 SHL sz imm dst -> patch1 (SHL sz imm) dst
494 SAR sz imm dst -> patch1 (SAR sz imm) dst
495 SHR sz imm dst -> patch1 (SHR sz imm) dst
496 BT sz imm src -> patch1 (BT sz imm) src
497 TEST sz src dst -> patch2 (TEST sz) src dst
498 CMP sz src dst -> patch2 (CMP sz) src dst
499 PUSH sz op -> patch1 (PUSH sz) op
500 POP sz op -> patch1 (POP sz) op
501 SETCC cond op -> patch1 (SETCC cond) op
502 JMP op -> patch1 JMP op
503 JMP_TBL op ids -> patch1 JMP_TBL op $ ids
506 GMOV src dst -> GMOV (env src) (env dst)
507 GLD sz src dst -> GLD sz (lookupAddr src) (env dst)
508 GST sz src dst -> GST sz (env src) (lookupAddr dst)
510 GLDZ dst -> GLDZ (env dst)
511 GLD1 dst -> GLD1 (env dst)
513 GFTOI src dst -> GFTOI (env src) (env dst)
514 GDTOI src dst -> GDTOI (env src) (env dst)
516 GITOF src dst -> GITOF (env src) (env dst)
517 GITOD src dst -> GITOD (env src) (env dst)
519 GADD sz s1 s2 dst -> GADD sz (env s1) (env s2) (env dst)
520 GSUB sz s1 s2 dst -> GSUB sz (env s1) (env s2) (env dst)
521 GMUL sz s1 s2 dst -> GMUL sz (env s1) (env s2) (env dst)
522 GDIV sz s1 s2 dst -> GDIV sz (env s1) (env s2) (env dst)
524 GCMP sz src1 src2 -> GCMP sz (env src1) (env src2)
525 GABS sz src dst -> GABS sz (env src) (env dst)
526 GNEG sz src dst -> GNEG sz (env src) (env dst)
527 GSQRT sz src dst -> GSQRT sz (env src) (env dst)
528 GSIN sz src dst -> GSIN sz (env src) (env dst)
529 GCOS sz src dst -> GCOS sz (env src) (env dst)
530 GTAN sz src dst -> GTAN sz (env src) (env dst)
533 #if x86_64_TARGET_ARCH
534 CVTSS2SD src dst -> CVTSS2SD (env src) (env dst)
535 CVTSD2SS src dst -> CVTSD2SS (env src) (env dst)
536 CVTSS2SI src dst -> CVTSS2SI (patchOp src) (env dst)
537 CVTSD2SI src dst -> CVTSD2SI (patchOp src) (env dst)
538 CVTSI2SS src dst -> CVTSI2SS (patchOp src) (env dst)
539 CVTSI2SD src dst -> CVTSI2SD (patchOp src) (env dst)
540 FDIV sz src dst -> FDIV sz (patchOp src) (patchOp dst)
543 CALL (Left imm) -> instr
544 CALL (Right reg) -> CALL (Right (env reg))
546 FETCHGOT reg -> FETCHGOT (env reg)
554 _other -> panic "patchRegs: unrecognised instr"
557 patch1 insn op = insn $! patchOp op
558 patch2 insn src dst = (insn $! patchOp src) $! patchOp dst
560 patchOp (OpReg reg) = OpReg $! env reg
561 patchOp (OpImm imm) = OpImm imm
562 patchOp (OpAddr ea) = OpAddr $! lookupAddr ea
564 lookupAddr (ImmAddr imm off) = ImmAddr imm off
565 lookupAddr (AddrBaseIndex base index disp)
566 = ((AddrBaseIndex $! lookupBase base) $! lookupIndex index) disp
568 lookupBase EABaseNone = EABaseNone
569 lookupBase EABaseRip = EABaseRip
570 lookupBase (EABaseReg r) = EABaseReg (env r)
572 lookupIndex EAIndexNone = EAIndexNone
573 lookupIndex (EAIndex r i) = EAIndex (env r) i
575 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH*/
576 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
577 #if sparc_TARGET_ARCH
579 patchRegs instr env = case instr of
580 LD sz addr reg -> LD sz (fixAddr addr) (env reg)
581 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
582 ADD x cc r1 ar r2 -> ADD x cc (env r1) (fixRI ar) (env r2)
583 SUB x cc r1 ar r2 -> SUB x cc (env r1) (fixRI ar) (env r2)
584 UMUL cc r1 ar r2 -> UMUL cc (env r1) (fixRI ar) (env r2)
585 SMUL cc r1 ar r2 -> SMUL cc (env r1) (fixRI ar) (env r2)
586 RDY rd -> RDY (env rd)
587 AND b r1 ar r2 -> AND b (env r1) (fixRI ar) (env r2)
588 ANDN b r1 ar r2 -> ANDN b (env r1) (fixRI ar) (env r2)
589 OR b r1 ar r2 -> OR b (env r1) (fixRI ar) (env r2)
590 ORN b r1 ar r2 -> ORN b (env r1) (fixRI ar) (env r2)
591 XOR b r1 ar r2 -> XOR b (env r1) (fixRI ar) (env r2)
592 XNOR b r1 ar r2 -> XNOR b (env r1) (fixRI ar) (env r2)
593 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
594 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
595 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
596 SETHI imm reg -> SETHI imm (env reg)
597 FABS s r1 r2 -> FABS s (env r1) (env r2)
598 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
599 FCMP e s r1 r2 -> FCMP e s (env r1) (env r2)
600 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
601 FMOV s r1 r2 -> FMOV s (env r1) (env r2)
602 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
603 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
604 FSQRT s r1 r2 -> FSQRT s (env r1) (env r2)
605 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
606 FxTOy s1 s2 r1 r2 -> FxTOy s1 s2 (env r1) (env r2)
607 JMP dsts addr -> JMP dsts (fixAddr addr)
608 CALL (Left i) n t -> CALL (Left i) n t
609 CALL (Right r) n t -> CALL (Right (env r)) n t
612 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
613 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
615 fixRI (RIReg r) = RIReg (env r)
618 #endif /* sparc_TARGET_ARCH */
619 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
620 #if powerpc_TARGET_ARCH
622 patchRegs instr env = case instr of
623 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
624 LA sz reg addr -> LA sz (env reg) (fixAddr addr)
625 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
626 STU sz reg addr -> STU sz (env reg) (fixAddr addr)
627 LIS reg imm -> LIS (env reg) imm
628 LI reg imm -> LI (env reg) imm
629 MR reg1 reg2 -> MR (env reg1) (env reg2)
630 CMP sz reg ri -> CMP sz (env reg) (fixRI ri)
631 CMPL sz reg ri -> CMPL sz (env reg) (fixRI ri)
632 BCC cond lbl -> BCC cond lbl
633 MTCTR reg -> MTCTR (env reg)
634 BCTR targets -> BCTR targets
635 BL imm argRegs -> BL imm argRegs -- argument regs
636 BCTRL argRegs -> BCTRL argRegs -- cannot be remapped
637 ADD reg1 reg2 ri -> ADD (env reg1) (env reg2) (fixRI ri)
638 ADDC reg1 reg2 reg3-> ADDC (env reg1) (env reg2) (env reg3)
639 ADDE reg1 reg2 reg3-> ADDE (env reg1) (env reg2) (env reg3)
640 ADDIS reg1 reg2 imm -> ADDIS (env reg1) (env reg2) imm
641 SUBF reg1 reg2 reg3-> SUBF (env reg1) (env reg2) (env reg3)
642 MULLW reg1 reg2 ri -> MULLW (env reg1) (env reg2) (fixRI ri)
643 DIVW reg1 reg2 reg3-> DIVW (env reg1) (env reg2) (env reg3)
644 DIVWU reg1 reg2 reg3-> DIVWU (env reg1) (env reg2) (env reg3)
645 MULLW_MayOflo reg1 reg2 reg3
646 -> MULLW_MayOflo (env reg1) (env reg2) (env reg3)
647 AND reg1 reg2 ri -> AND (env reg1) (env reg2) (fixRI ri)
648 OR reg1 reg2 ri -> OR (env reg1) (env reg2) (fixRI ri)
649 XOR reg1 reg2 ri -> XOR (env reg1) (env reg2) (fixRI ri)
650 XORIS reg1 reg2 imm -> XORIS (env reg1) (env reg2) imm
651 EXTS sz reg1 reg2 -> EXTS sz (env reg1) (env reg2)
652 NEG reg1 reg2 -> NEG (env reg1) (env reg2)
653 NOT reg1 reg2 -> NOT (env reg1) (env reg2)
654 SLW reg1 reg2 ri -> SLW (env reg1) (env reg2) (fixRI ri)
655 SRW reg1 reg2 ri -> SRW (env reg1) (env reg2) (fixRI ri)
656 SRAW reg1 reg2 ri -> SRAW (env reg1) (env reg2) (fixRI ri)
657 RLWINM reg1 reg2 sh mb me
658 -> RLWINM (env reg1) (env reg2) sh mb me
659 FADD sz r1 r2 r3 -> FADD sz (env r1) (env r2) (env r3)
660 FSUB sz r1 r2 r3 -> FSUB sz (env r1) (env r2) (env r3)
661 FMUL sz r1 r2 r3 -> FMUL sz (env r1) (env r2) (env r3)
662 FDIV sz r1 r2 r3 -> FDIV sz (env r1) (env r2) (env r3)
663 FNEG r1 r2 -> FNEG (env r1) (env r2)
664 FCMP r1 r2 -> FCMP (env r1) (env r2)
665 FCTIWZ r1 r2 -> FCTIWZ (env r1) (env r2)
666 FRSP r1 r2 -> FRSP (env r1) (env r2)
667 MFCR reg -> MFCR (env reg)
668 MFLR reg -> MFLR (env reg)
669 FETCHPC reg -> FETCHPC (env reg)
672 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
673 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
675 fixRI (RIReg r) = RIReg (env r)
677 #endif /* powerpc_TARGET_ARCH */
679 -- -----------------------------------------------------------------------------
680 -- Detecting reg->reg moves
682 -- The register allocator attempts to eliminate reg->reg moves whenever it can,
683 -- by assigning the src and dest temporaries to the same real register.
685 isRegRegMove :: Instr -> Maybe (Reg,Reg)
686 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
688 isRegRegMove (MOV _ (OpReg r1) (OpReg r2)) = Just (r1,r2)
689 #elif powerpc_TARGET_ARCH
690 isRegRegMove (MR dst src) = Just (src,dst)
692 #warning ToDo: isRegRegMove
694 isRegRegMove _ = Nothing
696 -- -----------------------------------------------------------------------------
697 -- Generating spill instructions
700 :: Reg -- register to spill (should be a real)
701 -> Int -- current stack delta
702 -> Int -- spill slot to use
704 mkSpillInstr reg delta slot
705 = ASSERT(isRealReg reg)
707 off = spillSlotToOffset slot
709 #ifdef alpha_TARGET_ARCH
710 {-Alpha: spill below the stack pointer (?)-}
711 ST sz dyn (spRel (- (off `div` 8)))
713 #ifdef i386_TARGET_ARCH
714 let off_w = (off-delta) `div` 4
715 in case regClass reg of
716 RcInteger -> MOV I32 (OpReg reg) (OpAddr (spRel off_w))
717 _ -> GST F80 reg (spRel off_w) {- RcFloat/RcDouble -}
719 #ifdef x86_64_TARGET_ARCH
720 let off_w = (off-delta) `div` 8
721 in case regClass reg of
722 RcInteger -> MOV I64 (OpReg reg) (OpAddr (spRel off_w))
723 RcDouble -> MOV F64 (OpReg reg) (OpAddr (spRel off_w))
724 -- ToDo: will it work to always spill as a double?
725 -- does that cause a stall if the data was a float?
727 #ifdef sparc_TARGET_ARCH
728 {-SPARC: spill below frame pointer leaving 2 words/spill-}
729 let{off_w = 1 + (off `div` 4);
730 sz = case regClass vreg of {
734 in ST sz dyn (fpRel (- off_w))
736 #ifdef powerpc_TARGET_ARCH
737 let sz = case regClass reg of
740 in ST sz reg (AddrRegImm sp (ImmInt (off-delta)))
745 :: Reg -- register to load (should be a real)
746 -> Int -- current stack delta
747 -> Int -- spill slot to use
749 mkLoadInstr reg delta slot
750 = ASSERT(isRealReg reg)
752 off = spillSlotToOffset slot
754 #if alpha_TARGET_ARCH
755 LD sz dyn (spRel (- (off `div` 8)))
758 let off_w = (off-delta) `div` 4
759 in case regClass reg of {
760 RcInteger -> MOV I32 (OpAddr (spRel off_w)) (OpReg reg);
761 _ -> GLD F80 (spRel off_w) reg} {- RcFloat/RcDouble -}
763 #if x86_64_TARGET_ARCH
764 let off_w = (off-delta) `div` 8
765 in case regClass reg of
766 RcInteger -> MOV I64 (OpAddr (spRel off_w)) (OpReg reg)
767 _ -> MOV F64 (OpAddr (spRel off_w)) (OpReg reg)
769 #if sparc_TARGET_ARCH
770 let{off_w = 1 + (off `div` 4);
771 sz = case regClass vreg of {
775 in LD sz (fpRel (- off_w)) dyn
777 #if powerpc_TARGET_ARCH
778 let sz = case regClass reg of
781 in LD sz reg (AddrRegImm sp (ImmInt (off-delta)))
786 spillSlotSize = IF_ARCH_i386(12, 8)
789 maxSpillSlots = ((rESERVED_C_STACK_BYTES - 64) `div` spillSlotSize) - 1
791 -- convert a spill slot number to a *byte* offset, with no sign:
792 -- decide on a per arch basis whether you are spilling above or below
793 -- the C stack pointer.
794 spillSlotToOffset :: Int -> Int
795 spillSlotToOffset slot
796 | slot >= 0 && slot < maxSpillSlots
797 = 64 + spillSlotSize * slot
799 = pprPanic "spillSlotToOffset:"
800 (text "invalid spill location: " <> int slot)