1 -----------------------------------------------------------------------------
3 -- Machine-specific parts of the register allocator
5 -- (c) The University of Glasgow 1996-2004
7 -----------------------------------------------------------------------------
9 #include "nativeGen/NCG.h"
24 #include "HsVersions.h"
26 import Cmm ( BlockId )
27 #if powerpc_TARGET_ARCH || i386_TARGET_ARCH || x86_64_TARGET_ARCH
28 import MachOp ( MachRep(..) )
33 import Constants ( rESERVED_C_STACK_BYTES )
36 -- -----------------------------------------------------------------------------
39 -- @regUsage@ returns the sets of src and destination registers used
40 -- by a particular instruction. Machine registers that are
41 -- pre-allocated to stgRegs are filtered out, because they are
42 -- uninteresting from a register allocation standpoint. (We wouldn't
43 -- want them to end up on the free list!) As far as we are concerned,
44 -- the fixed registers simply don't exist (for allocation purposes,
47 -- regUsage doesn't need to do any trickery for jumps and such. Just
48 -- state precisely the regs read and written by that insn. The
49 -- consequences of control flow transfers, as far as register
50 -- allocation goes, are taken care of by the register allocator.
52 data RegUsage = RU [Reg] [Reg]
57 regUsage :: Instr -> RegUsage
59 interesting (VirtualRegI _) = True
60 interesting (VirtualRegHi _) = True
61 interesting (VirtualRegF _) = True
62 interesting (VirtualRegD _) = True
63 interesting (RealReg i) = isFastTrue (freeReg i)
67 regUsage instr = case instr of
68 LD B reg addr -> usage (regAddr addr, [reg, t9])
69 LD Bu reg addr -> usage (regAddr addr, [reg, t9])
70 -- LD W reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
71 -- LD Wu reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
72 LD sz reg addr -> usage (regAddr addr, [reg])
73 LDA reg addr -> usage (regAddr addr, [reg])
74 LDAH reg addr -> usage (regAddr addr, [reg])
75 LDGP reg addr -> usage (regAddr addr, [reg])
76 LDI sz reg imm -> usage ([], [reg])
77 ST B reg addr -> usage (reg : regAddr addr, [t9, t10])
78 -- ST W reg addr -> usage (reg : regAddr addr, [t9, t10]) : UNUSED
79 ST sz reg addr -> usage (reg : regAddr addr, [])
80 CLR reg -> usage ([], [reg])
81 ABS sz ri reg -> usage (regRI ri, [reg])
82 NEG sz ov ri reg -> usage (regRI ri, [reg])
83 ADD sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
84 SADD sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
85 SUB sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
86 SSUB sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
87 MUL sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
88 DIV sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
89 REM sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
90 NOT ri reg -> usage (regRI ri, [reg])
91 AND r1 ar r2 -> usage (r1 : regRI ar, [r2])
92 ANDNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
93 OR r1 ar r2 -> usage (r1 : regRI ar, [r2])
94 ORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
95 XOR r1 ar r2 -> usage (r1 : regRI ar, [r2])
96 XORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
97 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
98 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
99 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
100 ZAP r1 ar r2 -> usage (r1 : regRI ar, [r2])
101 ZAPNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
102 CMP co r1 ar r2 -> usage (r1 : regRI ar, [r2])
103 FCLR reg -> usage ([], [reg])
104 FABS r1 r2 -> usage ([r1], [r2])
105 FNEG sz r1 r2 -> usage ([r1], [r2])
106 FADD sz r1 r2 r3 -> usage ([r1, r2], [r3])
107 FDIV sz r1 r2 r3 -> usage ([r1, r2], [r3])
108 FMUL sz r1 r2 r3 -> usage ([r1, r2], [r3])
109 FSUB sz r1 r2 r3 -> usage ([r1, r2], [r3])
110 CVTxy sz1 sz2 r1 r2 -> usage ([r1], [r2])
111 FCMP sz co r1 r2 r3 -> usage ([r1, r2], [r3])
112 FMOV r1 r2 -> usage ([r1], [r2])
115 -- We assume that all local jumps will be BI/BF/BR. JMP must be out-of-line.
116 BI cond reg lbl -> usage ([reg], [])
117 BF cond reg lbl -> usage ([reg], [])
118 JMP reg addr hint -> RU (mkRegSet (filter interesting (regAddr addr))) freeRegSet
120 BSR _ n -> RU (argRegSet n) callClobberedRegSet
121 JSR reg addr n -> RU (argRegSet n) callClobberedRegSet
126 usage (src, dst) = RU (mkRegSet (filter interesting src))
127 (mkRegSet (filter interesting dst))
129 interesting (FixedReg _) = False
132 regAddr (AddrReg r1) = [r1]
133 regAddr (AddrRegImm r1 _) = [r1]
134 regAddr (AddrImm _) = []
136 regRI (RIReg r) = [r]
139 #endif /* alpha_TARGET_ARCH */
140 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
141 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
143 regUsage instr = case instr of
144 MOV sz src dst -> usageRW src dst
145 MOVZxL sz src dst -> usageRW src dst
146 MOVSxL sz src dst -> usageRW src dst
147 LEA sz src dst -> usageRW src dst
148 ADD sz src dst -> usageRM src dst
149 ADC sz src dst -> usageRM src dst
150 SUB sz src dst -> usageRM src dst
151 IMUL sz src dst -> usageRM src dst
152 IMUL2 sz src -> mkRU (eax:use_R src) [eax,edx]
153 MUL sz src dst -> usageRM src dst
154 DIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
155 IDIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
156 AND sz src dst -> usageRM src dst
157 OR sz src dst -> usageRM src dst
158 XOR sz src dst -> usageRM src dst
159 NOT sz op -> usageM op
160 NEGI sz op -> usageM op
161 SHL sz imm dst -> usageRM imm dst
162 SAR sz imm dst -> usageRM imm dst
163 SHR sz imm dst -> usageRM imm dst
164 BT sz imm src -> mkRU (use_R src) []
166 PUSH sz op -> mkRU (use_R op) []
167 POP sz op -> mkRU [] (def_W op)
168 TEST sz src dst -> mkRU (use_R src ++ use_R dst) []
169 CMP sz src dst -> mkRU (use_R src ++ use_R dst) []
170 SETCC cond op -> mkRU [] (def_W op)
171 JXX cond lbl -> mkRU [] []
172 JMP op -> mkRU (use_R op) []
173 JMP_TBL op ids -> mkRU (use_R op) []
174 CALL (Left imm) params -> mkRU params callClobberedRegs
175 CALL (Right reg) params -> mkRU (reg:params) callClobberedRegs
176 CLTD sz -> mkRU [eax] [edx]
180 GMOV src dst -> mkRU [src] [dst]
181 GLD sz src dst -> mkRU (use_EA src) [dst]
182 GST sz src dst -> mkRU (src : use_EA dst) []
184 GLDZ dst -> mkRU [] [dst]
185 GLD1 dst -> mkRU [] [dst]
187 GFTOI src dst -> mkRU [src] [dst]
188 GDTOI src dst -> mkRU [src] [dst]
190 GITOF src dst -> mkRU [src] [dst]
191 GITOD src dst -> mkRU [src] [dst]
193 GADD sz s1 s2 dst -> mkRU [s1,s2] [dst]
194 GSUB sz s1 s2 dst -> mkRU [s1,s2] [dst]
195 GMUL sz s1 s2 dst -> mkRU [s1,s2] [dst]
196 GDIV sz s1 s2 dst -> mkRU [s1,s2] [dst]
198 GCMP sz src1 src2 -> mkRU [src1,src2] []
199 GABS sz src dst -> mkRU [src] [dst]
200 GNEG sz src dst -> mkRU [src] [dst]
201 GSQRT sz src dst -> mkRU [src] [dst]
202 GSIN sz src dst -> mkRU [src] [dst]
203 GCOS sz src dst -> mkRU [src] [dst]
204 GTAN sz src dst -> mkRU [src] [dst]
207 #if x86_64_TARGET_ARCH
208 CVTSS2SD src dst -> mkRU [src] [dst]
209 CVTSD2SS src dst -> mkRU [src] [dst]
210 CVTSS2SI src dst -> mkRU (use_R src) [dst]
211 CVTSD2SI src dst -> mkRU (use_R src) [dst]
212 CVTSI2SS src dst -> mkRU (use_R src) [dst]
213 CVTSI2SD src dst -> mkRU (use_R src) [dst]
214 FDIV sz src dst -> usageRM src dst
217 FETCHGOT reg -> mkRU [] [reg]
218 FETCHPC reg -> mkRU [] [reg]
223 _other -> panic "regUsage: unrecognised instr"
226 #if x86_64_TARGET_ARCH
227 -- call parameters: include %eax, because it is used
228 -- to pass the number of SSE reg arguments to varargs fns.
229 params = eax : allArgRegs ++ allFPArgRegs
232 -- 2 operand form; first operand Read; second Written
233 usageRW :: Operand -> Operand -> RegUsage
234 usageRW op (OpReg reg) = mkRU (use_R op) [reg]
235 usageRW op (OpAddr ea) = mkRU (use_R op ++ use_EA ea) []
237 -- 2 operand form; first operand Read; second Modified
238 usageRM :: Operand -> Operand -> RegUsage
239 usageRM op (OpReg reg) = mkRU (use_R op ++ [reg]) [reg]
240 usageRM op (OpAddr ea) = mkRU (use_R op ++ use_EA ea) []
242 -- 1 operand form; operand Modified
243 usageM :: Operand -> RegUsage
244 usageM (OpReg reg) = mkRU [reg] [reg]
245 usageM (OpAddr ea) = mkRU (use_EA ea) []
247 -- Registers defd when an operand is written.
248 def_W (OpReg reg) = [reg]
249 def_W (OpAddr ea) = []
251 -- Registers used when an operand is read.
252 use_R (OpReg reg) = [reg]
253 use_R (OpImm imm) = []
254 use_R (OpAddr ea) = use_EA ea
256 -- Registers used to compute an effective address.
257 use_EA (ImmAddr _ _) = []
258 use_EA (AddrBaseIndex base index _) =
259 use_base base $! use_index index
260 where use_base (EABaseReg r) x = r : x
262 use_index EAIndexNone = []
263 use_index (EAIndex i _) = [i]
265 mkRU src dst = RU (filter interesting src)
266 (filter interesting dst)
268 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH */
269 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
270 #if sparc_TARGET_ARCH
272 regUsage instr = case instr of
273 LD sz addr reg -> usage (regAddr addr, [reg])
274 ST sz reg addr -> usage (reg : regAddr addr, [])
275 ADD x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
276 SUB x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
277 UMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
278 SMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
279 RDY rd -> usage ([], [rd])
280 AND b r1 ar r2 -> usage (r1 : regRI ar, [r2])
281 ANDN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
282 OR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
283 ORN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
284 XOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
285 XNOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
286 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
287 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
288 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
289 SETHI imm reg -> usage ([], [reg])
290 FABS s r1 r2 -> usage ([r1], [r2])
291 FADD s r1 r2 r3 -> usage ([r1, r2], [r3])
292 FCMP e s r1 r2 -> usage ([r1, r2], [])
293 FDIV s r1 r2 r3 -> usage ([r1, r2], [r3])
294 FMOV s r1 r2 -> usage ([r1], [r2])
295 FMUL s r1 r2 r3 -> usage ([r1, r2], [r3])
296 FNEG s r1 r2 -> usage ([r1], [r2])
297 FSQRT s r1 r2 -> usage ([r1], [r2])
298 FSUB s r1 r2 r3 -> usage ([r1, r2], [r3])
299 FxTOy s1 s2 r1 r2 -> usage ([r1], [r2])
301 -- We assume that all local jumps will be BI/BF. JMP must be out-of-line.
302 JMP dst addr -> usage (regAddr addr, [])
304 CALL (Left imm) n True -> noUsage
305 CALL (Left imm) n False -> usage (argRegs n, callClobberedRegs)
306 CALL (Right reg) n True -> usage ([reg], [])
307 CALL (Right reg) n False -> usage (reg : (argRegs n), callClobberedRegs)
311 usage (src, dst) = RU (regSetFromList (filter interesting src))
312 (regSetFromList (filter interesting dst))
314 regAddr (AddrRegReg r1 r2) = [r1, r2]
315 regAddr (AddrRegImm r1 _) = [r1]
317 regRI (RIReg r) = [r]
320 #endif /* sparc_TARGET_ARCH */
321 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
322 #if powerpc_TARGET_ARCH
324 regUsage instr = case instr of
325 LD sz reg addr -> usage (regAddr addr, [reg])
326 LA sz reg addr -> usage (regAddr addr, [reg])
327 ST sz reg addr -> usage (reg : regAddr addr, [])
328 STU sz reg addr -> usage (reg : regAddr addr, [])
329 LIS reg imm -> usage ([], [reg])
330 LI reg imm -> usage ([], [reg])
331 MR reg1 reg2 -> usage ([reg2], [reg1])
332 CMP sz reg ri -> usage (reg : regRI ri,[])
333 CMPL sz reg ri -> usage (reg : regRI ri,[])
334 BCC cond lbl -> noUsage
335 MTCTR reg -> usage ([reg],[])
336 BCTR targets -> noUsage
337 BL imm params -> usage (params, callClobberedRegs)
338 BCTRL params -> usage (params, callClobberedRegs)
339 ADD reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
340 ADDC reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
341 ADDE reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
342 ADDIS reg1 reg2 imm -> usage ([reg2], [reg1])
343 SUBF reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
344 MULLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
345 DIVW reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
346 DIVWU reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
347 MULLW_MayOflo reg1 reg2 reg3
348 -> usage ([reg2,reg3], [reg1])
349 AND reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
350 OR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
351 XOR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
352 XORIS reg1 reg2 imm -> usage ([reg2], [reg1])
353 EXTS siz reg1 reg2 -> usage ([reg2], [reg1])
354 NEG reg1 reg2 -> usage ([reg2], [reg1])
355 NOT reg1 reg2 -> usage ([reg2], [reg1])
356 SLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
357 SRW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
358 SRAW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1])
359 RLWINM reg1 reg2 sh mb me
360 -> usage ([reg2], [reg1])
361 FADD sz r1 r2 r3 -> usage ([r2,r3], [r1])
362 FSUB sz r1 r2 r3 -> usage ([r2,r3], [r1])
363 FMUL sz r1 r2 r3 -> usage ([r2,r3], [r1])
364 FDIV sz r1 r2 r3 -> usage ([r2,r3], [r1])
365 FNEG r1 r2 -> usage ([r2], [r1])
366 FCMP r1 r2 -> usage ([r1,r2], [])
367 FCTIWZ r1 r2 -> usage ([r2], [r1])
368 FRSP r1 r2 -> usage ([r2], [r1])
369 MFCR reg -> usage ([], [reg])
370 MFLR reg -> usage ([], [reg])
371 FETCHPC reg -> usage ([], [reg])
374 usage (src, dst) = RU (filter interesting src)
375 (filter interesting dst)
376 regAddr (AddrRegReg r1 r2) = [r1, r2]
377 regAddr (AddrRegImm r1 _) = [r1]
379 regRI (RIReg r) = [r]
381 #endif /* powerpc_TARGET_ARCH */
384 -- -----------------------------------------------------------------------------
385 -- Determine the possible destinations from the current instruction.
387 -- (we always assume that the next instruction is also a valid destination;
388 -- if this isn't the case then the jump should be at the end of the basic
391 jumpDests :: Instr -> [BlockId] -> [BlockId]
394 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
396 JMP_TBL _ ids -> ids ++ acc
397 #elif powerpc_TARGET_ARCH
399 BCTR targets -> targets ++ acc
404 -- -----------------------------------------------------------------------------
405 -- 'patchRegs' function
407 -- 'patchRegs' takes an instruction and applies the given mapping to
408 -- all the register references.
410 patchRegs :: Instr -> (Reg -> Reg) -> Instr
412 #if alpha_TARGET_ARCH
414 patchRegs instr env = case instr of
415 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
416 LDA reg addr -> LDA (env reg) (fixAddr addr)
417 LDAH reg addr -> LDAH (env reg) (fixAddr addr)
418 LDGP reg addr -> LDGP (env reg) (fixAddr addr)
419 LDI sz reg imm -> LDI sz (env reg) imm
420 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
421 CLR reg -> CLR (env reg)
422 ABS sz ar reg -> ABS sz (fixRI ar) (env reg)
423 NEG sz ov ar reg -> NEG sz ov (fixRI ar) (env reg)
424 ADD sz ov r1 ar r2 -> ADD sz ov (env r1) (fixRI ar) (env r2)
425 SADD sz sc r1 ar r2 -> SADD sz sc (env r1) (fixRI ar) (env r2)
426 SUB sz ov r1 ar r2 -> SUB sz ov (env r1) (fixRI ar) (env r2)
427 SSUB sz sc r1 ar r2 -> SSUB sz sc (env r1) (fixRI ar) (env r2)
428 MUL sz ov r1 ar r2 -> MUL sz ov (env r1) (fixRI ar) (env r2)
429 DIV sz un r1 ar r2 -> DIV sz un (env r1) (fixRI ar) (env r2)
430 REM sz un r1 ar r2 -> REM sz un (env r1) (fixRI ar) (env r2)
431 NOT ar reg -> NOT (fixRI ar) (env reg)
432 AND r1 ar r2 -> AND (env r1) (fixRI ar) (env r2)
433 ANDNOT r1 ar r2 -> ANDNOT (env r1) (fixRI ar) (env r2)
434 OR r1 ar r2 -> OR (env r1) (fixRI ar) (env r2)
435 ORNOT r1 ar r2 -> ORNOT (env r1) (fixRI ar) (env r2)
436 XOR r1 ar r2 -> XOR (env r1) (fixRI ar) (env r2)
437 XORNOT r1 ar r2 -> XORNOT (env r1) (fixRI ar) (env r2)
438 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
439 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
440 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
441 ZAP r1 ar r2 -> ZAP (env r1) (fixRI ar) (env r2)
442 ZAPNOT r1 ar r2 -> ZAPNOT (env r1) (fixRI ar) (env r2)
443 CMP co r1 ar r2 -> CMP co (env r1) (fixRI ar) (env r2)
444 FCLR reg -> FCLR (env reg)
445 FABS r1 r2 -> FABS (env r1) (env r2)
446 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
447 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
448 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
449 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
450 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
451 CVTxy s1 s2 r1 r2 -> CVTxy s1 s2 (env r1) (env r2)
452 FCMP s co r1 r2 r3 -> FCMP s co (env r1) (env r2) (env r3)
453 FMOV r1 r2 -> FMOV (env r1) (env r2)
454 BI cond reg lbl -> BI cond (env reg) lbl
455 BF cond reg lbl -> BF cond (env reg) lbl
456 JMP reg addr hint -> JMP (env reg) (fixAddr addr) hint
457 JSR reg addr i -> JSR (env reg) (fixAddr addr) i
460 fixAddr (AddrReg r1) = AddrReg (env r1)
461 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
462 fixAddr other = other
464 fixRI (RIReg r) = RIReg (env r)
467 #endif /* alpha_TARGET_ARCH */
468 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
469 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
471 patchRegs instr env = case instr of
472 MOV sz src dst -> patch2 (MOV sz) src dst
473 MOVZxL sz src dst -> patch2 (MOVZxL sz) src dst
474 MOVSxL sz src dst -> patch2 (MOVSxL sz) src dst
475 LEA sz src dst -> patch2 (LEA sz) src dst
476 ADD sz src dst -> patch2 (ADD sz) src dst
477 ADC sz src dst -> patch2 (ADC sz) src dst
478 SUB sz src dst -> patch2 (SUB sz) src dst
479 IMUL sz src dst -> patch2 (IMUL sz) src dst
480 IMUL2 sz src -> patch1 (IMUL2 sz) src
481 MUL sz src dst -> patch2 (MUL sz) src dst
482 IDIV sz op -> patch1 (IDIV sz) op
483 DIV sz op -> patch1 (DIV sz) op
484 AND sz src dst -> patch2 (AND sz) src dst
485 OR sz src dst -> patch2 (OR sz) src dst
486 XOR sz src dst -> patch2 (XOR sz) src dst
487 NOT sz op -> patch1 (NOT sz) op
488 NEGI sz op -> patch1 (NEGI sz) op
489 SHL sz imm dst -> patch1 (SHL sz imm) dst
490 SAR sz imm dst -> patch1 (SAR sz imm) dst
491 SHR sz imm dst -> patch1 (SHR sz imm) dst
492 BT sz imm src -> patch1 (BT sz imm) src
493 TEST sz src dst -> patch2 (TEST sz) src dst
494 CMP sz src dst -> patch2 (CMP sz) src dst
495 PUSH sz op -> patch1 (PUSH sz) op
496 POP sz op -> patch1 (POP sz) op
497 SETCC cond op -> patch1 (SETCC cond) op
498 JMP op -> patch1 JMP op
499 JMP_TBL op ids -> patch1 JMP_TBL op $ ids
502 GMOV src dst -> GMOV (env src) (env dst)
503 GLD sz src dst -> GLD sz (lookupAddr src) (env dst)
504 GST sz src dst -> GST sz (env src) (lookupAddr dst)
506 GLDZ dst -> GLDZ (env dst)
507 GLD1 dst -> GLD1 (env dst)
509 GFTOI src dst -> GFTOI (env src) (env dst)
510 GDTOI src dst -> GDTOI (env src) (env dst)
512 GITOF src dst -> GITOF (env src) (env dst)
513 GITOD src dst -> GITOD (env src) (env dst)
515 GADD sz s1 s2 dst -> GADD sz (env s1) (env s2) (env dst)
516 GSUB sz s1 s2 dst -> GSUB sz (env s1) (env s2) (env dst)
517 GMUL sz s1 s2 dst -> GMUL sz (env s1) (env s2) (env dst)
518 GDIV sz s1 s2 dst -> GDIV sz (env s1) (env s2) (env dst)
520 GCMP sz src1 src2 -> GCMP sz (env src1) (env src2)
521 GABS sz src dst -> GABS sz (env src) (env dst)
522 GNEG sz src dst -> GNEG sz (env src) (env dst)
523 GSQRT sz src dst -> GSQRT sz (env src) (env dst)
524 GSIN sz src dst -> GSIN sz (env src) (env dst)
525 GCOS sz src dst -> GCOS sz (env src) (env dst)
526 GTAN sz src dst -> GTAN sz (env src) (env dst)
529 #if x86_64_TARGET_ARCH
530 CVTSS2SD src dst -> CVTSS2SD (env src) (env dst)
531 CVTSD2SS src dst -> CVTSD2SS (env src) (env dst)
532 CVTSS2SI src dst -> CVTSS2SI (patchOp src) (env dst)
533 CVTSD2SI src dst -> CVTSD2SI (patchOp src) (env dst)
534 CVTSI2SS src dst -> CVTSI2SS (patchOp src) (env dst)
535 CVTSI2SD src dst -> CVTSI2SD (patchOp src) (env dst)
536 FDIV sz src dst -> FDIV sz (patchOp src) (patchOp dst)
539 CALL (Left imm) _ -> instr
540 CALL (Right reg) p -> CALL (Right (env reg)) p
542 FETCHGOT reg -> FETCHGOT (env reg)
543 FETCHPC reg -> FETCHPC (env reg)
551 _other -> panic "patchRegs: unrecognised instr"
554 patch1 insn op = insn $! patchOp op
555 patch2 insn src dst = (insn $! patchOp src) $! patchOp dst
557 patchOp (OpReg reg) = OpReg $! env reg
558 patchOp (OpImm imm) = OpImm imm
559 patchOp (OpAddr ea) = OpAddr $! lookupAddr ea
561 lookupAddr (ImmAddr imm off) = ImmAddr imm off
562 lookupAddr (AddrBaseIndex base index disp)
563 = ((AddrBaseIndex $! lookupBase base) $! lookupIndex index) disp
565 lookupBase EABaseNone = EABaseNone
566 lookupBase EABaseRip = EABaseRip
567 lookupBase (EABaseReg r) = EABaseReg (env r)
569 lookupIndex EAIndexNone = EAIndexNone
570 lookupIndex (EAIndex r i) = EAIndex (env r) i
572 #endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH*/
573 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
574 #if sparc_TARGET_ARCH
576 patchRegs instr env = case instr of
577 LD sz addr reg -> LD sz (fixAddr addr) (env reg)
578 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
579 ADD x cc r1 ar r2 -> ADD x cc (env r1) (fixRI ar) (env r2)
580 SUB x cc r1 ar r2 -> SUB x cc (env r1) (fixRI ar) (env r2)
581 UMUL cc r1 ar r2 -> UMUL cc (env r1) (fixRI ar) (env r2)
582 SMUL cc r1 ar r2 -> SMUL cc (env r1) (fixRI ar) (env r2)
583 RDY rd -> RDY (env rd)
584 AND b r1 ar r2 -> AND b (env r1) (fixRI ar) (env r2)
585 ANDN b r1 ar r2 -> ANDN b (env r1) (fixRI ar) (env r2)
586 OR b r1 ar r2 -> OR b (env r1) (fixRI ar) (env r2)
587 ORN b r1 ar r2 -> ORN b (env r1) (fixRI ar) (env r2)
588 XOR b r1 ar r2 -> XOR b (env r1) (fixRI ar) (env r2)
589 XNOR b r1 ar r2 -> XNOR b (env r1) (fixRI ar) (env r2)
590 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
591 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
592 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
593 SETHI imm reg -> SETHI imm (env reg)
594 FABS s r1 r2 -> FABS s (env r1) (env r2)
595 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
596 FCMP e s r1 r2 -> FCMP e s (env r1) (env r2)
597 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
598 FMOV s r1 r2 -> FMOV s (env r1) (env r2)
599 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
600 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
601 FSQRT s r1 r2 -> FSQRT s (env r1) (env r2)
602 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
603 FxTOy s1 s2 r1 r2 -> FxTOy s1 s2 (env r1) (env r2)
604 JMP dsts addr -> JMP dsts (fixAddr addr)
605 CALL (Left i) n t -> CALL (Left i) n t
606 CALL (Right r) n t -> CALL (Right (env r)) n t
609 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
610 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
612 fixRI (RIReg r) = RIReg (env r)
615 #endif /* sparc_TARGET_ARCH */
616 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
617 #if powerpc_TARGET_ARCH
619 patchRegs instr env = case instr of
620 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
621 LA sz reg addr -> LA sz (env reg) (fixAddr addr)
622 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
623 STU sz reg addr -> STU sz (env reg) (fixAddr addr)
624 LIS reg imm -> LIS (env reg) imm
625 LI reg imm -> LI (env reg) imm
626 MR reg1 reg2 -> MR (env reg1) (env reg2)
627 CMP sz reg ri -> CMP sz (env reg) (fixRI ri)
628 CMPL sz reg ri -> CMPL sz (env reg) (fixRI ri)
629 BCC cond lbl -> BCC cond lbl
630 MTCTR reg -> MTCTR (env reg)
631 BCTR targets -> BCTR targets
632 BL imm argRegs -> BL imm argRegs -- argument regs
633 BCTRL argRegs -> BCTRL argRegs -- cannot be remapped
634 ADD reg1 reg2 ri -> ADD (env reg1) (env reg2) (fixRI ri)
635 ADDC reg1 reg2 reg3-> ADDC (env reg1) (env reg2) (env reg3)
636 ADDE reg1 reg2 reg3-> ADDE (env reg1) (env reg2) (env reg3)
637 ADDIS reg1 reg2 imm -> ADDIS (env reg1) (env reg2) imm
638 SUBF reg1 reg2 reg3-> SUBF (env reg1) (env reg2) (env reg3)
639 MULLW reg1 reg2 ri -> MULLW (env reg1) (env reg2) (fixRI ri)
640 DIVW reg1 reg2 reg3-> DIVW (env reg1) (env reg2) (env reg3)
641 DIVWU reg1 reg2 reg3-> DIVWU (env reg1) (env reg2) (env reg3)
642 MULLW_MayOflo reg1 reg2 reg3
643 -> MULLW_MayOflo (env reg1) (env reg2) (env reg3)
644 AND reg1 reg2 ri -> AND (env reg1) (env reg2) (fixRI ri)
645 OR reg1 reg2 ri -> OR (env reg1) (env reg2) (fixRI ri)
646 XOR reg1 reg2 ri -> XOR (env reg1) (env reg2) (fixRI ri)
647 XORIS reg1 reg2 imm -> XORIS (env reg1) (env reg2) imm
648 EXTS sz reg1 reg2 -> EXTS sz (env reg1) (env reg2)
649 NEG reg1 reg2 -> NEG (env reg1) (env reg2)
650 NOT reg1 reg2 -> NOT (env reg1) (env reg2)
651 SLW reg1 reg2 ri -> SLW (env reg1) (env reg2) (fixRI ri)
652 SRW reg1 reg2 ri -> SRW (env reg1) (env reg2) (fixRI ri)
653 SRAW reg1 reg2 ri -> SRAW (env reg1) (env reg2) (fixRI ri)
654 RLWINM reg1 reg2 sh mb me
655 -> RLWINM (env reg1) (env reg2) sh mb me
656 FADD sz r1 r2 r3 -> FADD sz (env r1) (env r2) (env r3)
657 FSUB sz r1 r2 r3 -> FSUB sz (env r1) (env r2) (env r3)
658 FMUL sz r1 r2 r3 -> FMUL sz (env r1) (env r2) (env r3)
659 FDIV sz r1 r2 r3 -> FDIV sz (env r1) (env r2) (env r3)
660 FNEG r1 r2 -> FNEG (env r1) (env r2)
661 FCMP r1 r2 -> FCMP (env r1) (env r2)
662 FCTIWZ r1 r2 -> FCTIWZ (env r1) (env r2)
663 FRSP r1 r2 -> FRSP (env r1) (env r2)
664 MFCR reg -> MFCR (env reg)
665 MFLR reg -> MFLR (env reg)
666 FETCHPC reg -> FETCHPC (env reg)
669 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
670 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
672 fixRI (RIReg r) = RIReg (env r)
674 #endif /* powerpc_TARGET_ARCH */
676 -- -----------------------------------------------------------------------------
677 -- Detecting reg->reg moves
679 -- The register allocator attempts to eliminate reg->reg moves whenever it can,
680 -- by assigning the src and dest temporaries to the same real register.
682 isRegRegMove :: Instr -> Maybe (Reg,Reg)
683 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
685 isRegRegMove (MOV _ (OpReg r1) (OpReg r2)) = Just (r1,r2)
686 #elif powerpc_TARGET_ARCH
687 isRegRegMove (MR dst src) = Just (src,dst)
689 #warning ToDo: isRegRegMove
691 isRegRegMove _ = Nothing
693 -- -----------------------------------------------------------------------------
694 -- Generating spill instructions
697 :: Reg -- register to spill (should be a real)
698 -> Int -- current stack delta
699 -> Int -- spill slot to use
701 mkSpillInstr reg delta slot
702 = ASSERT(isRealReg reg)
704 off = spillSlotToOffset slot
706 #ifdef alpha_TARGET_ARCH
707 {-Alpha: spill below the stack pointer (?)-}
708 ST sz dyn (spRel (- (off `div` 8)))
710 #ifdef i386_TARGET_ARCH
711 let off_w = (off-delta) `div` 4
712 in case regClass reg of
713 RcInteger -> MOV I32 (OpReg reg) (OpAddr (spRel off_w))
714 _ -> GST F80 reg (spRel off_w) {- RcFloat/RcDouble -}
716 #ifdef x86_64_TARGET_ARCH
717 let off_w = (off-delta) `div` 8
718 in case regClass reg of
719 RcInteger -> MOV I64 (OpReg reg) (OpAddr (spRel off_w))
720 RcDouble -> MOV F64 (OpReg reg) (OpAddr (spRel off_w))
721 -- ToDo: will it work to always spill as a double?
722 -- does that cause a stall if the data was a float?
724 #ifdef sparc_TARGET_ARCH
725 {-SPARC: spill below frame pointer leaving 2 words/spill-}
726 let{off_w = 1 + (off `div` 4);
727 sz = case regClass vreg of {
731 in ST sz dyn (fpRel (- off_w))
733 #ifdef powerpc_TARGET_ARCH
734 let sz = case regClass reg of
737 in ST sz reg (AddrRegImm sp (ImmInt (off-delta)))
742 :: Reg -- register to load (should be a real)
743 -> Int -- current stack delta
744 -> Int -- spill slot to use
746 mkLoadInstr reg delta slot
747 = ASSERT(isRealReg reg)
749 off = spillSlotToOffset slot
751 #if alpha_TARGET_ARCH
752 LD sz dyn (spRel (- (off `div` 8)))
755 let off_w = (off-delta) `div` 4
756 in case regClass reg of {
757 RcInteger -> MOV I32 (OpAddr (spRel off_w)) (OpReg reg);
758 _ -> GLD F80 (spRel off_w) reg} {- RcFloat/RcDouble -}
760 #if x86_64_TARGET_ARCH
761 let off_w = (off-delta) `div` 8
762 in case regClass reg of
763 RcInteger -> MOV I64 (OpAddr (spRel off_w)) (OpReg reg)
764 _ -> MOV F64 (OpAddr (spRel off_w)) (OpReg reg)
766 #if sparc_TARGET_ARCH
767 let{off_w = 1 + (off `div` 4);
768 sz = case regClass vreg of {
772 in LD sz (fpRel (- off_w)) dyn
774 #if powerpc_TARGET_ARCH
775 let sz = case regClass reg of
778 in LD sz reg (AddrRegImm sp (ImmInt (off-delta)))
783 spillSlotSize = IF_ARCH_i386(12, 8)
786 maxSpillSlots = ((rESERVED_C_STACK_BYTES - 64) `div` spillSlotSize) - 1
788 -- convert a spill slot number to a *byte* offset, with no sign:
789 -- decide on a per arch basis whether you are spilling above or below
790 -- the C stack pointer.
791 spillSlotToOffset :: Int -> Int
792 spillSlotToOffset slot
793 | slot >= 0 && slot < maxSpillSlots
794 = 64 + spillSlotSize * slot
796 = pprPanic "spillSlotToOffset:"
797 (text "invalid spill location: " <> int slot)