2 % (c) The AQUA Project, Glasgow University, 1996-1998
4 \section[RegAllocInfo]{Machine-specific info used for register allocation}
6 The (machine-independent) allocator itself is in @AsmRegAlloc@.
9 #include "nativeGen/NCG.h"
37 #include "HsVersions.h"
42 import Stix ( DestInfo(..) )
43 import CLabel ( isAsmTemp, CLabel{-instance Ord-} )
44 import FiniteMap ( addToFM, lookupFM, FiniteMap )
46 import Constants ( rESERVED_C_STACK_BYTES )
47 import Unique ( Unique, Uniquable(..) )
52 %************************************************************************
54 \subsection{Sets of registers}
56 %************************************************************************
60 -- Blargh. Use ghc stuff soon! Or: perhaps that's not such a good
61 -- idea. Most of these sets are either empty or very small, and it
62 -- might be that the overheads of the FiniteMap based set implementation
63 -- is a net loss. The same might be true of FeSets.
65 newtype RegSet = MkRegSet [Reg]
68 = MkRegSet (nukeDups (sort xs))
69 where nukeDups :: [Reg] -> [Reg]
73 = if x == y then nukeDups (y:xys)
74 else x : nukeDups (y:xys)
76 regSetToList (MkRegSet xs) = xs
77 isEmptyRegSet (MkRegSet xs) = null xs
78 emptyRegSet = MkRegSet []
79 eqRegSets (MkRegSet xs1) (MkRegSet xs2) = xs1 == xs2
80 unitRegSet x = MkRegSet [x]
81 filterRegSet p (MkRegSet xs) = MkRegSet (filter p xs)
83 elemRegSet x (MkRegSet xs)
87 f (y:ys) | x == y = True
91 unionRegSets (MkRegSet xs1) (MkRegSet xs2)
92 = MkRegSet (f xs1 xs2)
97 | a < b = a : f as (b:bs)
98 | a > b = b : f (a:as) bs
99 | otherwise = a : f as bs
101 minusRegSets (MkRegSet xs1) (MkRegSet xs2)
102 = MkRegSet (f xs1 xs2)
107 | a < b = a : f as (b:bs)
108 | a > b = f (a:as) bs
109 | otherwise = f as bs
111 intersectionRegSets (MkRegSet xs1) (MkRegSet xs2)
112 = MkRegSet (f xs1 xs2)
117 | a < b = f as (b:bs)
118 | a > b = f (a:as) bs
119 | otherwise = a : f as bs
122 %************************************************************************
124 \subsection{@RegUsage@ type; @noUsage@, @endUsage@, @regUsage@ functions}
126 %************************************************************************
128 @regUsage@ returns the sets of src and destination registers used by a
129 particular instruction. Machine registers that are pre-allocated to
130 stgRegs are filtered out, because they are uninteresting from a
131 register allocation standpoint. (We wouldn't want them to end up on
132 the free list!) As far as we are concerned, the fixed registers
133 simply don't exist (for allocation purposes, anyway).
135 regUsage doesn't need to do any trickery for jumps and such. Just
136 state precisely the regs read and written by that insn. The
137 consequences of control flow transfers, as far as register allocation
138 goes, are taken care of by @insnFuture@.
141 data RegUsage = RU RegSet RegSet
144 noUsage = RU emptyRegSet emptyRegSet
146 regUsage :: Instr -> RegUsage
148 interesting (VirtualRegI _) = True
149 interesting (VirtualRegF _) = True
150 interesting (VirtualRegD _) = True
151 interesting (RealReg i) = isFastTrue (freeReg i)
153 #if alpha_TARGET_ARCH
155 regUsage instr = case instr of
156 LD B reg addr -> usage (regAddr addr, [reg, t9])
157 LD Bu reg addr -> usage (regAddr addr, [reg, t9])
158 -- LD W reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
159 -- LD Wu reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
160 LD sz reg addr -> usage (regAddr addr, [reg])
161 LDA reg addr -> usage (regAddr addr, [reg])
162 LDAH reg addr -> usage (regAddr addr, [reg])
163 LDGP reg addr -> usage (regAddr addr, [reg])
164 LDI sz reg imm -> usage ([], [reg])
165 ST B reg addr -> usage (reg : regAddr addr, [t9, t10])
166 -- ST W reg addr -> usage (reg : regAddr addr, [t9, t10]) : UNUSED
167 ST sz reg addr -> usage (reg : regAddr addr, [])
168 CLR reg -> usage ([], [reg])
169 ABS sz ri reg -> usage (regRI ri, [reg])
170 NEG sz ov ri reg -> usage (regRI ri, [reg])
171 ADD sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
172 SADD sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
173 SUB sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
174 SSUB sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
175 MUL sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
176 DIV sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
177 REM sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
178 NOT ri reg -> usage (regRI ri, [reg])
179 AND r1 ar r2 -> usage (r1 : regRI ar, [r2])
180 ANDNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
181 OR r1 ar r2 -> usage (r1 : regRI ar, [r2])
182 ORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
183 XOR r1 ar r2 -> usage (r1 : regRI ar, [r2])
184 XORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
185 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
186 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
187 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
188 ZAP r1 ar r2 -> usage (r1 : regRI ar, [r2])
189 ZAPNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
190 CMP co r1 ar r2 -> usage (r1 : regRI ar, [r2])
191 FCLR reg -> usage ([], [reg])
192 FABS r1 r2 -> usage ([r1], [r2])
193 FNEG sz r1 r2 -> usage ([r1], [r2])
194 FADD sz r1 r2 r3 -> usage ([r1, r2], [r3])
195 FDIV sz r1 r2 r3 -> usage ([r1, r2], [r3])
196 FMUL sz r1 r2 r3 -> usage ([r1, r2], [r3])
197 FSUB sz r1 r2 r3 -> usage ([r1, r2], [r3])
198 CVTxy sz1 sz2 r1 r2 -> usage ([r1], [r2])
199 FCMP sz co r1 r2 r3 -> usage ([r1, r2], [r3])
200 FMOV r1 r2 -> usage ([r1], [r2])
203 -- We assume that all local jumps will be BI/BF/BR. JMP must be out-of-line.
204 BI cond reg lbl -> usage ([reg], [])
205 BF cond reg lbl -> usage ([reg], [])
206 JMP reg addr hint -> RU (mkRegSet (filter interesting (regAddr addr))) freeRegSet
208 BSR _ n -> RU (argRegSet n) callClobberedRegSet
209 JSR reg addr n -> RU (argRegSet n) callClobberedRegSet
214 usage (src, dst) = RU (mkRegSet (filter interesting src))
215 (mkRegSet (filter interesting dst))
217 interesting (FixedReg _) = False
220 regAddr (AddrReg r1) = [r1]
221 regAddr (AddrRegImm r1 _) = [r1]
222 regAddr (AddrImm _) = []
224 regRI (RIReg r) = [r]
227 #endif {- alpha_TARGET_ARCH -}
228 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
231 regUsage instr = case instr of
232 MOV sz src dst -> usageRW src dst
233 MOVZxL sz src dst -> usageRW src dst
234 MOVSxL sz src dst -> usageRW src dst
235 LEA sz src dst -> usageRW src dst
236 ADD sz src dst -> usageRM src dst
237 SUB sz src dst -> usageRM src dst
238 IMUL sz src dst -> usageRM src dst
239 IMUL64 sd1 sd2 -> mkRU [sd1,sd2] [sd1,sd2]
240 MUL sz src dst -> usageRM src dst
241 IQUOT sz src dst -> usageRM src dst
242 IREM sz src dst -> usageRM src dst
243 QUOT sz src dst -> usageRM src dst
244 REM sz src dst -> usageRM src dst
245 AND sz src dst -> usageRM src dst
246 OR sz src dst -> usageRM src dst
247 XOR sz src dst -> usageRM src dst
248 NOT sz op -> usageM op
249 NEGI sz op -> usageM op
250 SHL sz imm dst -> usageM dst
251 SAR sz imm dst -> usageM dst
252 SHR sz imm dst -> usageM dst
253 BT sz imm src -> mkRU (use_R src) []
255 PUSH sz op -> mkRU (use_R op) []
256 POP sz op -> mkRU [] (def_W op)
257 TEST sz src dst -> mkRU (use_R src ++ use_R dst) []
258 CMP sz src dst -> mkRU (use_R src ++ use_R dst) []
259 SETCC cond op -> mkRU [] (def_W op)
260 JXX cond lbl -> mkRU [] []
261 JMP dsts op -> mkRU (use_R op) []
262 CALL (Left imm) -> mkRU [] callClobberedRegs
263 CALL (Right reg) -> mkRU [reg] callClobberedRegs
264 CLTD -> mkRU [eax] [edx]
267 GMOV src dst -> mkRU [src] [dst]
268 GLD sz src dst -> mkRU (use_EA src) [dst]
269 GST sz src dst -> mkRU (src : use_EA dst) []
271 GLDZ dst -> mkRU [] [dst]
272 GLD1 dst -> mkRU [] [dst]
274 GFTOI src dst -> mkRU [src] [dst]
275 GDTOI src dst -> mkRU [src] [dst]
277 GITOF src dst -> mkRU [src] [dst]
278 GITOD src dst -> mkRU [src] [dst]
280 GADD sz s1 s2 dst -> mkRU [s1,s2] [dst]
281 GSUB sz s1 s2 dst -> mkRU [s1,s2] [dst]
282 GMUL sz s1 s2 dst -> mkRU [s1,s2] [dst]
283 GDIV sz s1 s2 dst -> mkRU [s1,s2] [dst]
285 GCMP sz src1 src2 -> mkRU [src1,src2] []
286 GABS sz src dst -> mkRU [src] [dst]
287 GNEG sz src dst -> mkRU [src] [dst]
288 GSQRT sz src dst -> mkRU [src] [dst]
289 GSIN sz src dst -> mkRU [src] [dst]
290 GCOS sz src dst -> mkRU [src] [dst]
291 GTAN sz src dst -> mkRU [src] [dst]
299 _ -> pprPanic "regUsage(x86)" empty
302 -- 2 operand form; first operand Read; second Written
303 usageRW :: Operand -> Operand -> RegUsage
304 usageRW op (OpReg reg) = mkRU (use_R op) [reg]
305 usageRW op (OpAddr ea) = mkRU (use_R op ++ use_EA ea) []
307 -- 2 operand form; first operand Read; second Modified
308 usageRM :: Operand -> Operand -> RegUsage
309 usageRM op (OpReg reg) = mkRU (use_R op ++ [reg]) [reg]
310 usageRM op (OpAddr ea) = mkRU (use_R op ++ use_EA ea) []
312 -- 1 operand form; operand Modified
313 usageM :: Operand -> RegUsage
314 usageM (OpReg reg) = mkRU [reg] [reg]
315 usageM (OpAddr ea) = mkRU (use_EA ea) []
317 -- Registers defd when an operand is written.
318 def_W (OpReg reg) = [reg]
319 def_W (OpAddr ea) = []
321 -- Registers used when an operand is read.
322 use_R (OpReg reg) = [reg]
323 use_R (OpImm imm) = []
324 use_R (OpAddr ea) = use_EA ea
326 -- Registers used to compute an effective address.
327 use_EA (ImmAddr _ _) = []
328 use_EA (AddrBaseIndex Nothing Nothing _) = []
329 use_EA (AddrBaseIndex (Just b) Nothing _) = [b]
330 use_EA (AddrBaseIndex Nothing (Just (i,_)) _) = [i]
331 use_EA (AddrBaseIndex (Just b) (Just (i,_)) _) = [b,i]
333 mkRU src dst = RU (regSetFromList (filter interesting src))
334 (regSetFromList (filter interesting dst))
336 #endif {- i386_TARGET_ARCH -}
337 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
338 #if sparc_TARGET_ARCH
340 regUsage instr = case instr of
341 LD sz addr reg -> usage (regAddr addr, [reg])
342 ST sz reg addr -> usage (reg : regAddr addr, [])
343 ADD x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
344 SUB x cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
345 UMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
346 SMUL cc r1 ar r2 -> usage (r1 : regRI ar, [r2])
347 RDY rd -> usage ([], [rd])
348 AND b r1 ar r2 -> usage (r1 : regRI ar, [r2])
349 ANDN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
350 OR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
351 ORN b r1 ar r2 -> usage (r1 : regRI ar, [r2])
352 XOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
353 XNOR b r1 ar r2 -> usage (r1 : regRI ar, [r2])
354 SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
355 SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
356 SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
357 SETHI imm reg -> usage ([], [reg])
358 FABS s r1 r2 -> usage ([r1], [r2])
359 FADD s r1 r2 r3 -> usage ([r1, r2], [r3])
360 FCMP e s r1 r2 -> usage ([r1, r2], [])
361 FDIV s r1 r2 r3 -> usage ([r1, r2], [r3])
362 FMOV s r1 r2 -> usage ([r1], [r2])
363 FMUL s r1 r2 r3 -> usage ([r1, r2], [r3])
364 FNEG s r1 r2 -> usage ([r1], [r2])
365 FSQRT s r1 r2 -> usage ([r1], [r2])
366 FSUB s r1 r2 r3 -> usage ([r1, r2], [r3])
367 FxTOy s1 s2 r1 r2 -> usage ([r1], [r2])
369 -- We assume that all local jumps will be BI/BF. JMP must be out-of-line.
370 JMP dst addr -> usage (regAddr addr, [])
372 CALL (Left imm) n True -> noUsage
373 CALL (Left imm) n False -> usage (argRegs n, callClobberedRegs)
374 CALL (Right reg) n True -> usage ([reg], [])
375 CALL (Right reg) n False -> usage (reg : (argRegs n), callClobberedRegs)
379 usage (src, dst) = RU (regSetFromList (filter interesting src))
380 (regSetFromList (filter interesting dst))
382 regAddr (AddrRegReg r1 r2) = [r1, r2]
383 regAddr (AddrRegImm r1 _) = [r1]
385 regRI (RIReg r) = [r]
388 #endif {- sparc_TARGET_ARCH -}
392 %************************************************************************
394 \subsection{Free, reserved, call-clobbered, and argument registers}
396 %************************************************************************
398 @freeRegs@ is the list of registers we can use in register allocation.
399 @freeReg@ (below) says if a particular register is free.
401 With a per-instruction clobber list, we might be able to get some of
402 these back, but it's probably not worth the hassle.
404 @callClobberedRegs@ ... the obvious.
406 @argRegs@: assuming a call with N arguments, what registers will be
407 used to hold arguments? (NB: it doesn't know whether the arguments
408 are integer or floating-point...)
410 findReservedRegs tells us which regs can be used as spill temporaries.
411 The list of instructions for which we are attempting allocation is
412 supplied. This is so that we can (at least for x86) examine it to
413 discover which registers are being used in a fixed way -- for example,
414 %eax and %edx are used by integer division, so they can't be used as
415 spill temporaries. However, most instruction lists don't do integer
416 division, so we don't want to rule them out altogether.
418 findReservedRegs returns not a list of spill temporaries, but a list
419 of list of them. This is so that the allocator can attempt allocating
420 with at first no spill temps, then if that fails, increasing numbers.
421 For x86 it is important that we minimise the number of regs reserved
422 as spill temporaries, since there are so few. For Alpha and Sparc
423 this isn't a concern; we just ignore the supplied code list and return
424 a singleton list which we know will satisfy all spill demands.
427 findReservedRegs :: [Instr] -> [[Reg]]
428 findReservedRegs instrs
429 #if alpha_TARGET_ARCH
430 = --[[NCG_Reserved_I1, NCG_Reserved_I2,
431 -- NCG_Reserved_F1, NCG_Reserved_F2]]
432 error "findReservedRegs: alpha"
434 #if sparc_TARGET_ARCH
435 = [[NCG_SpillTmp_I1, NCG_SpillTmp_I2,
436 NCG_SpillTmp_D1, NCG_SpillTmp_D2,
437 NCG_SpillTmp_F1, NCG_SpillTmp_F2]]
440 -- We can use %fake4 and %fake5 safely for float temps.
441 -- Int regs are more troublesome. Only %ecx and %edx are
442 -- definitely. At a pinch, we also could bag %eax if there
443 -- are no ccalls, but so far we've never encountered
444 -- a situation where three integer temporaries are necessary.
446 -- Because registers are in short supply on x86, we give the
447 -- allocator a whole bunch of possibilities, starting with zero
448 -- temporaries and working up to all that are available. This
449 -- is inefficient, but spills are pretty rare, so we don't care
450 -- if the register allocator has to try half a dozen or so possibilities
451 -- before getting to one that works.
457 = case intregs_avail of
458 [i1] -> [ [], [i1], [f1], [i1,f1], [f1,f2],
461 [i1,i2] -> [ [], [i1], [f1], [i1,i2], [i1,f1], [f1,f2],
462 [i1,i2,f1], [i1,f1,f2], [i1,i2,f1,f2] ]
468 %************************************************************************
470 \subsection{@InsnFuture@ type; @insnFuture@ function}
472 %************************************************************************
474 @insnFuture@ indicates the places we could get to following the
475 current instruction. This is used by the register allocator to
476 compute the flow edges between instructions.
480 = NoFuture -- makes a non-local jump; for the purposes of
481 -- register allocation, it exits our domain
482 | Next -- falls through to next insn
483 | Branch CLabel -- unconditional branch to the label
484 | NextOrBranch CLabel -- conditional branch to the label
485 | MultiFuture [CLabel] -- multiple specific futures
487 --instance Outputable InsnFuture where
488 -- ppr NoFuture = text "NoFuture"
489 -- ppr Next = text "Next"
490 -- ppr (Branch clbl) = text "(Branch " <> ppr clbl <> char ')'
491 -- ppr (NextOrBranch clbl) = text "(NextOrBranch " <> ppr clbl <> char ')'
497 #if alpha_TARGET_ARCH
499 -- We assume that all local jumps will be BI/BF. JMP must be out-of-line.
501 BR (ImmCLbl lbl) -> RL (lookup lbl) future
502 BI _ _ (ImmCLbl lbl) -> RL (lookup lbl `unionRegSets` live) future
503 BF _ _ (ImmCLbl lbl) -> RL (lookup lbl `unionRegSets` live) future
504 JMP _ _ _ -> RL emptyRegSet future
505 BSR _ _ -> RL live future
506 JSR _ _ _ -> RL live future
507 LABEL lbl -> RL live (FL (all `unionRegSets` live) (addToFM env lbl live))
510 #endif {- alpha_TARGET_ARCH -}
511 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
515 JXX _ clbl | isAsmTemp clbl -> NextOrBranch clbl
516 JXX _ _ -> panic "insnFuture: conditional jump to non-local label"
518 -- If the insn says what its dests are, use em!
519 JMP (DestInfo dsts) _ -> MultiFuture dsts
521 -- unconditional jump to local label
522 JMP NoDestInfo (OpImm (ImmCLbl clbl)) | isAsmTemp clbl -> Branch clbl
524 -- unconditional jump to non-local label
525 JMP NoDestInfo lbl -> NoFuture
528 JMP _ _ -> panic "insnFuture(x86): JMP wierdness"
532 #endif {- i386_TARGET_ARCH -}
533 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
534 #if sparc_TARGET_ARCH
536 -- We assume that all local jumps will be BI/BF.
537 BI ALWAYS _ (ImmCLbl clbl) -> Branch clbl
538 BI other _ (ImmCLbl clbl) -> NextOrBranch clbl
539 BI other _ _ -> panic "nativeGen(sparc):insnFuture(BI)"
541 BF ALWAYS _ (ImmCLbl clbl) -> Branch clbl
542 BF other _ (ImmCLbl clbl) -> NextOrBranch clbl
543 BF other _ _ -> panic "nativeGen(sparc):insnFuture(BF)"
545 -- CALL(terminal) must be out-of-line. JMP is not out-of-line
546 -- iff it specifies its destinations.
547 JMP NoDestInfo _ -> NoFuture -- n.b. NoFuture == MultiFuture []
548 JMP (DestInfo dsts) _ -> MultiFuture dsts
550 CALL _ _ True -> NoFuture
554 #endif {- sparc_TARGET_ARCH -}
557 %************************************************************************
559 \subsection{@patchRegs@ function}
561 %************************************************************************
563 @patchRegs@ takes an instruction (possibly with
564 MemoryReg/UnmappedReg registers) and changes all register references
565 according to the supplied environment.
568 patchRegs :: Instr -> (Reg -> Reg) -> Instr
570 #if alpha_TARGET_ARCH
572 patchRegs instr env = case instr of
573 LD sz reg addr -> LD sz (env reg) (fixAddr addr)
574 LDA reg addr -> LDA (env reg) (fixAddr addr)
575 LDAH reg addr -> LDAH (env reg) (fixAddr addr)
576 LDGP reg addr -> LDGP (env reg) (fixAddr addr)
577 LDI sz reg imm -> LDI sz (env reg) imm
578 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
579 CLR reg -> CLR (env reg)
580 ABS sz ar reg -> ABS sz (fixRI ar) (env reg)
581 NEG sz ov ar reg -> NEG sz ov (fixRI ar) (env reg)
582 ADD sz ov r1 ar r2 -> ADD sz ov (env r1) (fixRI ar) (env r2)
583 SADD sz sc r1 ar r2 -> SADD sz sc (env r1) (fixRI ar) (env r2)
584 SUB sz ov r1 ar r2 -> SUB sz ov (env r1) (fixRI ar) (env r2)
585 SSUB sz sc r1 ar r2 -> SSUB sz sc (env r1) (fixRI ar) (env r2)
586 MUL sz ov r1 ar r2 -> MUL sz ov (env r1) (fixRI ar) (env r2)
587 DIV sz un r1 ar r2 -> DIV sz un (env r1) (fixRI ar) (env r2)
588 REM sz un r1 ar r2 -> REM sz un (env r1) (fixRI ar) (env r2)
589 NOT ar reg -> NOT (fixRI ar) (env reg)
590 AND r1 ar r2 -> AND (env r1) (fixRI ar) (env r2)
591 ANDNOT r1 ar r2 -> ANDNOT (env r1) (fixRI ar) (env r2)
592 OR r1 ar r2 -> OR (env r1) (fixRI ar) (env r2)
593 ORNOT r1 ar r2 -> ORNOT (env r1) (fixRI ar) (env r2)
594 XOR r1 ar r2 -> XOR (env r1) (fixRI ar) (env r2)
595 XORNOT r1 ar r2 -> XORNOT (env r1) (fixRI ar) (env r2)
596 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
597 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
598 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
599 ZAP r1 ar r2 -> ZAP (env r1) (fixRI ar) (env r2)
600 ZAPNOT r1 ar r2 -> ZAPNOT (env r1) (fixRI ar) (env r2)
601 CMP co r1 ar r2 -> CMP co (env r1) (fixRI ar) (env r2)
602 FCLR reg -> FCLR (env reg)
603 FABS r1 r2 -> FABS (env r1) (env r2)
604 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
605 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
606 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
607 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
608 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
609 CVTxy s1 s2 r1 r2 -> CVTxy s1 s2 (env r1) (env r2)
610 FCMP s co r1 r2 r3 -> FCMP s co (env r1) (env r2) (env r3)
611 FMOV r1 r2 -> FMOV (env r1) (env r2)
612 BI cond reg lbl -> BI cond (env reg) lbl
613 BF cond reg lbl -> BF cond (env reg) lbl
614 JMP reg addr hint -> JMP (env reg) (fixAddr addr) hint
615 JSR reg addr i -> JSR (env reg) (fixAddr addr) i
618 fixAddr (AddrReg r1) = AddrReg (env r1)
619 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
620 fixAddr other = other
622 fixRI (RIReg r) = RIReg (env r)
625 #endif {- alpha_TARGET_ARCH -}
626 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
629 patchRegs instr env = case instr of
630 MOV sz src dst -> patch2 (MOV sz) src dst
631 MOVZxL sz src dst -> patch2 (MOVZxL sz) src dst
632 MOVSxL sz src dst -> patch2 (MOVSxL sz) src dst
633 LEA sz src dst -> patch2 (LEA sz) src dst
634 ADD sz src dst -> patch2 (ADD sz) src dst
635 SUB sz src dst -> patch2 (SUB sz) src dst
636 IMUL sz src dst -> patch2 (IMUL sz) src dst
637 IMUL64 sd1 sd2 -> IMUL64 (env sd1) (env sd2)
638 MUL sz src dst -> patch2 (MUL sz) src dst
639 IQUOT sz src dst -> patch2 (IQUOT sz) src dst
640 IREM sz src dst -> patch2 (IREM sz) src dst
641 QUOT sz src dst -> patch2 (QUOT sz) src dst
642 REM sz src dst -> patch2 (REM sz) src dst
643 AND sz src dst -> patch2 (AND sz) src dst
644 OR sz src dst -> patch2 (OR sz) src dst
645 XOR sz src dst -> patch2 (XOR sz) src dst
646 NOT sz op -> patch1 (NOT sz) op
647 NEGI sz op -> patch1 (NEGI sz) op
648 SHL sz imm dst -> patch1 (SHL sz imm) dst
649 SAR sz imm dst -> patch1 (SAR sz imm) dst
650 SHR sz imm dst -> patch1 (SHR sz imm) dst
651 BT sz imm src -> patch1 (BT sz imm) src
652 TEST sz src dst -> patch2 (TEST sz) src dst
653 CMP sz src dst -> patch2 (CMP sz) src dst
654 PUSH sz op -> patch1 (PUSH sz) op
655 POP sz op -> patch1 (POP sz) op
656 SETCC cond op -> patch1 (SETCC cond) op
657 JMP dsts op -> patch1 (JMP dsts) op
659 GMOV src dst -> GMOV (env src) (env dst)
660 GLD sz src dst -> GLD sz (lookupAddr src) (env dst)
661 GST sz src dst -> GST sz (env src) (lookupAddr dst)
663 GLDZ dst -> GLDZ (env dst)
664 GLD1 dst -> GLD1 (env dst)
666 GFTOI src dst -> GFTOI (env src) (env dst)
667 GDTOI src dst -> GDTOI (env src) (env dst)
669 GITOF src dst -> GITOF (env src) (env dst)
670 GITOD src dst -> GITOD (env src) (env dst)
672 GADD sz s1 s2 dst -> GADD sz (env s1) (env s2) (env dst)
673 GSUB sz s1 s2 dst -> GSUB sz (env s1) (env s2) (env dst)
674 GMUL sz s1 s2 dst -> GMUL sz (env s1) (env s2) (env dst)
675 GDIV sz s1 s2 dst -> GDIV sz (env s1) (env s2) (env dst)
677 GCMP sz src1 src2 -> GCMP sz (env src1) (env src2)
678 GABS sz src dst -> GABS sz (env src) (env dst)
679 GNEG sz src dst -> GNEG sz (env src) (env dst)
680 GSQRT sz src dst -> GSQRT sz (env src) (env dst)
681 GSIN sz src dst -> GSIN sz (env src) (env dst)
682 GCOS sz src dst -> GCOS sz (env src) (env dst)
683 GTAN sz src dst -> GTAN sz (env src) (env dst)
685 CALL (Left imm) -> instr
686 CALL (Right reg) -> CALL (Right (env reg))
696 _ -> pprPanic "patchRegs(x86)" empty
699 patch1 insn op = insn (patchOp op)
700 patch2 insn src dst = insn (patchOp src) (patchOp dst)
702 patchOp (OpReg reg) = OpReg (env reg)
703 patchOp (OpImm imm) = OpImm imm
704 patchOp (OpAddr ea) = OpAddr (lookupAddr ea)
706 lookupAddr (ImmAddr imm off) = ImmAddr imm off
707 lookupAddr (AddrBaseIndex base index disp)
708 = AddrBaseIndex (lookupBase base) (lookupIndex index) disp
710 lookupBase Nothing = Nothing
711 lookupBase (Just r) = Just (env r)
713 lookupIndex Nothing = Nothing
714 lookupIndex (Just (r,i)) = Just (env r, i)
716 #endif {- i386_TARGET_ARCH -}
717 -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
718 #if sparc_TARGET_ARCH
720 patchRegs instr env = case instr of
721 LD sz addr reg -> LD sz (fixAddr addr) (env reg)
722 ST sz reg addr -> ST sz (env reg) (fixAddr addr)
723 ADD x cc r1 ar r2 -> ADD x cc (env r1) (fixRI ar) (env r2)
724 SUB x cc r1 ar r2 -> SUB x cc (env r1) (fixRI ar) (env r2)
725 UMUL cc r1 ar r2 -> UMUL cc (env r1) (fixRI ar) (env r2)
726 SMUL cc r1 ar r2 -> SMUL cc (env r1) (fixRI ar) (env r2)
727 RDY rd -> RDY (env rd)
728 AND b r1 ar r2 -> AND b (env r1) (fixRI ar) (env r2)
729 ANDN b r1 ar r2 -> ANDN b (env r1) (fixRI ar) (env r2)
730 OR b r1 ar r2 -> OR b (env r1) (fixRI ar) (env r2)
731 ORN b r1 ar r2 -> ORN b (env r1) (fixRI ar) (env r2)
732 XOR b r1 ar r2 -> XOR b (env r1) (fixRI ar) (env r2)
733 XNOR b r1 ar r2 -> XNOR b (env r1) (fixRI ar) (env r2)
734 SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
735 SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
736 SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
737 SETHI imm reg -> SETHI imm (env reg)
738 FABS s r1 r2 -> FABS s (env r1) (env r2)
739 FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
740 FCMP e s r1 r2 -> FCMP e s (env r1) (env r2)
741 FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
742 FMOV s r1 r2 -> FMOV s (env r1) (env r2)
743 FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
744 FNEG s r1 r2 -> FNEG s (env r1) (env r2)
745 FSQRT s r1 r2 -> FSQRT s (env r1) (env r2)
746 FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
747 FxTOy s1 s2 r1 r2 -> FxTOy s1 s2 (env r1) (env r2)
748 JMP dsts addr -> JMP dsts (fixAddr addr)
749 CALL (Left i) n t -> CALL (Left i) n t
750 CALL (Right r) n t -> CALL (Right (env r)) n t
753 fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
754 fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
756 fixRI (RIReg r) = RIReg (env r)
759 #endif {- sparc_TARGET_ARCH -}
762 %************************************************************************
764 \subsection{@spillReg@ and @loadReg@ functions}
766 %************************************************************************
768 Spill to memory, and load it back...
770 JRS, 000122: on x86, don't spill directly above the stack pointer,
771 since some insn sequences (int <-> conversions) use this as a temp
772 location. Leave 8 words (ie, 64 bytes for a 64-bit arch) of slop.
776 spillSlotSize = IF_ARCH_alpha( 8, IF_ARCH_sparc( 8, IF_ARCH_i386( 12, )))
779 maxSpillSlots = ((rESERVED_C_STACK_BYTES - 64) `div` spillSlotSize) - 1
781 -- convert a spill slot number to a *byte* offset, with no sign:
782 -- decide on a per arch basis whether you are spilling above or below
783 -- the C stack pointer.
784 spillSlotToOffset :: Int -> Int
785 spillSlotToOffset slot
786 | slot >= 0 && slot < maxSpillSlots
787 = 64 + spillSlotSize * slot
789 = pprPanic "spillSlotToOffset:"
790 (text "invalid spill location: " <> int slot)
792 vregToSpillSlot :: FiniteMap VRegUnique Int -> VRegUnique -> Int
793 vregToSpillSlot vreg_to_slot_map u
794 = case lookupFM vreg_to_slot_map u of
796 Nothing -> pprPanic "vregToSpillSlot: unmapped vreg" (pprVRegUnique u)
799 spillReg, loadReg :: FiniteMap VRegUnique Int -> Int -> Reg -> Reg -> Instr
801 spillReg vreg_to_slot_map delta dyn vreg
803 = let slot_no = vregToSpillSlot vreg_to_slot_map (getVRegUnique vreg)
804 off = spillSlotToOffset slot_no
806 {-Alpha: spill below the stack pointer (?)-}
807 IF_ARCH_alpha( ST sz dyn (spRel (- (off `div` 8)))
809 {-I386: spill above stack pointer leaving 3 words/spill-}
810 ,IF_ARCH_i386 ( let off_w = (off-delta) `div` 4
811 in case regClass vreg of
812 RcInteger -> MOV L (OpReg dyn) (OpAddr (spRel off_w))
813 _ -> GST F80 dyn (spRel off_w) -- RcFloat/RcDouble
815 {-SPARC: spill below frame pointer leaving 2 words/spill-}
817 let off_w = 1 + (off `div` 4)
818 sz = case regClass vreg of
822 in ST sz dyn (fpRel (- off_w))
826 loadReg vreg_to_slot_map delta vreg dyn
828 = let slot_no = vregToSpillSlot vreg_to_slot_map (getVRegUnique vreg)
829 off = spillSlotToOffset slot_no
831 IF_ARCH_alpha( LD sz dyn (spRel (- (off `div` 8)))
833 ,IF_ARCH_i386 ( let off_w = (off-delta) `div` 4
834 in case regClass vreg of
835 RcInteger -> MOV L (OpAddr (spRel off_w)) (OpReg dyn)
836 _ -> GLD F80 (spRel off_w) dyn -- RcFloat/RcDouble
839 let off_w = 1 + (off `div` 4)
840 sz = case regClass vreg of
844 in LD sz (fpRel (- off_w)) dyn