1 -----------------------------------------------------------------------------
3 -- The register allocator
5 -- (c) The University of Glasgow 2004
7 -----------------------------------------------------------------------------
10 The algorithm is roughly:
12 1) Compute strongly connected components of the basic block list.
14 2) Compute liveness (mapping from pseudo register to
17 3) Walk instructions in each basic block. We keep track of
18 (a) Free real registers (a bitmap?)
19 (b) Current assignment of temporaries to machine registers and/or
20 spill slots (call this the "assignment").
21 (c) Partial mapping from basic block ids to a virt-to-loc mapping.
22 When we first encounter a branch to a basic block,
23 we fill in its entry in this table with the current mapping.
26 (a) For each real register clobbered by this instruction:
27 If a temporary resides in it,
28 If the temporary is live after this instruction,
29 Move the temporary to another (non-clobbered & free) reg,
30 or spill it to memory. Mark the temporary as residing
31 in both memory and a register if it was spilled (it might
32 need to be read by this instruction).
33 (ToDo: this is wrong for jump instructions?)
35 (b) For each temporary *read* by the instruction:
36 If the temporary does not have a real register allocation:
37 - Allocate a real register from the free list. If
39 - Find a temporary to spill. Pick one that is
40 not used in this instruction (ToDo: not
42 - generate a spill instruction
43 - If the temporary was previously spilled,
44 generate an instruction to read the temp from its spill loc.
45 (optimisation: if we can see that a real register is going to
46 be used soon, then don't use it for allocation).
48 (c) Update the current assignment
50 (d) If the intstruction is a branch:
51 if the destination block already has a register assignment,
52 Generate a new block with fixup code and redirect the
53 jump to the new block.
55 Update the block id->assignment mapping with the current
58 (e) Delete all register assignments for temps which are read
59 (only) and die here. Update the free register list.
61 (f) Mark all registers clobbered by this instruction as not free,
62 and mark temporaries which have been spilled due to clobbering
63 as in memory (step (a) marks then as in both mem & reg).
65 (g) For each temporary *written* by this instruction:
66 Allocate a real register as for (b), spilling something
68 - except when updating the assignment, drop any memory
69 locations that the temporary was previously in, since
70 they will be no longer valid after this instruction.
72 (h) Delete all register assignments for temps which are
73 written and die here (there should rarely be any). Update
74 the free register list.
76 (i) Rewrite the instruction with the new mapping.
78 (j) For each spilled reg known to be now dead, re-add its stack slot
83 module RegisterAlloc (
87 #include "HsVersions.h"
88 #include "../includes/ghcconfig.h"
97 import Unique ( Uniquable(..), Unique, getUnique )
103 import Maybe ( fromJust )
105 import List ( nub, partition )
106 import Monad ( when )
110 -- -----------------------------------------------------------------------------
113 type RegSet = UniqSet Reg
115 type RegMap a = UniqFM a
116 emptyRegMap = emptyUFM
118 type BlockMap a = UniqFM a
119 emptyBlockMap = emptyUFM
121 -- A basic block where the isntructions are annotated with the registers
122 -- which are no longer live in the *next* instruction in this sequence.
123 -- (NB. if the instruction is a jump, these registers might still be live
124 -- at the jump target(s) - you have to check the liveness at the destination
125 -- block to find out).
127 = GenBasicBlock (Instr,
128 [Reg], -- registers read (only) which die
129 [Reg]) -- registers written which die
131 -- -----------------------------------------------------------------------------
132 -- The free register set
134 -- This needs to be *efficient*
136 {- Here's an inefficient 'executable specification' of the FreeRegs data type:
137 type FreeRegs = [RegNo]
140 releaseReg n f = if n `elem` f then f else (n : f)
141 initFreeRegs = allocatableRegs
142 getFreeRegs cls f = filter ( (==cls) . regClass . RealReg ) f
143 allocateReg f r = filter (/= r) f
146 #if defined(powerpc_TARGET_ARCH)
148 -- The PowerPC has 32 integer and 32 floating point registers.
149 -- This is 32bit PowerPC, so Word64 is inefficient - two Word32s are much
151 -- Note that when getFreeRegs scans for free registers, it starts at register
152 -- 31 and counts down. This is a hack for the PowerPC - the higher-numbered
153 -- registers are callee-saves, while the lower regs are caller-saves, so it
154 -- makes sense to start at the high end.
155 -- Apart from that, the code does nothing PowerPC-specific, so feel free to
156 -- add your favourite platform to the #if (if you have 64 registers but only
159 data FreeRegs = FreeRegs !Word32 !Word32
161 noFreeRegs = FreeRegs 0 0
162 releaseReg r (FreeRegs g f)
163 | r > 31 = FreeRegs g (f .|. (1 `shiftL` (fromIntegral r - 32)))
164 | otherwise = FreeRegs (g .|. (1 `shiftL` fromIntegral r)) f
166 initFreeRegs :: FreeRegs
167 initFreeRegs = foldr releaseReg noFreeRegs allocatableRegs
169 getFreeRegs cls (FreeRegs g f)
170 | RcDouble <- cls = go f (0x80000000) 63
171 | RcInteger <- cls = go g (0x80000000) 31
174 go x m i | x .&. m /= 0 = i : (go x (m `shiftR` 1) $! i-1)
175 | otherwise = go x (m `shiftR` 1) $! i-1
177 allocateReg (FreeRegs g f) r
178 | r > 31 = FreeRegs g (f .&. complement (1 `shiftL` (fromIntegral r - 32)))
179 | otherwise = FreeRegs (g .&. complement (1 `shiftL` fromIntegral r)) f
183 -- If we have less than 32 registers, or if we have efficient 64-bit words,
184 -- we will just use a single bitfield.
186 #if defined(alpha_TARGET_ARCH)
187 type FreeRegs = Word64
189 type FreeRegs = Word32
192 noFreeRegs :: FreeRegs
195 releaseReg :: RegNo -> FreeRegs -> FreeRegs
196 releaseReg n f = f .|. (1 `shiftL` n)
198 initFreeRegs :: FreeRegs
199 initFreeRegs = foldr releaseReg noFreeRegs allocatableRegs
201 getFreeRegs :: RegClass -> FreeRegs -> [RegNo] -- lazilly
202 getFreeRegs cls f = go f 0
205 | n .&. 1 /= 0 && regClass (RealReg m) == cls
206 = m : (go (n `shiftR` 1) $! (m+1))
208 = go (n `shiftR` 1) $! (m+1)
209 -- ToDo: there's no point looking through all the integer registers
210 -- in order to find a floating-point one.
212 allocateReg :: FreeRegs -> RegNo -> FreeRegs
213 allocateReg f r = f .&. complement (1 `shiftL` fromIntegral r)
216 -- -----------------------------------------------------------------------------
217 -- The free list of stack slots
219 -- This doesn't need to be so efficient. It also doesn't really need to be
220 -- maintained as a set, so we just use an ordinary list (lazy, because it
221 -- contains all the possible stack slots and there are lots :-).
224 type FreeStack = [StackSlot]
226 completelyFreeStack :: FreeStack
227 completelyFreeStack = [0..maxSpillSlots]
229 getFreeStackSlot :: FreeStack -> (FreeStack,Int)
230 getFreeStackSlot (slot:stack) = (stack,slot)
232 freeStackSlot :: FreeStack -> Int -> FreeStack
233 freeStackSlot stack slot = slot:stack
236 -- -----------------------------------------------------------------------------
237 -- Top level of the register allocator
239 regAlloc :: NatCmmTop -> NatCmmTop
240 regAlloc (CmmData sec d) = CmmData sec d
241 regAlloc (CmmProc info lbl params [])
242 = CmmProc info lbl params [] -- no blocks to run the regalloc on
243 regAlloc (CmmProc info lbl params blocks@(first:rest))
244 = -- pprTrace "Liveness" (ppr block_live) $
245 CmmProc info lbl params (first':rest')
247 first_id = blockId first
248 sccs = sccBlocks blocks
249 (ann_sccs, block_live) = computeLiveness sccs
250 final_blocks = linearRegAlloc block_live ann_sccs
251 ((first':_),rest') = partition ((== first_id) . blockId) final_blocks
254 sccBlocks :: [NatBasicBlock] -> [SCC NatBasicBlock]
255 sccBlocks blocks = stronglyConnComp graph
257 getOutEdges :: [Instr] -> [BlockId]
258 getOutEdges instrs = foldr jumpDests [] instrs
260 graph = [ (block, getUnique id, map getUnique (getOutEdges instrs))
261 | block@(BasicBlock id instrs) <- blocks ]
264 -- -----------------------------------------------------------------------------
265 -- Computing liveness
268 :: [SCC NatBasicBlock]
269 -> ([SCC AnnBasicBlock], -- instructions annotated with list of registers
270 -- which are "dead after this instruction".
271 BlockMap RegSet) -- blocks annontated with set of live registers
272 -- on entry to the block.
274 -- NOTE: on entry, the SCCs are in "reverse" order: later blocks may transfer
275 -- control to earlier ones only. The SCCs returned are in the *opposite*
276 -- order, which is exactly what we want for the next pass.
279 = livenessSCCs emptyBlockMap [] sccs
283 -> [SCC AnnBasicBlock] -- accum
284 -> [SCC NatBasicBlock]
285 -> ([SCC AnnBasicBlock], BlockMap RegSet)
287 livenessSCCs blockmap done [] = (done, blockmap)
288 livenessSCCs blockmap done
289 (AcyclicSCC (BasicBlock block_id instrs) : sccs) =
290 {- pprTrace "live instrs" (ppr (getUnique block_id) $$
291 vcat (map (\(instr,regs) -> docToSDoc (pprInstr instr) $$ ppr regs) instrs')) $
293 livenessSCCs blockmap'
294 (AcyclicSCC (BasicBlock block_id instrs'):done) sccs
295 where (live,instrs') = liveness emptyUniqSet blockmap []
297 blockmap' = addToUFM blockmap block_id live
298 -- TODO: cope with recursive blocks
300 liveness :: RegSet -- live regs
301 -> BlockMap RegSet -- live regs on entry to other BBs
302 -> [(Instr,[Reg],[Reg])] -- instructions (accum)
303 -> [Instr] -- instructions
304 -> (RegSet, [(Instr,[Reg],[Reg])])
306 liveness liveregs blockmap done [] = (liveregs, done)
307 liveness liveregs blockmap done (instr:instrs)
308 = liveness liveregs2 blockmap ((instr,r_dying,w_dying):done) instrs
310 RU read written = regUsage instr
312 -- registers that were written here are dead going backwards.
313 -- registers that were read here are live going backwards.
314 liveregs1 = (liveregs `delListFromUniqSet` written)
315 `addListToUniqSet` read
317 -- union in the live regs from all the jump destinations of this
319 targets = jumpDests instr [] -- where we go from here
320 liveregs2 = unionManyUniqSets
321 (liveregs1 : map (lookItUp "liveness" blockmap)
324 -- registers that are not live beyond this point, are recorded
326 r_dying = [ reg | reg <- read, reg `notElem` written,
327 not (elementOfUniqSet reg liveregs) ]
329 w_dying = [ reg | reg <- written,
330 not (elementOfUniqSet reg liveregs) ]
332 -- -----------------------------------------------------------------------------
333 -- Linear sweep to allocate registers
335 data Loc = InReg {-# UNPACK #-} !RegNo
336 | InMem {-# UNPACK #-} !Int -- stack slot
337 | InBoth {-# UNPACK #-} !RegNo
338 {-# UNPACK #-} !Int -- stack slot
342 A temporary can be marked as living in both a register and memory
343 (InBoth), for example if it was recently loaded from a spill location.
344 This makes it cheap to spill (no save instruction required), but we
345 have to be careful to turn this into InReg if the value in the
348 This is also useful when a temporary is about to be clobbered. We
349 save it in a spill location, but mark it as InBoth because the current
350 instruction might still want to read it.
354 instance Outputable Loc where
355 ppr l = text (show l)
359 :: BlockMap RegSet -- live regs on entry to each basic block
360 -> [SCC AnnBasicBlock] -- instructions annotated with "deaths"
362 linearRegAlloc block_live sccs = linearRA_SCCs emptyBlockMap sccs
366 -> [SCC AnnBasicBlock]
368 linearRA_SCCs block_assig [] = []
369 linearRA_SCCs block_assig
370 (AcyclicSCC (BasicBlock id instrs) : sccs)
371 = BasicBlock id instrs' : linearRA_SCCs block_assig' sccs
373 (block_assig',(instrs',fixups)) =
374 case lookupUFM block_assig id of
375 -- no prior info about this block: assume everything is
376 -- free and the assignment is empty.
378 runR block_assig initFreeRegs
379 emptyRegMap completelyFreeStack $
380 linearRA [] [] instrs
381 Just (freeregs,stack,assig) ->
382 runR block_assig freeregs assig stack $
383 linearRA [] [] instrs
385 linearRA :: [Instr] -> [NatBasicBlock] -> [(Instr,[Reg],[Reg])]
386 -> RegM ([Instr], [NatBasicBlock])
387 linearRA instr_acc fixups [] =
388 return (reverse instr_acc, fixups)
389 linearRA instr_acc fixups (instr:instrs) = do
390 (instr_acc', new_fixups) <- raInsn block_live instr_acc instr
391 linearRA instr_acc' (new_fixups++fixups) instrs
393 -- -----------------------------------------------------------------------------
394 -- Register allocation for a single instruction
396 type BlockAssignment = BlockMap (FreeRegs, FreeStack, RegMap Loc)
398 raInsn :: BlockMap RegSet -- Live temporaries at each basic block
399 -> [Instr] -- new instructions (accum.)
400 -> (Instr,[Reg],[Reg]) -- the instruction (with "deaths")
402 [Instr], -- new instructions
403 [NatBasicBlock] -- extra fixup blocks
406 raInsn block_live new_instrs (instr@(DELTA n), _, _) = do
408 return (new_instrs, [])
410 raInsn block_live new_instrs (instr, r_dying, w_dying) = do
413 -- If we have a reg->reg move between virtual registers, where the
414 -- src register is not live after this instruction, and the dst
415 -- register does not already have an assignment, then we can
416 -- eliminate the instruction.
417 case isRegRegMove instr of
419 | src `elem` r_dying,
421 Just loc <- lookupUFM assig src,
422 not (dst `elemUFM` assig) -> do
423 setAssigR (addToUFM (delFromUFM assig src) dst loc)
424 return (new_instrs, [])
426 other -> genRaInsn block_live new_instrs instr r_dying w_dying
429 genRaInsn block_live new_instrs instr r_dying w_dying = do
431 RU read written = regUsage instr
433 (real_written1,virt_written) = partition isRealReg written
435 real_written = [ r | RealReg r <- real_written1 ]
437 -- we don't need to do anything with real registers that are
438 -- only read by this instr. (the list is typically ~2 elements,
439 -- so using nub isn't a problem).
440 virt_read = nub (filter isVirtualReg read)
443 -- (a) save any temporaries which will be clobbered by this instruction
444 (clobber_saves, assig_adj) <- saveClobberedTemps real_written r_dying
446 -- freeregs <- getFreeRegsR
447 -- assig <- getAssigR
448 -- pprTrace "raInsn" (docToSDoc (pprInstr instr) $$ ppr r_dying <+> ppr w_dying $$ ppr virt_read <+> ppr virt_written $$ text (show freeregs) $$ ppr assig) $ do
450 -- (b), (c) allocate real regs for all regs read by this instruction.
451 (r_spills, r_allocd) <-
452 allocateRegsAndSpill True{-reading-} virt_read [] [] virt_read
454 -- (d) Update block map for new destinations
455 -- NB. do this before removing dead regs from the assignment, because
456 -- these dead regs might in fact be live in the jump targets (they're
457 -- only dead in the code that follows in the current basic block).
458 (fixup_blocks, adjusted_instr)
459 <- joinToTargets block_live [] instr (jumpDests instr [])
461 -- (e) Delete all register assignments for temps which are read
462 -- (only) and die here. Update the free register list.
465 -- (f) Mark regs which are clobbered as unallocatable
466 clobberRegs real_written assig_adj
468 -- (g) Allocate registers for temporaries *written* (only)
469 (w_spills, w_allocd) <-
470 allocateRegsAndSpill False{-writing-} virt_written [] [] virt_written
472 -- (h) Release registers for temps which are written here and not
477 -- (i) Patch the instruction
478 patch_map = listToUFM [ (t,RealReg r) |
479 (t,r) <- zip virt_read r_allocd
480 ++ zip virt_written w_allocd ]
482 patched_instr = patchRegs adjusted_instr patchLookup
483 patchLookup x = case lookupUFM patch_map x of
488 -- pprTrace "patched" (docToSDoc (pprInstr patched_instr)) $ do
490 -- (j) free up stack slots for dead spilled regs
491 -- TODO (can't be bothered right now)
493 return (patched_instr : w_spills ++ reverse r_spills
494 ++ clobber_saves ++ new_instrs,
497 -- -----------------------------------------------------------------------------
500 releaseRegs regs = do
505 loop assig free [] = do setAssigR assig; setFreeRegsR free; return ()
506 loop assig free (RealReg r : rs) = loop assig (releaseReg r free) rs
507 loop assig free (r:rs) =
508 case lookupUFM assig r of
509 Just (InBoth real _) -> loop (delFromUFM assig r) (releaseReg real free) rs
510 Just (InReg real) -> loop (delFromUFM assig r) (releaseReg real free) rs
511 _other -> loop (delFromUFM assig r) free rs
513 -- -----------------------------------------------------------------------------
514 -- Clobber real registers
517 For each temp in a register that is going to be clobbered:
518 - if the temp dies after this instruction, do nothing
519 - otherwise, put it somewhere safe (another reg if possible,
520 otherwise spill and record InBoth in the assignment).
522 for allocateRegs on the temps *read*,
523 - clobbered regs are allocatable.
525 for allocateRegs on the temps *written*,
526 - clobbered regs are not allocatable.
530 :: [RegNo] -- real registers clobbered by this instruction
531 -> [Reg] -- registers which are no longer live after this insn
533 [Instr], -- return: instructions to spill any temps that will
534 [(Unique,Loc)] -- be clobbered, and adjustments to make to the
535 ) -- assignment after reading has taken place.
537 saveClobberedTemps [] _ = return ([],[]) -- common case
538 saveClobberedTemps clobbered dying = do
541 to_spill = [ (temp,reg) | (temp, InReg reg) <- ufmToList assig,
542 reg `elem` clobbered,
543 temp `notElem` map getUnique dying ]
545 (instrs,assig_adj,assig') <- clobber assig [] [] to_spill
547 return (instrs,assig_adj)
549 clobber assig instrs adj [] = return (instrs,adj,assig)
550 clobber assig instrs adj ((temp,reg):rest)
552 (spill,slot) <- spillR (RealReg reg)
553 clobber (addToUFM assig temp (InBoth reg slot))
554 (spill:instrs) ((temp,InMem slot):adj) rest
555 --ToDo: copy it to another register if possible
558 clobberRegs :: [RegNo] -> [(Unique,Loc)] -> RegM ()
559 clobberRegs [] _ = return () -- common case
560 clobberRegs clobbered assig_adj = do
561 freeregs <- getFreeRegsR
562 setFreeRegsR (foldl allocateReg freeregs clobbered)
564 setAssigR (addListToUFM assig assig_adj)
566 -- -----------------------------------------------------------------------------
567 -- allocateRegsAndSpill
569 -- This function does several things:
570 -- For each temporary referred to by this instruction,
571 -- we allocate a real register (spilling another temporary if necessary).
572 -- We load the temporary up from memory if necessary.
573 -- We also update the register assignment in the process, and
574 -- the list of free registers and free stack slots.
577 :: Bool -- True <=> reading (load up spilled regs)
578 -> [Reg] -- don't push these out
579 -> [Instr] -- spill insns
580 -> [RegNo] -- real registers allocated (accum.)
581 -> [Reg] -- temps to allocate
582 -> RegM ([Instr], [RegNo])
584 allocateRegsAndSpill reading keep spills alloc []
585 = return (spills,reverse alloc)
587 allocateRegsAndSpill reading keep spills alloc (r:rs) = do
589 case lookupUFM assig r of
590 -- case (1a): already in a register
591 Just (InReg my_reg) ->
592 allocateRegsAndSpill reading keep spills (my_reg:alloc) rs
594 -- case (1b): already in a register (and memory)
595 -- NB1. if we're writing this register, update its assignemnt to be
596 -- InReg, because the memory value is no longer valid.
597 -- NB2. This is why we must process written registers here, even if they
598 -- are also read by the same instruction.
599 Just (InBoth my_reg mem) -> do
600 when (not reading) (setAssigR (addToUFM assig r (InReg my_reg)))
601 allocateRegsAndSpill reading keep spills (my_reg:alloc) rs
603 -- Not already in a register, so we need to find a free one...
605 freeregs <- getFreeRegsR
607 case getFreeRegs (regClass r) freeregs of
609 -- case (2): we have a free register
611 spills' <- do_load reading loc my_reg spills
613 | Just (InMem slot) <- loc, reading = InBoth my_reg slot
614 | otherwise = InReg my_reg
615 setAssigR (addToUFM assig r $! new_loc)
616 setFreeRegsR (allocateReg freeregs my_reg)
617 allocateRegsAndSpill reading keep spills' (my_reg:alloc) rs
619 -- case (3): we need to push something out to free up a register
622 keep' = map getUnique keep
623 candidates1 = [ (temp,reg,mem)
624 | (temp, InBoth reg mem) <- ufmToList assig,
625 temp `notElem` keep', regClass (RealReg reg) == regClass r ]
626 candidates2 = [ (temp,reg)
627 | (temp, InReg reg) <- ufmToList assig,
628 temp `notElem` keep', regClass (RealReg reg) == regClass r ]
630 ASSERT2(not (null candidates1 && null candidates2), ppr assig) do
634 -- we have a temporary that is in both register and mem,
635 -- just free up its register for use.
637 (temp,my_reg,slot):_ -> do
638 spills' <- do_load reading loc my_reg spills
640 assig1 = addToUFM assig temp (InMem slot)
641 assig2 = addToUFM assig1 r (InReg my_reg)
644 allocateRegsAndSpill reading keep spills' (my_reg:alloc) rs
646 -- otherwise, we need to spill a temporary that currently
647 -- resides in a register.
650 (temp_to_push_out, my_reg) = head candidates2
651 -- TODO: plenty of room for optimisation in choosing which temp
652 -- to spill. We just pick the first one that isn't used in
653 -- the current instruction for now.
655 (spill_insn,slot) <- spillR (RealReg my_reg)
657 assig1 = addToUFM assig temp_to_push_out (InMem slot)
658 assig2 = addToUFM assig1 r (InReg my_reg)
661 spills' <- do_load reading loc my_reg spills
662 allocateRegsAndSpill reading keep (spill_insn:spills')
665 -- load up a spilled temporary if we need to
666 do_load True (Just (InMem slot)) reg spills = do
667 insn <- loadR (RealReg reg) slot
668 return (insn : spills)
669 do_load _ _ _ spills =
672 -- -----------------------------------------------------------------------------
673 -- Joining a jump instruction to its targets
675 -- The first time we encounter a jump to a particular basic block, we
676 -- record the assignment of temporaries. The next time we encounter a
677 -- jump to the same block, we compare our current assignment to the
678 -- stored one. They might be different if spilling has occrred in one
679 -- branch; so some fixup code will be required to match up the
687 -> RegM ([NatBasicBlock], Instr)
689 joinToTargets block_live new_blocks instr []
690 = return (new_blocks, instr)
691 joinToTargets block_live new_blocks instr (dest:dests) = do
692 block_assig <- getBlockAssigR
695 -- adjust the assignment to remove any registers which are not
696 -- live on entry to the destination block.
698 listToUFM [ (reg,loc) | reg <- live,
699 Just loc <- [lookupUFM assig reg] ]
701 case lookupUFM block_assig dest of
702 -- Nothing <=> this is the first time we jumped to this
705 freeregs <- getFreeRegsR
707 setBlockAssigR (addToUFM block_assig dest
708 (freeregs,stack,adjusted_assig))
709 joinToTargets block_live new_blocks instr dests
711 Just (freeregs,stack,dest_assig)
712 | ufmToList dest_assig == ufmToList adjusted_assig
713 -> -- ok, the assignments match
714 joinToTargets block_live new_blocks instr dests
716 -> -- need fixup code
717 panic "joinToTargets: ToDo: need fixup code"
719 live = uniqSetToList (lookItUp "joinToTargets" block_live dest)
721 -- -----------------------------------------------------------------------------
722 -- The register allocator's monad.
724 -- Here we keep all the state that the register allocator keeps track
725 -- of as it walks the instructions in a basic block.
729 ra_blockassig :: BlockAssignment,
730 -- The current mapping from basic blocks to
731 -- the register assignments at the beginning of that block.
732 ra_freeregs :: FreeRegs, -- free machine registers
733 ra_assig :: RegMap Loc, -- assignment of temps to locations
734 ra_delta :: Int, -- current stack delta
735 ra_stack :: FreeStack -- free stack slots for spilling
738 newtype RegM a = RegM { unReg :: RA_State -> (# RA_State, a #) }
740 instance Monad RegM where
741 m >>= k = RegM $ \s -> case unReg m s of { (# s, a #) -> unReg (k a) s }
742 return a = RegM $ \s -> (# s, a #)
744 runR :: BlockAssignment -> FreeRegs -> RegMap Loc -> FreeStack -> RegM a ->
746 runR block_assig freeregs assig stack thing =
747 case unReg thing (RA_State{ ra_blockassig=block_assig, ra_freeregs=freeregs,
748 ra_assig=assig, ra_delta=0{-???-}, ra_stack=stack }) of
749 (# RA_State{ ra_blockassig=block_assig }, returned_thing #)
750 -> (block_assig, returned_thing)
752 spillR :: Reg -> RegM (Instr, Int)
753 spillR reg = RegM $ \ s@RA_State{ra_delta=delta, ra_stack=stack} ->
754 let (stack',slot) = getFreeStackSlot stack
755 instr = mkSpillInstr reg delta slot
757 (# s{ra_stack=stack'}, (instr,slot) #)
759 loadR :: Reg -> Int -> RegM Instr
760 loadR reg slot = RegM $ \ s@RA_State{ra_delta=delta, ra_stack=stack} ->
761 (# s, mkLoadInstr reg delta slot #)
763 freeSlotR :: Int -> RegM ()
764 freeSlotR slot = RegM $ \ s@RA_State{ra_stack=stack} ->
765 (# s{ra_stack=freeStackSlot stack slot}, () #)
767 getFreeRegsR :: RegM FreeRegs
768 getFreeRegsR = RegM $ \ s@RA_State{ra_freeregs = freeregs} ->
771 setFreeRegsR :: FreeRegs -> RegM ()
772 setFreeRegsR regs = RegM $ \ s ->
773 (# s{ra_freeregs = regs}, () #)
775 getAssigR :: RegM (RegMap Loc)
776 getAssigR = RegM $ \ s@RA_State{ra_assig = assig} ->
779 setAssigR :: RegMap Loc -> RegM ()
780 setAssigR assig = RegM $ \ s ->
781 (# s{ra_assig=assig}, () #)
783 getStackR :: RegM FreeStack
784 getStackR = RegM $ \ s@RA_State{ra_stack = stack} ->
787 setStackR :: FreeStack -> RegM ()
788 setStackR stack = RegM $ \ s ->
789 (# s{ra_stack=stack}, () #)
791 getBlockAssigR :: RegM BlockAssignment
792 getBlockAssigR = RegM $ \ s@RA_State{ra_blockassig = assig} ->
795 setBlockAssigR :: BlockAssignment -> RegM ()
796 setBlockAssigR assig = RegM $ \ s ->
797 (# s{ra_blockassig = assig}, () #)
799 setDeltaR :: Int -> RegM ()
800 setDeltaR n = RegM $ \ s ->
801 (# s{ra_delta = n}, () #)
803 -- -----------------------------------------------------------------------------
807 my_fromJust s p Nothing = pprPanic ("fromJust: " ++ s) p
808 my_fromJust s p (Just x) = x
810 my_fromJust _ _ = fromJust
813 lookItUp :: Uniquable b => String -> UniqFM a -> b -> a
814 lookItUp str fm x = my_fromJust str (ppr (getUnique x)) (lookupUFM fm x)