1 /* -----------------------------------------------------------------------------
2 * $Id: MachRegs.h,v 1.14 2003/08/29 16:00:26 simonmar Exp $
4 * (c) The GHC Team, 1998-1999
6 * Registers used in STG code. Might or might not correspond to
7 * actual machine registers.
9 * ---------------------------------------------------------------------------*/
14 /* This file is #included into Haskell code in the compiler: #defines
15 * only in here please.
18 /* define NO_REGS to omit register declarations - used in RTS C code
19 * that needs all the STG definitions but not the global register
24 /* ----------------------------------------------------------------------------
25 Caller saves and callee-saves regs.
27 Caller-saves regs have to be saved around C-calls made from STG
28 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
29 is designated caller-saves in that machine's C calling convention.
31 Additionally, the following macros should be defined when
33 CALLER_SAVES_USER one or more of R<n>, F, D
36 CALLER_SAVES_SYSTEM one or more of Sp, SpLim, Hp, HpLim
39 This is so that the callWrapper mechanism knows which kind of
40 wrapper to generate for certain types of C call.
41 -------------------------------------------------------------------------- */
43 /* -----------------------------------------------------------------------------
44 The DEC Alpha register mapping
47 \tr{$9}--\tr{$14} are our ``prize'' callee-save registers.
48 \tr{$15} is the frame pointer, and \tr{$16}--\tr{$21} are argument
49 registers. (These are off-limits.) We can steal some of the \tr{$22}-and-up
50 caller-save registers provided we do the appropriate save/restore stuff.
52 \tr{$f2}--\tr{$f9} are some callee-save floating-point registers.
54 We cannot use \tr{$23} (aka t9), \tr{$24} (aka t10), \tr{$25} (aka
55 t11), \tr{$27} (aka pv), or \tr{$28} (aka at), because they are
56 occasionally required by the assembler to handle non-primitive
57 instructions (e.g. ldb, remq). Sigh!
77 -------------------------------------------------------------------------- */
79 #if defined(alpha_TARGET_ARCH)
80 # define REG(x) __asm__("$" #x)
82 # define CALLER_SAVES_R2
83 # define CALLER_SAVES_R3
84 # define CALLER_SAVES_R4
85 # define CALLER_SAVES_R5
86 # define CALLER_SAVES_R6
87 # define CALLER_SAVES_R7
88 # define CALLER_SAVES_R8
90 # define CALLER_SAVES_USER
110 # define REG_SpLim 11
113 # define REG_HpLim 13
115 # define NCG_Reserved_I1 22
116 # define NCG_Reserved_I2 27
117 # define NCG_Reserved_F1 f29
118 # define NCG_Reserved_F2 f30
120 #endif /* alpha_TARGET_ARCH */
122 /* -----------------------------------------------------------------------------
123 The HP-PA register mapping
125 We cater for HP-PA 1.1.
127 \tr{%r0}--\tr{%r1} are special.
128 \tr{%r2} is the return pointer.
129 \tr{%r3} is the frame pointer.
130 \tr{%r4}--\tr{%r18} are callee-save registers.
131 \tr{%r19} is a linkage table register for HPUX 8.0 shared libraries.
132 \tr{%r20}--\tr{%r22} are caller-save registers.
133 \tr{%r23}--\tr{%r26} are parameter registers.
134 \tr{%r27} is a global data pointer.
135 \tr{%r28}--\tr{%r29} are temporaries.
136 \tr{%r30} is the stack pointer.
137 \tr{%r31} is a temporary.
139 \tr{%fr12}--\tr{%fr15} are some callee-save floating-point registers.
140 \tr{%fr8}--\tr{%fr11} are some available caller-save fl-pt registers.
141 -------------------------------------------------------------------------- */
143 #if hppa1_1_TARGET_ARCH
145 #define REG(x) __asm__("%" #x)
161 #define REG_D1 fr20 /* L & R */
162 #define REG_D2 fr21 /* L & R */
170 #define NCG_Reserved_I1 r28
171 #define NCG_Reserved_I2 r29
172 #define NCG_Reserved_F1 fr8
173 #define NCG_Reserved_F2 fr8R
174 #define NCG_Reserved_D1 fr10
175 #define NCG_Reserved_D2 fr11
179 /* -----------------------------------------------------------------------------
180 The x86 register mapping
182 Ok, we've only got 6 general purpose registers, a frame pointer and a
183 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
184 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
185 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
194 Leaving SpLim, and HpLim out of the picture.
195 -------------------------------------------------------------------------- */
200 #define REG(x) __asm__("%" #x)
202 #ifndef not_doing_dynamic_linking
207 #if STOLEN_X86_REGS >= 3
211 #if STOLEN_X86_REGS >= 4
215 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
216 #define MAX_REAL_FLOAT_REG 0
217 #define MAX_REAL_DOUBLE_REG 0
218 #define MAX_REAL_LONG_REG 0
222 /* -----------------------------------------------------------------------------
223 The x86-64 register mapping
229 %rdx (seem to be used as arg regs on x86-64)
230 %rsi (seem to be used as arg regs on x86-64)
231 %rdi (seem to be used as arg regs on x86-64)
233 %rsp (unavailable - stack pointer)
242 --------------------------------------------------------------------------- */
244 #if x86_64_TARGET_ARCH
246 #define REG(x) __asm__("%" #x)
252 #define REG_SpLim r14
253 #define REG_HpLim r15
254 /* ToDo: try R2/R3 instead of SpLim/HpLim? */
256 #define MAX_REAL_VANILLA_REG 1
257 #define MAX_REAL_FLOAT_REG 0
258 #define MAX_REAL_DOUBLE_REG 0
259 #define MAX_REAL_LONG_REG 0
263 /* -----------------------------------------------------------------------------
264 The Motorola 680x0 register mapping
266 A Sun3 (mc680x0) has eight address registers, \tr{a0} to \tr{a7}, and
267 eight data registers, \tr{d0} to \tr{d7}. Address operations have to
268 be done through address registers; data registers are used for
269 comparison values and data.
271 Here's the register-usage picture for m68k boxes with GCC.
274 a0 & used directly by GCC \\
275 a1 & used directly by GCC \\
277 a2..a5 & callee-saved: available for STG registers \\
278 & (a5 may be special, ``global'' register for PIC?) \\
280 a6 & C-stack frame pointer \\
281 a7 & C-stack pointer \\
283 d0 & used directly by GCC \\
284 d1 & used directly by GCC \\
285 d2 & really needed for local optimisation by GCC \\
287 d3..d7 & callee-saved: available for STG registers
289 fp0 & call-clobbered \\
290 fp1 & call-clobbered \\
291 fp2..fp7 & callee-saved: available for STG registers
293 -------------------------------------------------------------------------- */
297 #define REG(x) __asm__(#x)
309 #define MAX_REAL_VANILLA_REG 2
323 /* -----------------------------------------------------------------------------
324 The DECstation (MIPS) register mapping
326 Here's at least some simple stuff about registers on a MIPS.
328 \tr{s0}--\tr{s7} are callee-save integer registers; they are our
329 ``prize'' stolen registers. There is also a wad of callee-save
330 floating-point registers, \tr{$f20}--\tr{$f31}; we'll use some of
333 \tr{t0}--\tr{t9} are caller-save (``temporary?'') integer registers.
334 We can steal some, but we might have to save/restore around ccalls.
335 -------------------------------------------------------------------------- */
337 #if mipsel_TARGET_ARCH || mipseb_TARGET_ARCH
339 #define REG(x) __asm__("$" #x)
341 #define CALLER_SAVES_R1
342 #define CALLER_SAVES_R2
343 #define CALLER_SAVES_R3
344 #define CALLER_SAVES_R4
345 #define CALLER_SAVES_R5
346 #define CALLER_SAVES_R6
347 #define CALLER_SAVES_R7
348 #define CALLER_SAVES_R8
350 #define CALLER_SAVES_USER
375 #endif /* mipse[lb] */
377 /* -----------------------------------------------------------------------------
378 The PowerPC register mapping
380 0 system glue? (caller-save, volatile)
381 1 SP (callee-save, non-volatile)
382 2 RTOC (callee-save, non-volatile)
383 3-10 args/return (caller-save, volatile)
384 11,12 system glue? (caller-save, volatile)
385 13-31 (callee-save, non-volatile)
387 f0 (caller-save, volatile)
388 f1-f13 args/return (caller-save, volatile)
389 f14-f31 (callee-save, non-volatile)
391 \tr{13}--\tr{31} are wonderful callee-save registers.
392 \tr{0}--\tr{12} are caller-save registers.
394 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
396 I think we can do the Whole Business with callee-save registers only!
397 -------------------------------------------------------------------------- */
399 #if powerpc_TARGET_ARCH || rs6000_TARGET_ARCH
401 #define REG(x) __asm__(#x)
421 #define REG_SpLim r24
424 #define REG_HpLim r26
426 #define NCG_SpillTmp_I1 r27
427 #define NCG_SpillTmp_I2 r28
429 #define NCG_SpillTmp_D1 f20
430 #define NCG_SpillTmp_D2 f21
434 /* -----------------------------------------------------------------------------
435 The IA64 register mapping
437 We place the general registers in the locals area of the register stack,
438 so that the call mechanism takes care of saving them for us. We reserve
439 the first 16 for gcc's use - since gcc uses the highest used register to
440 determine the register stack frame size, this gives us a constant size
441 register stack frame.
443 \tr{f16-f32} are the callee-saved floating point registers.
444 -------------------------------------------------------------------------- */
446 #ifdef ia64_TARGET_ARCH
448 #define REG(x) __asm__(#x)
468 #define REG_SpLim loc26
471 #define REG_HpLim loc28
475 /* -----------------------------------------------------------------------------
476 The Sun SPARC register mapping
478 The SPARC register (window) story: Remember, within the Haskell
479 Threaded World, we essentially ``shut down'' the register-window
480 mechanism---the window doesn't move at all while in this World. It
481 *does* move, of course, if we call out to arbitrary~C...
483 The %i, %l, and %o registers (8 each) are the input, local, and
484 output registers visible in one register window. The 8 %g (global)
485 registers are visible all the time.
487 %o0..%o7 not available; can be zapped by callee
488 (%o6 is C-stack ptr; %o7 hold ret addrs)
489 %i0..%i7 available (except %i6 is used as frame ptr)
490 (and %i7 tends to have ret-addr-ish things)
492 %g0..%g4 not available; prone to stomping by division, etc.
493 %g5..%g7 not available; reserved for the OS
495 Note: %g3 is *definitely* clobbered in the builtin divide code (and
496 our save/restore machinery is NOT GOOD ENOUGH for that); discretion
497 being the better part of valor, we also don't take %g4.
499 The paired nature of the floating point registers causes complications for
500 the native code generator. For convenience, we pretend that the first 22
501 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
502 float (single) regs. The NCG acts accordingly. That means that the
503 following FP assignment is rather fragile, and should only be changed
504 with extreme care. The current scheme is:
506 %f0 /%f1 FP return from C
509 %f6 /%f7 ncg double spill tmp #1
510 %f8 /%f9 ncg double spill tmp #2
511 %f10/%f11 allocatable
512 %f12/%f13 allocatable
513 %f14/%f15 allocatable
514 %f16/%f17 allocatable
515 %f18/%f19 allocatable
516 %f20/%f21 allocatable
522 %f26 ncg single spill tmp #1
523 %f27 ncg single spill tmp #2
529 -------------------------------------------------------------------------- */
531 #if sparc_TARGET_ARCH
533 #define REG(x) __asm__("%" #x)
535 #define CALLER_SAVES_USER
537 #define CALLER_SAVES_F1
538 #define CALLER_SAVES_F2
539 #define CALLER_SAVES_F3
540 #define CALLER_SAVES_F4
541 #define CALLER_SAVES_D1
542 #define CALLER_SAVES_D2
566 #define NCG_SpillTmp_I1 g1
567 #define NCG_SpillTmp_I2 g2
568 #define NCG_SpillTmp_F1 f26
569 #define NCG_SpillTmp_F2 f27
570 #define NCG_SpillTmp_D1 f6
571 #define NCG_SpillTmp_D2 f8
573 #define NCG_FirstFloatReg f22
579 /* -----------------------------------------------------------------------------
580 * These constants define how many stg registers will be used for
581 * passing arguments (and results, in the case of an unboxed-tuple
584 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
585 * highest STG register to occupy a real machine register, otherwise
586 * the calling conventions will needlessly shuffle data between the
587 * stack and memory-resident STG registers. We might occasionally
588 * set these macros to other values for testing, though.
590 * Registers above these values might still be used, for instance to
591 * communicate with PrimOps and RTS functions.
594 #ifndef MAX_REAL_VANILLA_REG
596 # define MAX_REAL_VANILLA_REG 8
597 # elif defined(REG_R7)
598 # define MAX_REAL_VANILLA_REG 7
599 # elif defined(REG_R6)
600 # define MAX_REAL_VANILLA_REG 6
601 # elif defined(REG_R5)
602 # define MAX_REAL_VANILLA_REG 5
603 # elif defined(REG_R4)
604 # define MAX_REAL_VANILLA_REG 4
605 # elif defined(REG_R3)
606 # define MAX_REAL_VANILLA_REG 3
607 # elif defined(REG_R2)
608 # define MAX_REAL_VANILLA_REG 2
609 # elif defined(REG_R1)
610 # define MAX_REAL_VANILLA_REG 1
612 # define MAX_REAL_VANILLA_REG 0
616 #ifndef MAX_REAL_FLOAT_REG
618 # define MAX_REAL_FLOAT_REG 4
619 # elif defined(REG_F3)
620 # define MAX_REAL_FLOAT_REG 3
621 # elif defined(REG_F2)
622 # define MAX_REAL_FLOAT_REG 2
623 # elif defined(REG_F1)
624 # define MAX_REAL_FLOAT_REG 1
626 # define MAX_REAL_FLOAT_REG 0
630 #ifndef MAX_REAL_DOUBLE_REG
632 # define MAX_REAL_DOUBLE_REG 2
633 # elif defined(REG_D1)
634 # define MAX_REAL_DOUBLE_REG 1
636 # define MAX_REAL_DOUBLE_REG 0
640 #ifndef MAX_REAL_LONG_REG
642 # define MAX_REAL_LONG_REG 1
644 # define MAX_REAL_LONG_REG 0
648 /* define NO_ARG_REGS if we have no argument registers at all (we can
649 * optimise certain code paths using this predicate).
651 #if MAX_REAL_VANILLA_REG < 2
657 #endif /* MACHREGS_H */