1 /* -----------------------------------------------------------------------------
2 * $Id: MachRegs.h,v 1.11 2002/06/07 09:40:10 matthewc Exp $
4 * (c) The GHC Team, 1998-1999
6 * Registers used in STG code. Might or might not correspond to
7 * actual machine registers.
9 * ---------------------------------------------------------------------------*/
14 /* This file is #included into Haskell code in the compiler: #defines
15 * only in here please.
18 /* define NO_REGS to omit register declarations - used in RTS C code
19 * that needs all the STG definitions but not the global register
24 /* ----------------------------------------------------------------------------
25 Caller saves and callee-saves regs.
27 Caller-saves regs have to be saved around C-calls made from STG
28 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
29 is designated caller-saves in that machine's C calling convention.
31 Additionally, the following macros should be defined when
33 CALLER_SAVES_USER one or more of R<n>, F, D
36 CALLER_SAVES_SYSTEM one or more of Sp, Su, SpLim, Hp, HpLim
39 This is so that the callWrapper mechanism knows which kind of
40 wrapper to generate for certain types of C call.
41 -------------------------------------------------------------------------- */
43 /* -----------------------------------------------------------------------------
44 The DEC Alpha register mapping
47 \tr{$9}--\tr{$14} are our ``prize'' callee-save registers.
48 \tr{$15} is the frame pointer, and \tr{$16}--\tr{$21} are argument
49 registers. (These are off-limits.) We can steal some of the \tr{$22}-and-up
50 caller-save registers provided we do the appropriate save/restore stuff.
52 \tr{$f2}--\tr{$f9} are some callee-save floating-point registers.
54 We cannot use \tr{$23} (aka t9), \tr{$24} (aka t10), \tr{$25} (aka
55 t11), \tr{$27} (aka pv), or \tr{$28} (aka at), because they are
56 occasionally required by the assembler to handle non-primitive
57 instructions (e.g. ldb, remq). Sigh!
78 -------------------------------------------------------------------------- */
80 #if defined(alpha_TARGET_ARCH)
81 # define REG(x) __asm__("$" #x)
83 # define CALLER_SAVES_R2
84 # define CALLER_SAVES_R3
85 # define CALLER_SAVES_R4
86 # define CALLER_SAVES_R5
87 # define CALLER_SAVES_R6
88 # define CALLER_SAVES_R7
89 # define CALLER_SAVES_R8
91 # define CALLER_SAVES_USER
112 # define REG_SpLim 11
115 # define REG_HpLim 13
117 # define NCG_Reserved_I1 22
118 # define NCG_Reserved_I2 27
119 # define NCG_Reserved_F1 f29
120 # define NCG_Reserved_F2 f30
122 #endif /* alpha_TARGET_ARCH */
124 /* -----------------------------------------------------------------------------
125 The HP-PA register mapping
127 We cater for HP-PA 1.1.
129 \tr{%r0}--\tr{%r1} are special.
130 \tr{%r2} is the return pointer.
131 \tr{%r3} is the frame pointer.
132 \tr{%r4}--\tr{%r18} are callee-save registers.
133 \tr{%r19} is a linkage table register for HPUX 8.0 shared libraries.
134 \tr{%r20}--\tr{%r22} are caller-save registers.
135 \tr{%r23}--\tr{%r26} are parameter registers.
136 \tr{%r27} is a global data pointer.
137 \tr{%r28}--\tr{%r29} are temporaries.
138 \tr{%r30} is the stack pointer.
139 \tr{%r31} is a temporary.
141 \tr{%fr12}--\tr{%fr15} are some callee-save floating-point registers.
142 \tr{%fr8}--\tr{%fr11} are some available caller-save fl-pt registers.
143 -------------------------------------------------------------------------- */
145 #if hppa1_1_TARGET_ARCH
147 #define REG(x) __asm__("%" #x)
163 #define REG_D1 fr20 /* L & R */
164 #define REG_D2 fr21 /* L & R */
173 #define NCG_Reserved_I1 r28
174 #define NCG_Reserved_I2 r29
175 #define NCG_Reserved_F1 fr8
176 #define NCG_Reserved_F2 fr8R
177 #define NCG_Reserved_D1 fr10
178 #define NCG_Reserved_D2 fr11
182 /* -----------------------------------------------------------------------------
183 The x86 register mapping
185 Ok, we've only got 6 general purpose registers, a frame pointer and a
186 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
187 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
188 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
197 Leaving Su, SpLim, and HpLim out of the picture.
198 -------------------------------------------------------------------------- */
203 #define REG(x) __asm__("%" #x)
205 #ifndef not_doing_dynamic_linking
209 /* #define REG_Su ebx*/
211 #if STOLEN_X86_REGS >= 3
215 #if STOLEN_X86_REGS >= 4
219 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
220 #define MAX_REAL_FLOAT_REG 0
221 #define MAX_REAL_DOUBLE_REG 0
222 #define MAX_REAL_LONG_REG 0
226 /* -----------------------------------------------------------------------------
227 The Motorola 680x0 register mapping
229 A Sun3 (mc680x0) has eight address registers, \tr{a0} to \tr{a7}, and
230 eight data registers, \tr{d0} to \tr{d7}. Address operations have to
231 be done through address registers; data registers are used for
232 comparison values and data.
234 Here's the register-usage picture for m68k boxes with GCC.
237 a0 & used directly by GCC \\
238 a1 & used directly by GCC \\
240 a2..a5 & callee-saved: available for STG registers \\
241 & (a5 may be special, ``global'' register for PIC?) \\
243 a6 & C-stack frame pointer \\
244 a7 & C-stack pointer \\
246 d0 & used directly by GCC \\
247 d1 & used directly by GCC \\
248 d2 & really needed for local optimisation by GCC \\
250 d3..d7 & callee-saved: available for STG registers
252 fp0 & call-clobbered \\
253 fp1 & call-clobbered \\
254 fp2..fp7 & callee-saved: available for STG registers
256 -------------------------------------------------------------------------- */
260 #define REG(x) __asm__(#x)
273 #define MAX_REAL_VANILLA_REG 2
287 /* -----------------------------------------------------------------------------
288 The DECstation (MIPS) register mapping
290 Here's at least some simple stuff about registers on a MIPS.
292 \tr{s0}--\tr{s7} are callee-save integer registers; they are our
293 ``prize'' stolen registers. There is also a wad of callee-save
294 floating-point registers, \tr{$f20}--\tr{$f31}; we'll use some of
297 \tr{t0}--\tr{t9} are caller-save (``temporary?'') integer registers.
298 We can steal some, but we might have to save/restore around ccalls.
299 -------------------------------------------------------------------------- */
301 #if mipsel_TARGET_ARCH || mipseb_TARGET_ARCH
303 #define REG(x) __asm__("$" #x)
305 #define CALLER_SAVES_R1
306 #define CALLER_SAVES_R2
307 #define CALLER_SAVES_R3
308 #define CALLER_SAVES_R4
309 #define CALLER_SAVES_R5
310 #define CALLER_SAVES_R6
311 #define CALLER_SAVES_R7
312 #define CALLER_SAVES_R8
314 #define CALLER_SAVES_USER
340 #endif /* mipse[lb] */
342 /* -----------------------------------------------------------------------------
343 The PowerPC register mapping
345 0 system glue? (caller-save, volatile)
346 1 SP (callee-save, non-volatile)
347 2 RTOC (callee-save, non-volatile)
348 3-10 args/return (caller-save, volatile)
349 11,12 system glue? (caller-save, volatile)
350 13-31 (callee-save, non-volatile)
352 f0 (caller-save, volatile)
353 f1-f13 args/return (caller-save, volatile)
354 f14-f31 (callee-save, non-volatile)
356 \tr{13}--\tr{31} are wonderful callee-save registers.
357 \tr{0}--\tr{12} are caller-save registers.
359 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
361 I think we can do the Whole Business with callee-save registers only!
362 -------------------------------------------------------------------------- */
364 #if powerpc_TARGET_ARCH || rs6000_TARGET_ARCH
366 #define REG(x) __asm__(#x)
387 #define REG_SpLim r24
390 #define REG_HpLim r26
394 /* -----------------------------------------------------------------------------
395 The IA64 register mapping
397 We place the general registers in the locals area of the register stack,
398 so that the call mechanism takes care of saving them for us. We reserve
399 the first 16 for gcc's use - since gcc uses the highest used register to
400 determine the register stack frame size, this gives us a constant size
401 register stack frame.
403 \tr{f16-f32} are the callee-saved floating point registers.
404 -------------------------------------------------------------------------- */
406 #ifdef ia64_TARGET_ARCH
408 #define REG(x) __asm__(#x)
429 #define REG_SpLim loc26
432 #define REG_HpLim loc28
436 /* -----------------------------------------------------------------------------
437 The Sun SPARC register mapping
439 The SPARC register (window) story: Remember, within the Haskell
440 Threaded World, we essentially ``shut down'' the register-window
441 mechanism---the window doesn't move at all while in this World. It
442 *does* move, of course, if we call out to arbitrary~C...
444 The %i, %l, and %o registers (8 each) are the input, local, and
445 output registers visible in one register window. The 8 %g (global)
446 registers are visible all the time.
448 %o0..%o7 not available; can be zapped by callee
449 (%o6 is C-stack ptr; %o7 hold ret addrs)
450 %i0..%i7 available (except %i6 is used as frame ptr)
451 (and %i7 tends to have ret-addr-ish things)
453 %g0..%g4 not available; prone to stomping by division, etc.
454 %g5..%g7 not available; reserved for the OS
456 Note: %g3 is *definitely* clobbered in the builtin divide code (and
457 our save/restore machinery is NOT GOOD ENOUGH for that); discretion
458 being the better part of valor, we also don't take %g4.
460 The paired nature of the floating point registers causes complications for
461 the native code generator. For convenience, we pretend that the first 22
462 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
463 float (single) regs. The NCG acts accordingly. That means that the
464 following FP assignment is rather fragile, and should only be changed
465 with extreme care. The current scheme is:
467 %f0 /%f1 FP return from C
470 %f6 /%f7 ncg double spill tmp #1
471 %f8 /%f9 ncg double spill tmp #2
472 %f10/%f11 allocatable
473 %f12/%f13 allocatable
474 %f14/%f15 allocatable
475 %f16/%f17 allocatable
476 %f18/%f19 allocatable
477 %f20/%f21 allocatable
483 %f26 ncg single spill tmp #1
484 %f27 ncg single spill tmp #2
490 -------------------------------------------------------------------------- */
492 #if sparc_TARGET_ARCH
494 #define REG(x) __asm__("%" #x)
496 #define CALLER_SAVES_USER
498 #define CALLER_SAVES_F1
499 #define CALLER_SAVES_F2
500 #define CALLER_SAVES_F3
501 #define CALLER_SAVES_F4
502 #define CALLER_SAVES_D1
503 #define CALLER_SAVES_D2
528 #define NCG_SpillTmp_I1 g1
529 #define NCG_SpillTmp_I2 g2
530 #define NCG_SpillTmp_F1 f26
531 #define NCG_SpillTmp_F2 f27
532 #define NCG_SpillTmp_D1 f6
533 #define NCG_SpillTmp_D2 f8
535 #define NCG_FirstFloatReg f22
539 /* These constants define how many stg registers are *actually* in
540 * registers: the code generator uses this information to avoid
541 * generating code to load/store registers which are really offsets
544 * Registers above these values might still be used, for instance to
545 * communicate with PrimOps and RTS functions.
548 #ifndef MAX_REAL_VANILLA_REG
549 #define MAX_REAL_VANILLA_REG 8
552 #ifndef MAX_REAL_FLOAT_REG
553 #define MAX_REAL_FLOAT_REG 4
556 #ifndef MAX_REAL_DOUBLE_REG
557 #define MAX_REAL_DOUBLE_REG 2
562 #endif /* MACHREGS_H */