1 /* -----------------------------------------------------------------------------
2 * $Id: MachRegs.h,v 1.22 2005/02/09 15:59:35 wolfgang Exp $
4 * (c) The GHC Team, 1998-1999
6 * Registers used in STG code. Might or might not correspond to
7 * actual machine registers.
9 * ---------------------------------------------------------------------------*/
14 /* This file is #included into Haskell code in the compiler: #defines
15 * only in here please.
19 * Defining NO_REGS causes no global registers to be used. NO_REGS is
20 * typically defined by GHC, via a command-line option passed to gcc,
21 * when the -funregisterised flag is given.
23 * NB. When NO_REGS is on, calling & return conventions may be
24 * different. For example, all function arguments will be passed on
25 * the stack, and components of an unboxed tuple will be returned on
26 * the stack rather than in registers.
30 /* NOTE: when testing the platform in this file we must test either
31 * *_HOST_ARCH and *_TARGET_ARCH, depending on whether COMPILING_GHC
32 * is set. This is because when we're compiling the RTS and HC code,
33 * the platform we're running on is the HOST, but when compiling GHC
34 * we want to know about the register mapping on the TARGET platform.
37 #define alpha_REGS alpha_TARGET_ARCH
38 #define hppa1_1_REGS hppa1_1_TARGET_ARCH
39 #define i386_REGS i386_TARGET_ARCH
40 #define x86_64_REGS x86_64_TARGET_ARCH
41 #define m68k_REGS m68k_TARGET_ARCH
42 #define mips_REGS (mipsel_TARGET_ARCH || mipseb_TARGET_ARCH)
43 #define powerpc_REGS (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH)
44 #define ia64_REGS ia64_TARGET_ARCH
45 #define sparc_REGS sparc_TARGET_ARCH
46 #define darwin_REGS darwin_TARGET_OS
48 #define alpha_REGS alpha_HOST_ARCH
49 #define hppa1_1_REGS hppa1_1_HOST_ARCH
50 #define i386_REGS i386_HOST_ARCH
51 #define x86_64_REGS x86_64_HOST_ARCH
52 #define m68k_REGS m68k_HOST_ARCH
53 #define mips_REGS (mipsel_HOST_ARCH || mipseb_HOST_ARCH)
54 #define powerpc_REGS (powerpc_HOST_ARCH || powerpc64_HOST_ARCH || rs6000_HOST_ARCH)
55 #define ia64_REGS ia64_HOST_ARCH
56 #define sparc_REGS sparc_HOST_ARCH
57 #define darwin_REGS darwin_HOST_OS
60 /* ----------------------------------------------------------------------------
61 Caller saves and callee-saves regs.
63 Caller-saves regs have to be saved around C-calls made from STG
64 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
65 is designated caller-saves in that machine's C calling convention.
67 Additionally, the following macros should be defined when
69 CALLER_SAVES_USER one or more of R<n>, F, D
72 CALLER_SAVES_SYSTEM one or more of Sp, SpLim, Hp, HpLim
75 This is so that the callWrapper mechanism knows which kind of
76 wrapper to generate for certain types of C call.
77 -------------------------------------------------------------------------- */
79 /* -----------------------------------------------------------------------------
80 The DEC Alpha register mapping
83 \tr{$9}--\tr{$14} are our ``prize'' callee-save registers.
84 \tr{$15} is the frame pointer, and \tr{$16}--\tr{$21} are argument
85 registers. (These are off-limits.) We can steal some of the \tr{$22}-and-up
86 caller-save registers provided we do the appropriate save/restore stuff.
88 \tr{$f2}--\tr{$f9} are some callee-save floating-point registers.
90 We cannot use \tr{$23} (aka t9), \tr{$24} (aka t10), \tr{$25} (aka
91 t11), \tr{$27} (aka pv), or \tr{$28} (aka at), because they are
92 occasionally required by the assembler to handle non-primitive
93 instructions (e.g. ldb, remq). Sigh!
113 -------------------------------------------------------------------------- */
116 # define REG(x) __asm__("$" #x)
118 # define CALLER_SAVES_R2
119 # define CALLER_SAVES_R3
120 # define CALLER_SAVES_R4
121 # define CALLER_SAVES_R5
122 # define CALLER_SAVES_R6
123 # define CALLER_SAVES_R7
124 # define CALLER_SAVES_R8
126 # define CALLER_SAVES_USER
146 # define REG_SpLim 11
149 # define REG_HpLim 13
151 # define NCG_Reserved_I1 22
152 # define NCG_Reserved_I2 27
153 # define NCG_Reserved_F1 f29
154 # define NCG_Reserved_F2 f30
156 #endif /* alpha_REGS */
158 /* -----------------------------------------------------------------------------
159 The HP-PA register mapping
161 We cater for HP-PA 1.1.
163 \tr{%r0}--\tr{%r1} are special.
164 \tr{%r2} is the return pointer.
165 \tr{%r3} is the frame pointer.
166 \tr{%r4}--\tr{%r18} are callee-save registers.
167 \tr{%r19} is a linkage table register for HPUX 8.0 shared libraries.
168 \tr{%r20}--\tr{%r22} are caller-save registers.
169 \tr{%r23}--\tr{%r26} are parameter registers.
170 \tr{%r27} is a global data pointer.
171 \tr{%r28}--\tr{%r29} are temporaries.
172 \tr{%r30} is the stack pointer.
173 \tr{%r31} is a temporary.
175 \tr{%fr12}--\tr{%fr15} are some callee-save floating-point registers.
176 \tr{%fr8}--\tr{%fr11} are some available caller-save fl-pt registers.
177 -------------------------------------------------------------------------- */
181 #define REG(x) __asm__("%" #x)
197 #define REG_D1 fr20 /* L & R */
198 #define REG_D2 fr21 /* L & R */
206 #define NCG_Reserved_I1 r28
207 #define NCG_Reserved_I2 r29
208 #define NCG_Reserved_F1 fr8
209 #define NCG_Reserved_F2 fr8R
210 #define NCG_Reserved_D1 fr10
211 #define NCG_Reserved_D2 fr11
215 /* -----------------------------------------------------------------------------
216 The x86 register mapping
218 Ok, we've only got 6 general purpose registers, a frame pointer and a
219 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
220 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
221 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
230 Leaving SpLim, and HpLim out of the picture.
231 -------------------------------------------------------------------------- */
236 #define REG(x) __asm__("%" #x)
238 #ifndef not_doing_dynamic_linking
243 #ifndef STOLEN_X86_REGS
244 #define STOLEN_X86_REGS 4
247 #if STOLEN_X86_REGS >= 3
251 #if STOLEN_X86_REGS >= 4
255 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
256 #define MAX_REAL_FLOAT_REG 0
257 #define MAX_REAL_DOUBLE_REG 0
258 #define MAX_REAL_LONG_REG 0
262 /* -----------------------------------------------------------------------------
263 The x86-64 register mapping
269 %rdx (seem to be used as arg regs on x86-64)
270 %rsi (seem to be used as arg regs on x86-64)
271 %rdi (seem to be used as arg regs on x86-64)
273 %rsp (unavailable - stack pointer)
282 --------------------------------------------------------------------------- */
286 #define REG(x) __asm__("%" #x)
292 #define REG_SpLim r14
293 #define REG_HpLim r15
294 /* ToDo: try R2/R3 instead of SpLim/HpLim? */
296 #define MAX_REAL_VANILLA_REG 1
297 #define MAX_REAL_FLOAT_REG 0
298 #define MAX_REAL_DOUBLE_REG 0
299 #define MAX_REAL_LONG_REG 0
303 /* -----------------------------------------------------------------------------
304 The Motorola 680x0 register mapping
306 A Sun3 (mc680x0) has eight address registers, \tr{a0} to \tr{a7}, and
307 eight data registers, \tr{d0} to \tr{d7}. Address operations have to
308 be done through address registers; data registers are used for
309 comparison values and data.
311 Here's the register-usage picture for m68k boxes with GCC.
314 a0 & used directly by GCC \\
315 a1 & used directly by GCC \\
317 a2..a5 & callee-saved: available for STG registers \\
318 & (a5 may be special, ``global'' register for PIC?) \\
320 a6 & C-stack frame pointer \\
321 a7 & C-stack pointer \\
323 d0 & used directly by GCC \\
324 d1 & used directly by GCC \\
325 d2 & really needed for local optimisation by GCC \\
327 d3..d7 & callee-saved: available for STG registers
329 fp0 & call-clobbered \\
330 fp1 & call-clobbered \\
331 fp2..fp7 & callee-saved: available for STG registers
333 -------------------------------------------------------------------------- */
337 #define REG(x) __asm__(#x)
349 #define MAX_REAL_VANILLA_REG 2
363 /* -----------------------------------------------------------------------------
364 The DECstation (MIPS) register mapping
366 Here's at least some simple stuff about registers on a MIPS.
368 \tr{s0}--\tr{s7} are callee-save integer registers; they are our
369 ``prize'' stolen registers. There is also a wad of callee-save
370 floating-point registers, \tr{$f20}--\tr{$f31}; we'll use some of
373 \tr{t0}--\tr{t9} are caller-save (``temporary?'') integer registers.
374 We can steal some, but we might have to save/restore around ccalls.
375 -------------------------------------------------------------------------- */
379 #define REG(x) __asm__("$" #x)
381 #define CALLER_SAVES_R1
382 #define CALLER_SAVES_R2
383 #define CALLER_SAVES_R3
384 #define CALLER_SAVES_R4
385 #define CALLER_SAVES_R5
386 #define CALLER_SAVES_R6
387 #define CALLER_SAVES_R7
388 #define CALLER_SAVES_R8
390 #define CALLER_SAVES_USER
415 #endif /* mipse[lb] */
417 /* -----------------------------------------------------------------------------
418 The PowerPC register mapping
420 0 system glue? (caller-save, volatile)
421 1 SP (callee-save, non-volatile)
422 2 AIX, powerpc64-linux:
423 RTOC (a strange special case)
425 (caller-save, volatile)
427 reserved for use by system
429 3-10 args/return (caller-save, volatile)
430 11,12 system glue? (caller-save, volatile)
431 13 on 64-bit: reserved for thread state pointer
432 on 32-bit: (callee-save, non-volatile)
433 14-31 (callee-save, non-volatile)
435 f0 (caller-save, volatile)
436 f1-f13 args/return (caller-save, volatile)
437 f14-f31 (callee-save, non-volatile)
439 \tr{14}--\tr{31} are wonderful callee-save registers on all ppc OSes.
440 \tr{0}--\tr{12} are caller-save registers.
442 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
444 We can do the Whole Business with callee-save registers only!
445 -------------------------------------------------------------------------- */
449 #define REG(x) __asm__(#x)
483 #define REG_SpLim r24
486 #define REG_HpLim r26
492 /* -----------------------------------------------------------------------------
493 The IA64 register mapping
495 We place the general registers in the locals area of the register stack,
496 so that the call mechanism takes care of saving them for us. We reserve
497 the first 16 for gcc's use - since gcc uses the highest used register to
498 determine the register stack frame size, this gives us a constant size
499 register stack frame.
501 \tr{f16-f32} are the callee-saved floating point registers.
502 -------------------------------------------------------------------------- */
506 #define REG(x) __asm__(#x)
526 #define REG_SpLim loc26
529 #define REG_HpLim loc28
533 /* -----------------------------------------------------------------------------
534 The Sun SPARC register mapping
536 The SPARC register (window) story: Remember, within the Haskell
537 Threaded World, we essentially ``shut down'' the register-window
538 mechanism---the window doesn't move at all while in this World. It
539 *does* move, of course, if we call out to arbitrary~C...
541 The %i, %l, and %o registers (8 each) are the input, local, and
542 output registers visible in one register window. The 8 %g (global)
543 registers are visible all the time.
545 %o0..%o7 not available; can be zapped by callee
546 (%o6 is C-stack ptr; %o7 hold ret addrs)
547 %i0..%i7 available (except %i6 is used as frame ptr)
548 (and %i7 tends to have ret-addr-ish things)
550 %g0..%g4 not available; prone to stomping by division, etc.
551 %g5..%g7 not available; reserved for the OS
553 Note: %g3 is *definitely* clobbered in the builtin divide code (and
554 our save/restore machinery is NOT GOOD ENOUGH for that); discretion
555 being the better part of valor, we also don't take %g4.
557 The paired nature of the floating point registers causes complications for
558 the native code generator. For convenience, we pretend that the first 22
559 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
560 float (single) regs. The NCG acts accordingly. That means that the
561 following FP assignment is rather fragile, and should only be changed
562 with extreme care. The current scheme is:
564 %f0 /%f1 FP return from C
567 %f6 /%f7 ncg double spill tmp #1
568 %f8 /%f9 ncg double spill tmp #2
569 %f10/%f11 allocatable
570 %f12/%f13 allocatable
571 %f14/%f15 allocatable
572 %f16/%f17 allocatable
573 %f18/%f19 allocatable
574 %f20/%f21 allocatable
580 %f26 ncg single spill tmp #1
581 %f27 ncg single spill tmp #2
587 -------------------------------------------------------------------------- */
591 #define REG(x) __asm__("%" #x)
593 #define CALLER_SAVES_USER
595 #define CALLER_SAVES_F1
596 #define CALLER_SAVES_F2
597 #define CALLER_SAVES_F3
598 #define CALLER_SAVES_F4
599 #define CALLER_SAVES_D1
600 #define CALLER_SAVES_D2
624 #define NCG_SpillTmp_I1 g1
625 #define NCG_SpillTmp_I2 g2
626 #define NCG_SpillTmp_F1 f26
627 #define NCG_SpillTmp_F2 f27
628 #define NCG_SpillTmp_D1 f6
629 #define NCG_SpillTmp_D2 f8
631 #define NCG_FirstFloatReg f22
637 /* -----------------------------------------------------------------------------
638 * These constants define how many stg registers will be used for
639 * passing arguments (and results, in the case of an unboxed-tuple
642 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
643 * highest STG register to occupy a real machine register, otherwise
644 * the calling conventions will needlessly shuffle data between the
645 * stack and memory-resident STG registers. We might occasionally
646 * set these macros to other values for testing, though.
648 * Registers above these values might still be used, for instance to
649 * communicate with PrimOps and RTS functions.
652 #ifndef MAX_REAL_VANILLA_REG
654 # define MAX_REAL_VANILLA_REG 8
655 # elif defined(REG_R7)
656 # define MAX_REAL_VANILLA_REG 7
657 # elif defined(REG_R6)
658 # define MAX_REAL_VANILLA_REG 6
659 # elif defined(REG_R5)
660 # define MAX_REAL_VANILLA_REG 5
661 # elif defined(REG_R4)
662 # define MAX_REAL_VANILLA_REG 4
663 # elif defined(REG_R3)
664 # define MAX_REAL_VANILLA_REG 3
665 # elif defined(REG_R2)
666 # define MAX_REAL_VANILLA_REG 2
667 # elif defined(REG_R1)
668 # define MAX_REAL_VANILLA_REG 1
670 # define MAX_REAL_VANILLA_REG 0
674 #ifndef MAX_REAL_FLOAT_REG
676 # define MAX_REAL_FLOAT_REG 4
677 # elif defined(REG_F3)
678 # define MAX_REAL_FLOAT_REG 3
679 # elif defined(REG_F2)
680 # define MAX_REAL_FLOAT_REG 2
681 # elif defined(REG_F1)
682 # define MAX_REAL_FLOAT_REG 1
684 # define MAX_REAL_FLOAT_REG 0
688 #ifndef MAX_REAL_DOUBLE_REG
690 # define MAX_REAL_DOUBLE_REG 2
691 # elif defined(REG_D1)
692 # define MAX_REAL_DOUBLE_REG 1
694 # define MAX_REAL_DOUBLE_REG 0
698 #ifndef MAX_REAL_LONG_REG
700 # define MAX_REAL_LONG_REG 1
702 # define MAX_REAL_LONG_REG 0
706 /* define NO_ARG_REGS if we have no argument registers at all (we can
707 * optimise certain code paths using this predicate).
709 #if MAX_REAL_VANILLA_REG < 2
715 #endif /* MACHREGS_H */