1 /* -----------------------------------------------------------------------------
3 * (c) The GHC Team, 1998-1999
5 * Registers used in STG code. Might or might not correspond to
6 * actual machine registers.
8 * ---------------------------------------------------------------------------*/
13 /* This file is #included into Haskell code in the compiler: #defines
14 * only in here please.
18 * Defining NO_REGS causes no global registers to be used. NO_REGS is
19 * typically defined by GHC, via a command-line option passed to gcc,
20 * when the -funregisterised flag is given.
22 * NB. When NO_REGS is on, calling & return conventions may be
23 * different. For example, all function arguments will be passed on
24 * the stack, and components of an unboxed tuple will be returned on
25 * the stack rather than in registers.
29 /* NOTE: when testing the platform in this file we must test either
30 * *_HOST_ARCH and *_TARGET_ARCH, depending on whether COMPILING_GHC
31 * is set. This is because when we're compiling the RTS and HC code,
32 * the platform we're running on is the HOST, but when compiling GHC
33 * we want to know about the register mapping on the TARGET platform.
36 #define alpha_REGS alpha_TARGET_ARCH
37 #define hppa1_1_REGS hppa1_1_TARGET_ARCH
38 #define i386_REGS i386_TARGET_ARCH
39 #define x86_64_REGS x86_64_TARGET_ARCH
40 #define m68k_REGS m68k_TARGET_ARCH
41 #define mips_REGS (mipsel_TARGET_ARCH || mipseb_TARGET_ARCH)
42 #define powerpc_REGS (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH)
43 #define ia64_REGS ia64_TARGET_ARCH
44 #define sparc_REGS sparc_TARGET_ARCH
45 #define darwin_REGS darwin_TARGET_OS
47 #define alpha_REGS alpha_HOST_ARCH
48 #define hppa1_1_REGS hppa1_1_HOST_ARCH
49 #define i386_REGS i386_HOST_ARCH
50 #define x86_64_REGS x86_64_HOST_ARCH
51 #define m68k_REGS m68k_HOST_ARCH
52 #define mips_REGS (mipsel_HOST_ARCH || mipseb_HOST_ARCH)
53 #define powerpc_REGS (powerpc_HOST_ARCH || powerpc64_HOST_ARCH || rs6000_HOST_ARCH)
54 #define ia64_REGS ia64_HOST_ARCH
55 #define sparc_REGS sparc_HOST_ARCH
56 #define darwin_REGS darwin_HOST_OS
59 /* ----------------------------------------------------------------------------
60 Caller saves and callee-saves regs.
62 Caller-saves regs have to be saved around C-calls made from STG
63 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
64 is designated caller-saves in that machine's C calling convention.
66 Additionally, the following macros should be defined when
68 CALLER_SAVES_USER one or more of R<n>, F, D
71 CALLER_SAVES_SYSTEM one or more of Sp, SpLim, Hp, HpLim
74 This is so that the callWrapper mechanism knows which kind of
75 wrapper to generate for certain types of C call.
76 -------------------------------------------------------------------------- */
78 /* -----------------------------------------------------------------------------
79 The DEC Alpha register mapping
82 \tr{$9}--\tr{$14} are our ``prize'' callee-save registers.
83 \tr{$15} is the frame pointer, and \tr{$16}--\tr{$21} are argument
84 registers. (These are off-limits.) We can steal some of the \tr{$22}-and-up
85 caller-save registers provided we do the appropriate save/restore stuff.
87 \tr{$f2}--\tr{$f9} are some callee-save floating-point registers.
89 We cannot use \tr{$23} (aka t9), \tr{$24} (aka t10), \tr{$25} (aka
90 t11), \tr{$27} (aka pv), or \tr{$28} (aka at), because they are
91 occasionally required by the assembler to handle non-primitive
92 instructions (e.g. ldb, remq). Sigh!
112 -------------------------------------------------------------------------- */
115 # define REG(x) __asm__("$" #x)
117 # define CALLER_SAVES_R2
118 # define CALLER_SAVES_R3
119 # define CALLER_SAVES_R4
120 # define CALLER_SAVES_R5
121 # define CALLER_SAVES_R6
122 # define CALLER_SAVES_R7
123 # define CALLER_SAVES_R8
125 # define CALLER_SAVES_USER
145 # define REG_SpLim 11
148 # define REG_HpLim 13
150 # define NCG_Reserved_I1 22
151 # define NCG_Reserved_I2 27
152 # define NCG_Reserved_F1 f29
153 # define NCG_Reserved_F2 f30
155 #endif /* alpha_REGS */
157 /* -----------------------------------------------------------------------------
158 The HP-PA register mapping
160 We cater for HP-PA 1.1.
162 \tr{%r0}--\tr{%r1} are special.
163 \tr{%r2} is the return pointer.
164 \tr{%r3} is the frame pointer.
165 \tr{%r4}--\tr{%r18} are callee-save registers.
166 \tr{%r19} is a linkage table register for HPUX 8.0 shared libraries.
167 \tr{%r20}--\tr{%r22} are caller-save registers.
168 \tr{%r23}--\tr{%r26} are parameter registers.
169 \tr{%r27} is a global data pointer.
170 \tr{%r28}--\tr{%r29} are temporaries.
171 \tr{%r30} is the stack pointer.
172 \tr{%r31} is a temporary.
174 \tr{%fr12}--\tr{%fr15} are some callee-save floating-point registers.
175 \tr{%fr8}--\tr{%fr11} are some available caller-save fl-pt registers.
176 -------------------------------------------------------------------------- */
180 #define REG(x) __asm__("%" #x)
196 #define REG_D1 fr20 /* L & R */
197 #define REG_D2 fr21 /* L & R */
205 #define NCG_Reserved_I1 r28
206 #define NCG_Reserved_I2 r29
207 #define NCG_Reserved_F1 fr8
208 #define NCG_Reserved_F2 fr8R
209 #define NCG_Reserved_D1 fr10
210 #define NCG_Reserved_D2 fr11
214 /* -----------------------------------------------------------------------------
215 The x86 register mapping
217 Ok, we've only got 6 general purpose registers, a frame pointer and a
218 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
219 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
220 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
229 Leaving SpLim, and HpLim out of the picture.
230 -------------------------------------------------------------------------- */
235 #define REG(x) __asm__("%" #x)
237 #ifndef not_doing_dynamic_linking
242 #ifndef STOLEN_X86_REGS
243 #define STOLEN_X86_REGS 4
246 #if STOLEN_X86_REGS >= 3
250 #if STOLEN_X86_REGS >= 4
254 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
255 #define MAX_REAL_FLOAT_REG 0
256 #define MAX_REAL_DOUBLE_REG 0
257 #define MAX_REAL_LONG_REG 0
261 /* -----------------------------------------------------------------------------
262 The x86-64 register mapping
267 %rcx arg reg, caller-saves
268 %rdx arg reg, caller-saves
269 %rsi arg reg, caller-saves
270 %rdi arg reg, caller-saves
271 %rbp YES (our *prime* register)
272 %rsp (unavailable - stack pointer)
273 %r8 arg reg, caller-saves
274 %r9 arg reg, caller-saves
282 %xmm0-7 arg regs, caller-saves
283 %xmm8-15 caller-saves
285 A better reg mapping might be:
298 Use the caller-saves regs for Rn, because we don't always have to
299 save those (as opposed to Sp/Hp/SpLim etc. which always have to be
302 --------------------------------------------------------------------------- */
306 #define REG(x) __asm__("%" #x)
312 #define REG_SpLim r14
313 #define REG_HpLim r15
314 /* ToDo: try R2/R3 instead of SpLim/HpLim? */
316 #define MAX_REAL_VANILLA_REG 1
317 #define MAX_REAL_FLOAT_REG 0
318 #define MAX_REAL_DOUBLE_REG 0
319 #define MAX_REAL_LONG_REG 0
323 /* -----------------------------------------------------------------------------
324 The Motorola 680x0 register mapping
326 A Sun3 (mc680x0) has eight address registers, \tr{a0} to \tr{a7}, and
327 eight data registers, \tr{d0} to \tr{d7}. Address operations have to
328 be done through address registers; data registers are used for
329 comparison values and data.
331 Here's the register-usage picture for m68k boxes with GCC.
334 a0 & used directly by GCC \\
335 a1 & used directly by GCC \\
337 a2..a5 & callee-saved: available for STG registers \\
338 & (a5 may be special, ``global'' register for PIC?) \\
340 a6 & C-stack frame pointer \\
341 a7 & C-stack pointer \\
343 d0 & used directly by GCC \\
344 d1 & used directly by GCC \\
345 d2 & really needed for local optimisation by GCC \\
347 d3..d7 & callee-saved: available for STG registers
349 fp0 & call-clobbered \\
350 fp1 & call-clobbered \\
351 fp2..fp7 & callee-saved: available for STG registers
353 -------------------------------------------------------------------------- */
357 #define REG(x) __asm__(#x)
369 #define MAX_REAL_VANILLA_REG 2
383 /* -----------------------------------------------------------------------------
384 The DECstation (MIPS) register mapping
386 Here's at least some simple stuff about registers on a MIPS.
388 \tr{s0}--\tr{s7} are callee-save integer registers; they are our
389 ``prize'' stolen registers. There is also a wad of callee-save
390 floating-point registers, \tr{$f20}--\tr{$f31}; we'll use some of
393 \tr{t0}--\tr{t9} are caller-save (``temporary?'') integer registers.
394 We can steal some, but we might have to save/restore around ccalls.
395 -------------------------------------------------------------------------- */
399 #define REG(x) __asm__("$" #x)
401 #define CALLER_SAVES_R1
402 #define CALLER_SAVES_R2
403 #define CALLER_SAVES_R3
404 #define CALLER_SAVES_R4
405 #define CALLER_SAVES_R5
406 #define CALLER_SAVES_R6
407 #define CALLER_SAVES_R7
408 #define CALLER_SAVES_R8
410 #define CALLER_SAVES_USER
435 #endif /* mipse[lb] */
437 /* -----------------------------------------------------------------------------
438 The PowerPC register mapping
440 0 system glue? (caller-save, volatile)
441 1 SP (callee-save, non-volatile)
442 2 AIX, powerpc64-linux:
443 RTOC (a strange special case)
445 (caller-save, volatile)
447 reserved for use by system
449 3-10 args/return (caller-save, volatile)
450 11,12 system glue? (caller-save, volatile)
451 13 on 64-bit: reserved for thread state pointer
452 on 32-bit: (callee-save, non-volatile)
453 14-31 (callee-save, non-volatile)
455 f0 (caller-save, volatile)
456 f1-f13 args/return (caller-save, volatile)
457 f14-f31 (callee-save, non-volatile)
459 \tr{14}--\tr{31} are wonderful callee-save registers on all ppc OSes.
460 \tr{0}--\tr{12} are caller-save registers.
462 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
464 We can do the Whole Business with callee-save registers only!
465 -------------------------------------------------------------------------- */
469 #define REG(x) __asm__(#x)
503 #define REG_SpLim r24
506 #define REG_HpLim r26
512 /* -----------------------------------------------------------------------------
513 The IA64 register mapping
515 We place the general registers in the locals area of the register stack,
516 so that the call mechanism takes care of saving them for us. We reserve
517 the first 16 for gcc's use - since gcc uses the highest used register to
518 determine the register stack frame size, this gives us a constant size
519 register stack frame.
521 \tr{f16-f32} are the callee-saved floating point registers.
522 -------------------------------------------------------------------------- */
526 #define REG(x) __asm__(#x)
546 #define REG_SpLim loc26
549 #define REG_HpLim loc28
553 /* -----------------------------------------------------------------------------
554 The Sun SPARC register mapping
556 The SPARC register (window) story: Remember, within the Haskell
557 Threaded World, we essentially ``shut down'' the register-window
558 mechanism---the window doesn't move at all while in this World. It
559 *does* move, of course, if we call out to arbitrary~C...
561 The %i, %l, and %o registers (8 each) are the input, local, and
562 output registers visible in one register window. The 8 %g (global)
563 registers are visible all the time.
565 %o0..%o7 not available; can be zapped by callee
566 (%o6 is C-stack ptr; %o7 hold ret addrs)
567 %i0..%i7 available (except %i6 is used as frame ptr)
568 (and %i7 tends to have ret-addr-ish things)
570 %g0..%g4 not available; prone to stomping by division, etc.
571 %g5..%g7 not available; reserved for the OS
573 Note: %g3 is *definitely* clobbered in the builtin divide code (and
574 our save/restore machinery is NOT GOOD ENOUGH for that); discretion
575 being the better part of valor, we also don't take %g4.
577 The paired nature of the floating point registers causes complications for
578 the native code generator. For convenience, we pretend that the first 22
579 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
580 float (single) regs. The NCG acts accordingly. That means that the
581 following FP assignment is rather fragile, and should only be changed
582 with extreme care. The current scheme is:
584 %f0 /%f1 FP return from C
587 %f6 /%f7 ncg double spill tmp #1
588 %f8 /%f9 ncg double spill tmp #2
589 %f10/%f11 allocatable
590 %f12/%f13 allocatable
591 %f14/%f15 allocatable
592 %f16/%f17 allocatable
593 %f18/%f19 allocatable
594 %f20/%f21 allocatable
600 %f26 ncg single spill tmp #1
601 %f27 ncg single spill tmp #2
607 -------------------------------------------------------------------------- */
611 #define REG(x) __asm__("%" #x)
613 #define CALLER_SAVES_USER
615 #define CALLER_SAVES_F1
616 #define CALLER_SAVES_F2
617 #define CALLER_SAVES_F3
618 #define CALLER_SAVES_F4
619 #define CALLER_SAVES_D1
620 #define CALLER_SAVES_D2
642 #define NCG_SpillTmp_I1 g1
643 #define NCG_SpillTmp_I2 g2
644 #define NCG_SpillTmp_F1 f26
645 #define NCG_SpillTmp_F2 f27
646 #define NCG_SpillTmp_D1 f6
647 #define NCG_SpillTmp_D2 f8
649 #define NCG_FirstFloatReg f22
655 /* -----------------------------------------------------------------------------
656 * These constants define how many stg registers will be used for
657 * passing arguments (and results, in the case of an unboxed-tuple
660 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
661 * highest STG register to occupy a real machine register, otherwise
662 * the calling conventions will needlessly shuffle data between the
663 * stack and memory-resident STG registers. We might occasionally
664 * set these macros to other values for testing, though.
666 * Registers above these values might still be used, for instance to
667 * communicate with PrimOps and RTS functions.
670 #ifndef MAX_REAL_VANILLA_REG
672 # define MAX_REAL_VANILLA_REG 8
673 # elif defined(REG_R7)
674 # define MAX_REAL_VANILLA_REG 7
675 # elif defined(REG_R6)
676 # define MAX_REAL_VANILLA_REG 6
677 # elif defined(REG_R5)
678 # define MAX_REAL_VANILLA_REG 5
679 # elif defined(REG_R4)
680 # define MAX_REAL_VANILLA_REG 4
681 # elif defined(REG_R3)
682 # define MAX_REAL_VANILLA_REG 3
683 # elif defined(REG_R2)
684 # define MAX_REAL_VANILLA_REG 2
685 # elif defined(REG_R1)
686 # define MAX_REAL_VANILLA_REG 1
688 # define MAX_REAL_VANILLA_REG 0
692 #ifndef MAX_REAL_FLOAT_REG
694 # define MAX_REAL_FLOAT_REG 4
695 # elif defined(REG_F3)
696 # define MAX_REAL_FLOAT_REG 3
697 # elif defined(REG_F2)
698 # define MAX_REAL_FLOAT_REG 2
699 # elif defined(REG_F1)
700 # define MAX_REAL_FLOAT_REG 1
702 # define MAX_REAL_FLOAT_REG 0
706 #ifndef MAX_REAL_DOUBLE_REG
708 # define MAX_REAL_DOUBLE_REG 2
709 # elif defined(REG_D1)
710 # define MAX_REAL_DOUBLE_REG 1
712 # define MAX_REAL_DOUBLE_REG 0
716 #ifndef MAX_REAL_LONG_REG
718 # define MAX_REAL_LONG_REG 1
720 # define MAX_REAL_LONG_REG 0
724 /* define NO_ARG_REGS if we have no argument registers at all (we can
725 * optimise certain code paths using this predicate).
727 #if MAX_REAL_VANILLA_REG < 2
733 #endif /* MACHREGS_H */