1 /* -----------------------------------------------------------------------------
2 * $Id: MachRegs.h,v 1.19 2005/01/13 16:21:14 simonmar Exp $
4 * (c) The GHC Team, 1998-1999
6 * Registers used in STG code. Might or might not correspond to
7 * actual machine registers.
9 * ---------------------------------------------------------------------------*/
14 /* This file is #included into Haskell code in the compiler: #defines
15 * only in here please.
19 * Defining NO_REGS causes no global registers to be used. NO_REGS is
20 * typically defined by GHC, via a command-line option passed to gcc,
21 * when the -funregisterised flag is given.
23 * NB. When NO_REGS is on, calling & return conventions may be
24 * different. For example, all function arguments will be passed on
25 * the stack, and components of an unboxed tuple will be returned on
26 * the stack rather than in registers.
30 /* ----------------------------------------------------------------------------
31 Caller saves and callee-saves regs.
33 Caller-saves regs have to be saved around C-calls made from STG
34 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
35 is designated caller-saves in that machine's C calling convention.
37 Additionally, the following macros should be defined when
39 CALLER_SAVES_USER one or more of R<n>, F, D
42 CALLER_SAVES_SYSTEM one or more of Sp, SpLim, Hp, HpLim
45 This is so that the callWrapper mechanism knows which kind of
46 wrapper to generate for certain types of C call.
47 -------------------------------------------------------------------------- */
49 /* -----------------------------------------------------------------------------
50 The DEC Alpha register mapping
53 \tr{$9}--\tr{$14} are our ``prize'' callee-save registers.
54 \tr{$15} is the frame pointer, and \tr{$16}--\tr{$21} are argument
55 registers. (These are off-limits.) We can steal some of the \tr{$22}-and-up
56 caller-save registers provided we do the appropriate save/restore stuff.
58 \tr{$f2}--\tr{$f9} are some callee-save floating-point registers.
60 We cannot use \tr{$23} (aka t9), \tr{$24} (aka t10), \tr{$25} (aka
61 t11), \tr{$27} (aka pv), or \tr{$28} (aka at), because they are
62 occasionally required by the assembler to handle non-primitive
63 instructions (e.g. ldb, remq). Sigh!
83 -------------------------------------------------------------------------- */
85 #if defined(alpha_TARGET_ARCH)
86 # define REG(x) __asm__("$" #x)
88 # define CALLER_SAVES_R2
89 # define CALLER_SAVES_R3
90 # define CALLER_SAVES_R4
91 # define CALLER_SAVES_R5
92 # define CALLER_SAVES_R6
93 # define CALLER_SAVES_R7
94 # define CALLER_SAVES_R8
96 # define CALLER_SAVES_USER
116 # define REG_SpLim 11
119 # define REG_HpLim 13
121 # define NCG_Reserved_I1 22
122 # define NCG_Reserved_I2 27
123 # define NCG_Reserved_F1 f29
124 # define NCG_Reserved_F2 f30
126 #endif /* alpha_TARGET_ARCH */
128 /* -----------------------------------------------------------------------------
129 The HP-PA register mapping
131 We cater for HP-PA 1.1.
133 \tr{%r0}--\tr{%r1} are special.
134 \tr{%r2} is the return pointer.
135 \tr{%r3} is the frame pointer.
136 \tr{%r4}--\tr{%r18} are callee-save registers.
137 \tr{%r19} is a linkage table register for HPUX 8.0 shared libraries.
138 \tr{%r20}--\tr{%r22} are caller-save registers.
139 \tr{%r23}--\tr{%r26} are parameter registers.
140 \tr{%r27} is a global data pointer.
141 \tr{%r28}--\tr{%r29} are temporaries.
142 \tr{%r30} is the stack pointer.
143 \tr{%r31} is a temporary.
145 \tr{%fr12}--\tr{%fr15} are some callee-save floating-point registers.
146 \tr{%fr8}--\tr{%fr11} are some available caller-save fl-pt registers.
147 -------------------------------------------------------------------------- */
149 #if hppa1_1_TARGET_ARCH
151 #define REG(x) __asm__("%" #x)
167 #define REG_D1 fr20 /* L & R */
168 #define REG_D2 fr21 /* L & R */
176 #define NCG_Reserved_I1 r28
177 #define NCG_Reserved_I2 r29
178 #define NCG_Reserved_F1 fr8
179 #define NCG_Reserved_F2 fr8R
180 #define NCG_Reserved_D1 fr10
181 #define NCG_Reserved_D2 fr11
185 /* -----------------------------------------------------------------------------
186 The x86 register mapping
188 Ok, we've only got 6 general purpose registers, a frame pointer and a
189 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
190 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
191 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
200 Leaving SpLim, and HpLim out of the picture.
201 -------------------------------------------------------------------------- */
206 #define REG(x) __asm__("%" #x)
208 #ifndef not_doing_dynamic_linking
213 #ifndef STOLEN_X86_REGS
214 #define STOLEN_X86_REGS 4
217 #if STOLEN_X86_REGS >= 3
221 #if STOLEN_X86_REGS >= 4
225 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
226 #define MAX_REAL_FLOAT_REG 0
227 #define MAX_REAL_DOUBLE_REG 0
228 #define MAX_REAL_LONG_REG 0
232 /* -----------------------------------------------------------------------------
233 The x86-64 register mapping
239 %rdx (seem to be used as arg regs on x86-64)
240 %rsi (seem to be used as arg regs on x86-64)
241 %rdi (seem to be used as arg regs on x86-64)
243 %rsp (unavailable - stack pointer)
252 --------------------------------------------------------------------------- */
254 #if x86_64_TARGET_ARCH
256 #define REG(x) __asm__("%" #x)
262 #define REG_SpLim r14
263 #define REG_HpLim r15
264 /* ToDo: try R2/R3 instead of SpLim/HpLim? */
266 #define MAX_REAL_VANILLA_REG 1
267 #define MAX_REAL_FLOAT_REG 0
268 #define MAX_REAL_DOUBLE_REG 0
269 #define MAX_REAL_LONG_REG 0
273 /* -----------------------------------------------------------------------------
274 The Motorola 680x0 register mapping
276 A Sun3 (mc680x0) has eight address registers, \tr{a0} to \tr{a7}, and
277 eight data registers, \tr{d0} to \tr{d7}. Address operations have to
278 be done through address registers; data registers are used for
279 comparison values and data.
281 Here's the register-usage picture for m68k boxes with GCC.
284 a0 & used directly by GCC \\
285 a1 & used directly by GCC \\
287 a2..a5 & callee-saved: available for STG registers \\
288 & (a5 may be special, ``global'' register for PIC?) \\
290 a6 & C-stack frame pointer \\
291 a7 & C-stack pointer \\
293 d0 & used directly by GCC \\
294 d1 & used directly by GCC \\
295 d2 & really needed for local optimisation by GCC \\
297 d3..d7 & callee-saved: available for STG registers
299 fp0 & call-clobbered \\
300 fp1 & call-clobbered \\
301 fp2..fp7 & callee-saved: available for STG registers
303 -------------------------------------------------------------------------- */
307 #define REG(x) __asm__(#x)
319 #define MAX_REAL_VANILLA_REG 2
333 /* -----------------------------------------------------------------------------
334 The DECstation (MIPS) register mapping
336 Here's at least some simple stuff about registers on a MIPS.
338 \tr{s0}--\tr{s7} are callee-save integer registers; they are our
339 ``prize'' stolen registers. There is also a wad of callee-save
340 floating-point registers, \tr{$f20}--\tr{$f31}; we'll use some of
343 \tr{t0}--\tr{t9} are caller-save (``temporary?'') integer registers.
344 We can steal some, but we might have to save/restore around ccalls.
345 -------------------------------------------------------------------------- */
347 #if mipsel_TARGET_ARCH || mipseb_TARGET_ARCH
349 #define REG(x) __asm__("$" #x)
351 #define CALLER_SAVES_R1
352 #define CALLER_SAVES_R2
353 #define CALLER_SAVES_R3
354 #define CALLER_SAVES_R4
355 #define CALLER_SAVES_R5
356 #define CALLER_SAVES_R6
357 #define CALLER_SAVES_R7
358 #define CALLER_SAVES_R8
360 #define CALLER_SAVES_USER
385 #endif /* mipse[lb] */
387 /* -----------------------------------------------------------------------------
388 The PowerPC register mapping
390 0 system glue? (caller-save, volatile)
391 1 SP (callee-save, non-volatile)
392 2 RTOC (callee-save, non-volatile)
393 3-10 args/return (caller-save, volatile)
394 11,12 system glue? (caller-save, volatile)
395 13-31 (callee-save, non-volatile)
397 f0 (caller-save, volatile)
398 f1-f13 args/return (caller-save, volatile)
399 f14-f31 (callee-save, non-volatile)
401 \tr{13}--\tr{31} are wonderful callee-save registers.
402 \tr{0}--\tr{12} are caller-save registers.
404 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
406 I think we can do the Whole Business with callee-save registers only!
407 -------------------------------------------------------------------------- */
409 #if powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH
411 #define REG(x) __asm__(#x)
422 #ifdef darwin_TARGET_OS
445 #define REG_SpLim r24
448 #define REG_HpLim r26
454 /* -----------------------------------------------------------------------------
455 The IA64 register mapping
457 We place the general registers in the locals area of the register stack,
458 so that the call mechanism takes care of saving them for us. We reserve
459 the first 16 for gcc's use - since gcc uses the highest used register to
460 determine the register stack frame size, this gives us a constant size
461 register stack frame.
463 \tr{f16-f32} are the callee-saved floating point registers.
464 -------------------------------------------------------------------------- */
466 #ifdef ia64_TARGET_ARCH
468 #define REG(x) __asm__(#x)
488 #define REG_SpLim loc26
491 #define REG_HpLim loc28
495 /* -----------------------------------------------------------------------------
496 The Sun SPARC register mapping
498 The SPARC register (window) story: Remember, within the Haskell
499 Threaded World, we essentially ``shut down'' the register-window
500 mechanism---the window doesn't move at all while in this World. It
501 *does* move, of course, if we call out to arbitrary~C...
503 The %i, %l, and %o registers (8 each) are the input, local, and
504 output registers visible in one register window. The 8 %g (global)
505 registers are visible all the time.
507 %o0..%o7 not available; can be zapped by callee
508 (%o6 is C-stack ptr; %o7 hold ret addrs)
509 %i0..%i7 available (except %i6 is used as frame ptr)
510 (and %i7 tends to have ret-addr-ish things)
512 %g0..%g4 not available; prone to stomping by division, etc.
513 %g5..%g7 not available; reserved for the OS
515 Note: %g3 is *definitely* clobbered in the builtin divide code (and
516 our save/restore machinery is NOT GOOD ENOUGH for that); discretion
517 being the better part of valor, we also don't take %g4.
519 The paired nature of the floating point registers causes complications for
520 the native code generator. For convenience, we pretend that the first 22
521 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
522 float (single) regs. The NCG acts accordingly. That means that the
523 following FP assignment is rather fragile, and should only be changed
524 with extreme care. The current scheme is:
526 %f0 /%f1 FP return from C
529 %f6 /%f7 ncg double spill tmp #1
530 %f8 /%f9 ncg double spill tmp #2
531 %f10/%f11 allocatable
532 %f12/%f13 allocatable
533 %f14/%f15 allocatable
534 %f16/%f17 allocatable
535 %f18/%f19 allocatable
536 %f20/%f21 allocatable
542 %f26 ncg single spill tmp #1
543 %f27 ncg single spill tmp #2
549 -------------------------------------------------------------------------- */
551 #if sparc_TARGET_ARCH
553 #define REG(x) __asm__("%" #x)
555 #define CALLER_SAVES_USER
557 #define CALLER_SAVES_F1
558 #define CALLER_SAVES_F2
559 #define CALLER_SAVES_F3
560 #define CALLER_SAVES_F4
561 #define CALLER_SAVES_D1
562 #define CALLER_SAVES_D2
586 #define NCG_SpillTmp_I1 g1
587 #define NCG_SpillTmp_I2 g2
588 #define NCG_SpillTmp_F1 f26
589 #define NCG_SpillTmp_F2 f27
590 #define NCG_SpillTmp_D1 f6
591 #define NCG_SpillTmp_D2 f8
593 #define NCG_FirstFloatReg f22
599 /* -----------------------------------------------------------------------------
600 * These constants define how many stg registers will be used for
601 * passing arguments (and results, in the case of an unboxed-tuple
604 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
605 * highest STG register to occupy a real machine register, otherwise
606 * the calling conventions will needlessly shuffle data between the
607 * stack and memory-resident STG registers. We might occasionally
608 * set these macros to other values for testing, though.
610 * Registers above these values might still be used, for instance to
611 * communicate with PrimOps and RTS functions.
614 #ifndef MAX_REAL_VANILLA_REG
616 # define MAX_REAL_VANILLA_REG 8
617 # elif defined(REG_R7)
618 # define MAX_REAL_VANILLA_REG 7
619 # elif defined(REG_R6)
620 # define MAX_REAL_VANILLA_REG 6
621 # elif defined(REG_R5)
622 # define MAX_REAL_VANILLA_REG 5
623 # elif defined(REG_R4)
624 # define MAX_REAL_VANILLA_REG 4
625 # elif defined(REG_R3)
626 # define MAX_REAL_VANILLA_REG 3
627 # elif defined(REG_R2)
628 # define MAX_REAL_VANILLA_REG 2
629 # elif defined(REG_R1)
630 # define MAX_REAL_VANILLA_REG 1
632 # define MAX_REAL_VANILLA_REG 0
636 #ifndef MAX_REAL_FLOAT_REG
638 # define MAX_REAL_FLOAT_REG 4
639 # elif defined(REG_F3)
640 # define MAX_REAL_FLOAT_REG 3
641 # elif defined(REG_F2)
642 # define MAX_REAL_FLOAT_REG 2
643 # elif defined(REG_F1)
644 # define MAX_REAL_FLOAT_REG 1
646 # define MAX_REAL_FLOAT_REG 0
650 #ifndef MAX_REAL_DOUBLE_REG
652 # define MAX_REAL_DOUBLE_REG 2
653 # elif defined(REG_D1)
654 # define MAX_REAL_DOUBLE_REG 1
656 # define MAX_REAL_DOUBLE_REG 0
660 #ifndef MAX_REAL_LONG_REG
662 # define MAX_REAL_LONG_REG 1
664 # define MAX_REAL_LONG_REG 0
668 /* define NO_ARG_REGS if we have no argument registers at all (we can
669 * optimise certain code paths using this predicate).
671 #if MAX_REAL_VANILLA_REG < 2
677 #endif /* MACHREGS_H */