2 % (c) The GRASP Project, Glasgow University, 1994
4 \section[MachRegs-decls]{Architecture-specific register mappings}
6 NB: THIS FILE IS INCLUDED IN HASKELL SOURCE!
12 #if defined(__STG_GCC_REGS__) || defined(COMPILING_NCG)
14 #include "StgMachDeps.h"
18 %************************************************************************
20 \subsection[register-tricks]{Things to watch out for}
22 %************************************************************************
24 Here we collect random pieces of lore about register mapping. It is a
27 The best place to get a blow-by-blow account of the register story for
28 a particular machine architecture is in the ``main mapping'' section
29 (\sectionref{main-mapping-StgRegs}).
31 %************************************************************************
33 \subsubsection{Using callee-saves registers}
35 %************************************************************************
37 Mostly we map variables to callee-saves registers. These are
38 best---the only thing you have to worry about is that whoever starts
39 up a wadge of code that uses them does, in fact, save them! (i.e.,
40 observes the callee-save convention).
42 To see what GCC thinks is a callee-save register: Look at the
43 \tr{FIXED_REGISTERS} and \tr{CALL_USED_REGISTERS} tables for an
44 architecture. A register that is marked as \tr{0} in both tables is
47 Of course, whatever you do, it isn't wise to grab {\em all} available
48 registers, because then GCC has nothing to use for temporaries, etc.
50 %************************************************************************
52 \subsubsection{Using caller-saves registers}
54 %************************************************************************
56 Using callee-saves registers only isn't really good enough. For
57 example, on a SPARC, {\em none} of the floating-point registers are
58 callee-save, so it's caller-save registers or terrible performance...
59 Also, modern RISC architectures normally offer about eight callee-save
60 registers; we'd really rather steal more machine registers.
62 We need to be extra careful with stolen caller-save registers. We
63 don't want to save them {\em all} across every call to a C function
64 (specifically @ccall@s). Here is table of what STG registers {\em
65 must} be saved across @ccalls@ if they are held in caller-save
68 SpA, SuA, must be saved *every time* if
69 SpB, SuB, Hp, HpLim in a caller-save reg (to be avoided)
71 TagReg Usually won't be in a register, unless we have a
72 register glut. In any event, it needn't be saved;
73 it isn't live at ccalls.
74 CLAIM: it isn't alive during other PrimOps either!
76 R1 (Node), R2 ... R8 must be saved if in a caller-save reg *and*
77 FltReg1 .. n its value survives over the ccall [rare] (the
78 DblReg1 .. n code-generator knows this...)
81 BaseReg, better choices for caller-saves regs than the
82 StkStub,... other system regs, since they only need to be
83 restored, and never saved. (For PAR, BaseReg
84 is not fixed, and must be saved.)
87 So: the compiler emits suitable \tr{CALLER_SAVE_<reg-name>} macros
88 before a ccall, and corresponding \tr{...RESTORE...}s afterwards. It
89 {\em always} emits them for @BaseReg@ and friends; it emits them only
90 for the known-to-be-live @R1@, ..., \tr{DoubleRegN} and friends.
92 Notice that PrimOps like arbitrary-precision arithmetic can trigger
93 GC, so everything gets saved on the stack safely.
95 Special care needs to be taken for ``invisible'' calls to C functions.
96 In particular, we freely generate calls to \tr{{PK,UNPK}_{FLT,DBL}},
97 to construct and deconstruct floats and doubles. These {\em must} be
98 inlined by @gcc@, because otherwise they trash floating point
99 registers. So you have to compile with at least @gcc -O@ if you want
102 Morals: We try {\em very hard} to keep @BaseReg@ and friends in
103 callee-save registers. If we have callee-save registers available for
104 @R1@ (@Node@), etc., we use them on the more-heavily-used
105 ``low-numbered'' registers. As the likelihood of having to do a
106 SAVE/RESTORE for @R6@ (for example) is near zero, it's OK to assign it
107 a caller-save register.
109 On machines with register-based calling conventions, never try to steal
110 argument or return registers, for two reasons: (1) it breaks the
111 callWrapper approach (saves and restores have to be done inline), and
112 (2) it means that you have to be extremely careful about setting up
113 arguments for calls (and may in fact have to introduce temporaries to
114 handle simultaneous assignments to/from the argument registers).
116 %************************************************************************
118 \subsubsection[mapping-alpha]{The DEC Alpha register mapping}
120 %************************************************************************
123 \tr{$9}--\tr{$14} are our ``prize'' callee-save registers.
124 \tr{$15} is the frame pointer, and \tr{$16}--\tr{$21} are argument
125 registers. (These are off-limits.) We can steal some of the \tr{$22}-and-up
126 caller-save registers provided we do the appropriate save/restore stuff.
128 \tr{$f2}--\tr{$f9} are some callee-save floating-point registers.
130 We cannot use \tr{$23} (aka t9), \tr{$24} (aka t10), \tr{$25} (aka
131 t11), \tr{$27} (aka pv), or \tr{$28} (aka at), because they are
132 occasionally required by the assembler to handle non-primitive
133 instructions (e.g. ldb, remq). Sigh!
160 #if defined(alpha_TARGET_ARCH)
161 # define REG(x) __asm__("$" #x)
163 # if defined(MARK_REG_MAP)
165 # define REG_MStack 10
166 # define REG_MRoot 11
167 # define REG_BitArray 12
168 # define REG_HeapBase 13
169 # define REG_HeapLim 14
171 # if defined(SCAN_REG_MAP)
174 # define REG_LinkLim 11
176 # if defined(SCAV_REG_MAP)
179 # if defined(GCap) || defined(GCgn)
180 # define REG_OldGen 11
181 # endif /* GCap || GCgn */
183 # else /* default: MAIN_REG_MAP */
185 # define CALLEE_SAVES_FltReg1
186 # define CALLEE_SAVES_FltReg2
187 # define CALLEE_SAVES_FltReg3
188 # define CALLEE_SAVES_FltReg4
189 # define CALLEE_SAVES_DblReg1
190 # define CALLEE_SAVES_DblReg2
191 # define CALLEE_SAVES_SpA
192 # define CALLEE_SAVES_SuA
193 # define CALLEE_SAVES_SpB
194 # define CALLEE_SAVES_SuB
195 # define CALLEE_SAVES_Hp
196 # define CALLEE_SAVES_HpLim
198 # define CALLEE_SAVES_Ret
201 # define CALLER_SAVES_R1
202 # define CALLER_SAVES_R2
203 # define CALLER_SAVES_R3
204 # define CALLER_SAVES_R4
205 # define CALLER_SAVES_R5
206 # define CALLER_SAVES_R6
207 # define CALLER_SAVES_R7
208 # define CALLER_SAVES_R8
210 # define CALLER_SAVES_USER
235 # define REG_HpLim 14
239 # define NCG_Reserved_I1 22
240 # define NCG_Reserved_I2 27
241 # define NCG_Reserved_F1 f29
242 # define NCG_Reserved_F2 f30
244 # endif /* !SCAV_REG_MAP */
245 # endif /* !SCAN_REG_MAP */
246 # endif /* !MARK_REG_MAP */
251 %************************************************************************
253 \subsubsection[mapping-hpux]{The HP-PA register mapping}
255 %************************************************************************
257 We cater for HP-PA 1.1.
259 \tr{%r0}--\tr{%r1} are special.
260 \tr{%r2} is the return pointer.
261 \tr{%r3} is the frame pointer.
262 \tr{%r4}--\tr{%r18} are callee-save registers.
263 \tr{%r19} is a linkage table register for HPUX 8.0 shared libraries.
264 \tr{%r20}--\tr{%r22} are caller-save registers.
265 \tr{%r23}--\tr{%r26} are parameter registers.
266 \tr{%r27} is a global data pointer.
267 \tr{%r28}--\tr{%r29} are temporaries.
268 \tr{%r30} is the stack pointer.
269 \tr{%r31} is a temporary.
271 \tr{%fr12}--\tr{%fr15} are some callee-save floating-point registers.
272 \tr{%fr8}--\tr{%fr11} are some available caller-save fl-pt registers.
275 #if hppa1_1_TARGET_ARCH
277 #define REG(x) __asm__("%" #x)
279 #if defined(MARK_REG_MAP)
281 #define REG_MStack r5
283 #define REG_BitArray r7
284 #define REG_HeapBase r8
285 #define REG_HeapLim r9
287 #if defined(SCAN_REG_MAP)
290 #define REG_LinkLim r6
292 #if defined(SCAV_REG_MAP)
295 #if defined(GCap) || defined(GCgn)
296 #define REG_OldGen r6
297 #endif /* GCap || GCgn */
298 #else /* default: MAIN_REG_MAP */
301 #define CALLEE_SAVES_FltReg1
302 #define CALLEE_SAVES_FltReg2
303 #define CALLEE_SAVES_FltReg3
304 #define CALLEE_SAVES_FltReg4
305 #define CALLEE_SAVES_DblReg1
306 #define CALLEE_SAVES_DblReg2
308 #if HAVE_LONG_LONG && SIZEOF_LONG < 8
309 #define CALLEE_SAVES_LngReg1
310 #define CALLEE_SAVES_LngReg2
312 #define CALLEE_SAVES_SpA
313 #define CALLEE_SAVES_SuA
314 #define CALLEE_SAVES_SpB
315 #define CALLEE_SAVES_SuB
316 #define CALLEE_SAVES_Hp
317 #define CALLEE_SAVES_HpLim
319 #define CALLEE_SAVES_Ret
321 #define CALLEE_SAVES_R1
322 #define CALLEE_SAVES_R2
323 #define CALLEE_SAVES_R3
324 #define CALLEE_SAVES_R4
325 #define CALLEE_SAVES_R5
326 #define CALLEE_SAVES_R6
327 #define CALLEE_SAVES_R7
328 #define CALLEE_SAVES_R8
330 /* caller saves -- none */
341 #define REG_Flt1 fr12
342 #define REG_Flt2 fr12R
343 #define REG_Flt3 fr13
344 #define REG_Flt4 fr13R
346 #define REG_Dbl1 fr20 /* L & R */
347 #define REG_Dbl2 fr21 /* L & R */
359 /* #define REG_StkStub r2 */
361 #define NCG_Reserved_I1 r28
362 #define NCG_Reserved_I2 r29
363 #define NCG_Reserved_F1 fr8
364 #define NCG_Reserved_F2 fr8R
365 #define NCG_Reserved_D1 fr10
366 #define NCG_Reserved_D2 fr11
368 #endif /* SCAV_REG_MAP */
369 #endif /* SCAN_REG_MAP */
370 #endif /* MARK_REG_MAP */
375 %************************************************************************
377 \subsubsection[mapping-iX86]{The Intel iX86 register mapping}
379 %************************************************************************
381 Ok, we've only got 6 general purpose registers, a frame pointer and a
382 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
383 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
384 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
389 #define REG(x) __asm__("%" #x)
391 #if defined(MARK_REG_MAP)
392 #define REG_MarkBase ebx
394 #define REG_MStack esi
395 #define REG_MRoot edi
398 #if defined(SCAN_REG_MAP)
401 #define REG_LinkLim esi
404 #if defined(SCAV_REG_MAP)
407 #if defined(GCap) || defined(GCgn)
408 /* NO: -concurrent croaks on SMevac.lc with this
409 #define REG_OldGen esi
411 #endif /* GCap || GCgn */
413 #else /* default: MAIN_REG_MAP */
416 #define CALLEE_SAVES_Base
417 #define CALLEE_SAVES_SpB
419 /* caller saves -- none */
421 /* After trying to steal 4 regs, ... crash:
426 - give back edi & ebp
432 /* SpB and R1 are the two heaviest hitters, followed by SpA.
433 Hp comes next, followed closely by R2;
434 then RetReg, then R3 and R4.
435 At least based on some static counts.
440 #if STOLEN_X86_REGS >= 3
442 # define CALLEE_SAVES_R1
444 #if STOLEN_X86_REGS >= 4
446 # define CALLEE_SAVES_SpA
448 #if STOLEN_X86_REGS >= 5
451 # define CALLER_SAVES_Hp
452 # define CALLER_SAVES_SYSTEM
454 /* because we *might* have Hp in a caller-saves register */
458 #endif /* SCAV_REG_MAP */
459 #endif /* SCAN_REG_MAP */
460 #endif /* MARK_REG_MAP */
465 %************************************************************************
467 \subsubsection[mapping-m68k]{The Motorola 680x0 register mapping}
469 %************************************************************************
471 A Sun3 (mc680x0) has eight address registers, \tr{a0} to \tr{a7}, and
472 eight data registers, \tr{d0} to \tr{d7}. Address operations have to
473 be done through address registers; data registers are used for
474 comparison values and data.
476 Here's the register-usage picture for m68k boxes with GCC.
479 a0 & used directly by GCC \\
480 a1 & used directly by GCC \\
482 a2..a5 & callee-saved: available for STG registers \\
483 & (a5 may be special, ``global'' register for PIC?) \\
485 a6 & C-stack frame pointer \\
486 a7 & C-stack pointer \\
488 d0 & used directly by GCC \\
489 d1 & used directly by GCC \\
490 d2 & really needed for local optimisation by GCC \\
492 d3..d7 & callee-saved: available for STG registers
494 fp0 & call-clobbered \\
495 fp1 & call-clobbered \\
496 fp2..fp7 & callee-saved: available for STG registers
502 #define REG(x) __asm__(#x)
504 #if defined(FLUSH_REG_MAP)
505 #define REG_FlushP a2
506 #define REG_FStack a3
507 #define REG_FlushTemp a4
509 #if defined(MARK_REG_MAP)
511 #define REG_MStack a3
513 #define REG_BitArray a5
514 #define REG_HeapBase d3
515 #define REG_HeapLim d4
517 #if defined(SCAN_REG_MAP)
520 #define REG_LinkLim a4
522 #if defined(SCAV_REG_MAP)
526 #define REG_OldGen a4
529 #define REG_OldGen a4
530 #define REG_AllocGen a5
534 #else /* default: MAIN_REG_MAP */
537 #define CALLEE_SAVES_FltReg1
538 #define CALLEE_SAVES_DblReg1
539 #if !defined(CONCURRENT)
540 # define CALLEE_SAVES_FltReg2
541 # define CALLEE_SAVES_FltReg3
542 # define CALLEE_SAVES_FltReg4
543 # define CALLEE_SAVES_DblReg2
545 #if HAVE_LONG_LONG && SIZEOF_LONG < 8
546 #define CALLEE_SAVES_LngReg1
547 #define CALLEE_SAVES_LngReg2
549 #define CALLEE_SAVES_Base
550 #define CALLEE_SAVES_SpB
551 #define CALLEE_SAVES_SpA
552 #define CALLEE_SAVES_Hp
553 #define CALLEE_SAVES_SuA
554 #define CALLEE_SAVES_SuB
556 #define CALLEE_SAVES_R1
557 #define CALLEE_SAVES_R2
558 #define CALLEE_SAVES_Ret
560 /* caller saves -- none */
577 #if !defined(CONCURRENT)
578 /* The extra float registers are not worth the tradeoff in
579 context-switch time for most programs (for now, at least).
587 /* The extra double registers are not worth the tradeoff in
588 context-switch time for most programs (for now, at least).
590 #if !defined(CONCURRENT)
594 #endif /* SCAV_REG_MAP */
595 #endif /* SCAN_REG_MAP */
596 #endif /* MARK_REG_MAP */
597 #endif /* FLUSH_REG_MAP */
602 %************************************************************************
604 \subsubsection[mapping-mipsel]{The DECstation (MIPS) register mapping}
606 %************************************************************************
608 Here's at least some simple stuff about registers on a MIPS.
610 \tr{s0}--\tr{s7} are callee-save integer registers; they are our
611 ``prize'' stolen registers. There is also a wad of callee-save
612 floating-point registers, \tr{$f20}--\tr{$f31}; we'll use some of
615 \tr{t0}--\tr{t9} are caller-save (``temporary?'') integer registers.
616 We can steal some, but we might have to save/restore around ccalls.
619 #if mipsel_TARGET_ARCH || mipseb_TARGET_ARCH
621 #define REG(x) __asm__("$" #x)
623 #if defined(MARK_REG_MAP)
625 #define REG_MStack 17
627 #define REG_BitArray 19
628 #define REG_HeapBase 20
629 #define REG_HeapLim 21
631 #if defined(SCAN_REG_MAP)
634 #define REG_LinkLim 18
636 #if defined(SCAV_REG_MAP)
639 #if defined(GCap) || defined(GCgn)
640 #define REG_OldGen 18
641 #endif /* GCap || GCgn */
642 #else /* default: MAIN_REG_MAP */
645 #define CALLEE_SAVES_FltReg1
646 #define CALLEE_SAVES_FltReg2
647 #define CALLEE_SAVES_FltReg3
648 #define CALLEE_SAVES_FltReg4
649 #define CALLEE_SAVES_DblReg1
650 #define CALLEE_SAVES_DblReg2
651 #if HAVE_LONG_LONG && SIZEOF_LONG < 8
652 #define CALLEE_SAVES_LngReg1
653 #define CALLEE_SAVES_LngReg2
655 #define CALLEE_SAVES_SpA
656 #define CALLEE_SAVES_SuA
657 #define CALLEE_SAVES_SpB
658 #define CALLEE_SAVES_SuB
659 #define CALLEE_SAVES_Hp
660 #define CALLEE_SAVES_HpLim
662 #define CALLEE_SAVES_Ret
665 #define CALLER_SAVES_R1
666 #define CALLER_SAVES_R2
667 #define CALLER_SAVES_R3
668 #define CALLER_SAVES_R4
669 #define CALLER_SAVES_R5
670 #define CALLER_SAVES_R6
671 #define CALLER_SAVES_R7
672 #define CALLER_SAVES_R8
674 #define CALLER_SAVES_USER
703 #define REG_StkStub 23
705 #endif /* SCAV_REG_MAP */
706 #endif /* SCAN_REG_MAP */
707 #endif /* MARK_REG_MAP */
709 #endif /* mipse[lb] */
712 %************************************************************************
714 \subsubsection[mapping-powerpc]{The PowerPC register mapping}
716 %************************************************************************
718 0 system glue? (caller-save, volatile)
719 1 SP (callee-save, non-volatile)
720 2 RTOC (callee-save, non-volatile)
721 3-10 args/return (caller-save, volatile)
722 11,12 system glue? (caller-save, volatile)
723 13-31 (callee-save, non-volatile)
725 f0 (caller-save, volatile)
726 f1-f13 args/return (caller-save, volatile)
727 f14-f31 (callee-save, non-volatile)
729 \tr{13}--\tr{31} are wonderful callee-save registers.
730 \tr{0}--\tr{12} are caller-save registers.
732 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
734 I think we can do the Whole Business with callee-save registers only!
737 #if powerpc_TARGET_ARCH || rs6000_TARGET_ARCH
739 #define REG(x) __asm__(#x)
741 #if defined(MARK_REG_MAP)
743 #define REG_MStack r23
744 #define REG_MRoot r24
745 #define REG_BitArray r25
746 #define REG_HeapBase r26
747 #define REG_HeapLim r27
749 #if defined(SCAN_REG_MAP)
752 #define REG_LinkLim r24
754 #if defined(SCAV_REG_MAP)
757 #if defined(GCap) || defined(GCgn)
758 #define REG_OldGen r24
759 #endif /* GCap || GCgn */
760 #else /* default: MAIN_REG_MAP */
763 #define CALLEE_SAVES_FltReg1
764 #define CALLEE_SAVES_FltReg2
765 #define CALLEE_SAVES_FltReg3
766 #define CALLEE_SAVES_FltReg4
767 #define CALLEE_SAVES_DblReg1
768 #define CALLEE_SAVES_DblReg2
769 #if HAVE_LONG_LONG && SIZEOF_LONG < 8
770 #define CALLEE_SAVES_LngReg1
771 #define CALLEE_SAVES_LngReg2
773 #define CALLEE_SAVES_SpA
774 #define CALLEE_SAVES_SuA
775 #define CALLEE_SAVES_SpB
776 #define CALLEE_SAVES_SuB
777 #define CALLEE_SAVES_Hp
778 #define CALLEE_SAVES_HpLim
780 #define CALLEE_SAVES_Ret
782 #define CALLEE_SAVES_R1
783 #define CALLEE_SAVES_R2
784 #define CALLEE_SAVES_R3
785 #define CALLEE_SAVES_R4
786 #define CALLEE_SAVES_R5
787 #define CALLEE_SAVES_R6
788 #define CALLEE_SAVES_R7
789 #define CALLEE_SAVES_R8
800 #define REG_Flt1 fr14
801 #define REG_Flt2 fr15
802 #define REG_Flt3 fr16
803 #define REG_Flt4 fr17
805 #define REG_Dbl1 fr18
806 #define REG_Dbl2 fr19
814 #define REG_HpLim r27
818 #define REG_StkStub r29
820 #endif /* SCAV_REG_MAP */
821 #endif /* SCAN_REG_MAP */
822 #endif /* MARK_REG_MAP */
827 %************************************************************************
829 \subsubsection[mapping-sparc]{The Sun SPARC register mapping}
831 %************************************************************************
833 The SPARC register (window) story: Remember, within the Haskell
834 Threaded World, we essentially ``shut down'' the register-window
835 mechanism---the window doesn't move at all while in this World. It
836 {\em does} move, of course, if we call out to arbitrary~C...
838 The \tr{%i}, \tr{%l}, and \tr{%o} registers (8 each) are the input,
839 local, and output registers visible in one register window. The 8
840 \tr{%g} (global) registers are visible all the time.
843 \tr{%o0}..\tr{%o7} & not available; can be zapped by callee \\
844 & (\tr{%o6} is C-stack ptr; \tr{%o7} hold ret addrs) \\
845 \tr{%i0}..\tr{%i7} & available (except \tr{%i6} is used as frame ptr) \\
846 & (and \tr{%i7} tends to have ret-addr-ish things) \\
847 \tr{%l0}..\tr{%l7} & available \\
848 \tr{%g0}..\tr{%g4} & not available; prone to stomping by division, etc.\\
849 \tr{%g5}..\tr{%g7} & not available; reserved for the OS \\
852 Note: \tr{%g3} is {\em definitely} clobbered in the builtin divide
853 code (and our save/restore machinery is NOT GOOD ENOUGH for that);
854 discretion being the better part of valor, we also don't take
858 #if sparc_TARGET_ARCH
860 #define REG(x) __asm__("%" #x)
862 #if defined(MARK_REG_MAP)
864 #define REG_MStack i1
866 #define REG_BitArray i3
867 #define REG_HeapBase i4
868 #define REG_HeapLim i5
870 #if defined(SCAN_REG_MAP)
871 #define REG_ScanBase g4
872 /* NB: *not* defining this (so that everything is done w/ global variables)
873 does *not* work; I suspect that the Sca[nv]RegTable is not being
874 initialised somewhere... WDP 95/10
877 #if defined(SCAV_REG_MAP)
878 #define REG_ScavBase g4
879 /* see comment above */
880 #else /* default: MAIN_REG_MAP */
882 /* callee saves (nothing) */
884 /* caller saves (fp registers) */
886 #define CALLER_SAVES_USER
888 #define CALLER_SAVES_FltReg1
889 #define CALLER_SAVES_FltReg2
890 #define CALLER_SAVES_FltReg3
891 #define CALLER_SAVES_FltReg4
892 #define CALLER_SAVES_DblReg1
893 #define CALLER_SAVES_DblReg2
894 #if HAVE_LONG_LONG && SIZEOF_LONG < 8
895 #define CALLER_SAVES_LngReg1
896 #define CALLER_SAVES_LngReg2
924 #define REG_StkStub i7
926 #define NCG_Reserved_I1 g1
927 #define NCG_Reserved_I2 g2
928 #define NCG_Reserved_F1 f14
929 #define NCG_Reserved_F2 f15
930 #define NCG_Reserved_D1 f16
931 #define NCG_Reserved_D2 f18
933 #endif /* SCAV_REG_MAP */
934 #endif /* SCAN_REG_MAP */
935 #endif /* MARK_REG_MAP */
940 Concluding multi-slurp protection:
943 #endif /* __STG_GCC_REGS__ || COMPILING_NCG */
945 #endif /* MACHREGS_H */