2 % (c) The GRASP Project, Glasgow University, 1994
4 \section[MachRegs-decls]{Architecture-specific register mappings}
6 NB: THIS FILE IS INCLUDED IN HASKELL SOURCE!
12 #if defined(__STG_GCC_REGS__) || defined(COMPILING_NCG)
14 #include "StgMachDeps.h"
18 %************************************************************************
20 \subsection[register-tricks]{Things to watch out for}
22 %************************************************************************
24 Here we collect random pieces of lore about register mapping. It is a
27 The best place to get a blow-by-blow account of the register story for
28 a particular machine architecture is in the ``main mapping'' section
29 (\sectionref{main-mapping-StgRegs}).
31 %************************************************************************
33 \subsubsection{Using callee-saves registers}
35 %************************************************************************
37 Mostly we map variables to callee-saves registers. These are
38 best---the only thing you have to worry about is that whoever starts
39 up a wadge of code that uses them does, in fact, save them! (i.e.,
40 observes the callee-save convention).
42 To see what GCC thinks is a callee-save register: Look at the
43 \tr{FIXED_REGISTERS} and \tr{CALL_USED_REGISTERS} tables for an
44 architecture. A register that is marked as \tr{0} in both tables is
47 Of course, whatever you do, it isn't wise to grab {\em all} available
48 registers, because then GCC has nothing to use for temporaries, etc.
50 %************************************************************************
52 \subsubsection{Using caller-saves registers}
54 %************************************************************************
56 Using callee-saves registers only isn't really good enough. For
57 example, on a SPARC, {\em none} of the floating-point registers are
58 callee-save, so it's caller-save registers or terrible performance...
59 Also, modern RISC architectures normally offer about eight callee-save
60 registers; we'd really rather steal more machine registers.
62 We need to be extra careful with stolen caller-save registers. We
63 don't want to save them {\em all} across every call to a C function
64 (specifically @ccall@s). Here is table of what STG registers {\em
65 must} be saved across @ccalls@ if they are held in caller-save
68 SpA, SuA, must be saved *every time* if
69 SpB, SuB, Hp, HpLim in a caller-save reg (to be avoided)
71 TagReg Usually won't be in a register, unless we have a
72 register glut. In any event, it needn't be saved;
73 it isn't live at ccalls.
74 CLAIM: it isn't alive during other PrimOps either!
76 R1 (Node), R2 ... R8 must be saved if in a caller-save reg *and*
77 FltReg1 .. n its value survives over the ccall [rare] (the
78 DblReg1 .. n code-generator knows this...)
80 BaseReg, better choices for caller-saves regs than the
81 StkStub,... other system regs, since they only need to be
82 restored, and never saved. (For PAR, BaseReg
83 is not fixed, and must be saved.)
86 So: the compiler emits suitable \tr{CALLER_SAVE_<reg-name>} macros
87 before a ccall, and corresponding \tr{...RESTORE...}s afterwards. It
88 {\em always} emits them for @BaseReg@ and friends; it emits them only
89 for the known-to-be-live @R1@, ..., \tr{DoubleRegN} and friends.
91 Notice that PrimOps like arbitrary-precision arithmetic can trigger
92 GC, so everything gets saved on the stack safely.
94 Special care needs to be taken for ``invisible'' calls to C functions.
95 In particular, we freely generate calls to \tr{{PK,UNPK}_{FLT,DBL}},
96 to construct and deconstruct floats and doubles. These {\em must} be
97 inlined by @gcc@, because otherwise they trash floating point
98 registers. So you have to compile with at least @gcc -O@ if you want
101 Morals: We try {\em very hard} to keep @BaseReg@ and friends in
102 callee-save registers. If we have callee-save registers available for
103 @R1@ (@Node@), etc., we use them on the more-heavily-used
104 ``low-numbered'' registers. As the likelihood of having to do a
105 SAVE/RESTORE for @R6@ (for example) is near zero, it's OK to assign it
106 a caller-save register.
108 On machines with register-based calling conventions, never try to steal
109 argument or return registers, for two reasons: (1) it breaks the
110 callWrapper approach (saves and restores have to be done inline), and
111 (2) it means that you have to be extremely careful about setting up
112 arguments for calls (and may in fact have to introduce temporaries to
113 handle simultaneous assignments to/from the argument registers).
115 %************************************************************************
117 \subsubsection[mapping-alpha]{The DEC Alpha register mapping}
119 %************************************************************************
122 \tr{$9}--\tr{$14} are our ``prize'' callee-save registers.
123 \tr{$15} is the frame pointer, and \tr{$16}--\tr{$21} are argument
124 registers. (These are off-limits.) We can steal some of the \tr{$22}-and-up
125 caller-save registers provided we do the appropriate save/restore stuff.
127 \tr{$f2}--\tr{$f9} are some callee-save floating-point registers.
129 We cannot use \tr{$23} (aka t9), \tr{$24} (aka t10), \tr{$25} (aka
130 t11), \tr{$27} (aka pv), or \tr{$28} (aka at), because they are
131 occasionally required by the assembler to handle non-primitive
132 instructions (e.g. ldb, remq). Sigh!
159 #if defined(alpha_TARGET_ARCH)
160 # define REG(x) __asm__("$" #x)
162 # if defined(MARK_REG_MAP)
164 # define REG_MStack 10
165 # define REG_MRoot 11
166 # define REG_BitArray 12
167 # define REG_HeapBase 13
168 # define REG_HeapLim 14
170 # if defined(SCAN_REG_MAP)
173 # define REG_LinkLim 11
175 # if defined(SCAV_REG_MAP)
178 # if defined(GCap) || defined(GCgn)
179 # define REG_OldGen 11
180 # endif /* GCap || GCgn */
182 # else /* default: MAIN_REG_MAP */
184 # define CALLEE_SAVES_FltReg1
185 # define CALLEE_SAVES_FltReg2
186 # define CALLEE_SAVES_FltReg3
187 # define CALLEE_SAVES_FltReg4
188 # define CALLEE_SAVES_DblReg1
189 # define CALLEE_SAVES_DblReg2
190 # define CALLEE_SAVES_SpA
191 # define CALLEE_SAVES_SuA
192 # define CALLEE_SAVES_SpB
193 # define CALLEE_SAVES_SuB
194 # define CALLEE_SAVES_Hp
195 # define CALLEE_SAVES_HpLim
197 # define CALLEE_SAVES_Ret
200 # define CALLER_SAVES_R1
201 # define CALLER_SAVES_R2
202 # define CALLER_SAVES_R3
203 # define CALLER_SAVES_R4
204 # define CALLER_SAVES_R5
205 # define CALLER_SAVES_R6
206 # define CALLER_SAVES_R7
207 # define CALLER_SAVES_R8
209 # define CALLER_SAVES_USER
234 # define REG_HpLim 14
238 # define NCG_Reserved_I1 22
239 # define NCG_Reserved_I2 27
240 # define NCG_Reserved_F1 f29
241 # define NCG_Reserved_F2 f30
243 # endif /* !SCAV_REG_MAP */
244 # endif /* !SCAN_REG_MAP */
245 # endif /* !MARK_REG_MAP */
250 %************************************************************************
252 \subsubsection[mapping-hpux]{The HP-PA register mapping}
254 %************************************************************************
256 We cater for HP-PA 1.1.
258 \tr{%r0}--\tr{%r1} are special.
259 \tr{%r2} is the return pointer.
260 \tr{%r3} is the frame pointer.
261 \tr{%r4}--\tr{%r18} are callee-save registers.
262 \tr{%r19} is a linkage table register for HPUX 8.0 shared libraries.
263 \tr{%r20}--\tr{%r22} are caller-save registers.
264 \tr{%r23}--\tr{%r26} are parameter registers.
265 \tr{%r27} is a global data pointer.
266 \tr{%r28}--\tr{%r29} are temporaries.
267 \tr{%r30} is the stack pointer.
268 \tr{%r31} is a temporary.
270 \tr{%fr12}--\tr{%fr15} are some callee-save floating-point registers.
271 \tr{%fr8}--\tr{%fr11} are some available caller-save fl-pt registers.
274 #if hppa1_1_TARGET_ARCH
276 #define REG(x) __asm__("%" #x)
278 #if defined(MARK_REG_MAP)
280 #define REG_MStack r5
282 #define REG_BitArray r7
283 #define REG_HeapBase r8
284 #define REG_HeapLim r9
286 #if defined(SCAN_REG_MAP)
289 #define REG_LinkLim r6
291 #if defined(SCAV_REG_MAP)
294 #if defined(GCap) || defined(GCgn)
295 #define REG_OldGen r6
296 #endif /* GCap || GCgn */
297 #else /* default: MAIN_REG_MAP */
300 #define CALLEE_SAVES_FltReg1
301 #define CALLEE_SAVES_FltReg2
302 #define CALLEE_SAVES_FltReg3
303 #define CALLEE_SAVES_FltReg4
304 #define CALLEE_SAVES_DblReg1
305 #define CALLEE_SAVES_DblReg2
306 #define CALLEE_SAVES_SpA
307 #define CALLEE_SAVES_SuA
308 #define CALLEE_SAVES_SpB
309 #define CALLEE_SAVES_SuB
310 #define CALLEE_SAVES_Hp
311 #define CALLEE_SAVES_HpLim
313 #define CALLEE_SAVES_Ret
315 #define CALLEE_SAVES_R1
316 #define CALLEE_SAVES_R2
317 #define CALLEE_SAVES_R3
318 #define CALLEE_SAVES_R4
319 #define CALLEE_SAVES_R5
320 #define CALLEE_SAVES_R6
321 #define CALLEE_SAVES_R7
322 #define CALLEE_SAVES_R8
324 /* caller saves -- none */
335 #define REG_Flt1 fr12
336 #define REG_Flt2 fr12R
337 #define REG_Flt3 fr13
338 #define REG_Flt4 fr13R
340 #define REG_Dbl1 fr20 /* L & R */
341 #define REG_Dbl2 fr21 /* L & R */
353 /* #define REG_StkStub r2 */
355 #define NCG_Reserved_I1 r28
356 #define NCG_Reserved_I2 r29
357 #define NCG_Reserved_F1 fr8
358 #define NCG_Reserved_F2 fr8R
359 #define NCG_Reserved_D1 fr10
360 #define NCG_Reserved_D2 fr11
362 #endif /* SCAV_REG_MAP */
363 #endif /* SCAN_REG_MAP */
364 #endif /* MARK_REG_MAP */
369 %************************************************************************
371 \subsubsection[mapping-iX86]{The Intel iX86 register mapping}
373 %************************************************************************
375 Ok, we've only got 6 general purpose registers, a frame pointer and a
376 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
377 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
378 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
383 #define REG(x) __asm__("%" #x)
385 #if defined(MARK_REG_MAP)
386 #define REG_MarkBase ebx
388 #define REG_MStack esi
389 #define REG_MRoot edi
392 #if defined(SCAN_REG_MAP)
395 #define REG_LinkLim esi
398 #if defined(SCAV_REG_MAP)
401 #if defined(GCap) || defined(GCgn)
402 /* NO: -concurrent croaks on SMevac.lc with this
403 #define REG_OldGen esi
405 #endif /* GCap || GCgn */
407 #else /* default: MAIN_REG_MAP */
410 #define CALLEE_SAVES_Base
411 #define CALLEE_SAVES_SpB
413 /* caller saves -- none */
415 /* After trying to steal 4 regs, ... crash:
420 - give back edi & ebp
426 /* SpB and R1 are the two heaviest hitters, followed by SpA.
427 Hp comes next, followed closely by R2;
428 then RetReg, then R3 and R4.
429 At least based on some static counts.
434 #if STOLEN_X86_REGS >= 3
436 # define CALLEE_SAVES_R1
438 #if STOLEN_X86_REGS >= 4
440 # define CALLEE_SAVES_SpA
442 #if STOLEN_X86_REGS >= 5
445 # define CALLER_SAVES_Hp
446 # define CALLER_SAVES_SYSTEM
448 /* because we *might* have Hp in a caller-saves register */
452 #endif /* SCAV_REG_MAP */
453 #endif /* SCAN_REG_MAP */
454 #endif /* MARK_REG_MAP */
459 %************************************************************************
461 \subsubsection[mapping-m68k]{The Motorola 680x0 register mapping}
463 %************************************************************************
465 A Sun3 (mc680x0) has eight address registers, \tr{a0} to \tr{a7}, and
466 eight data registers, \tr{d0} to \tr{d7}. Address operations have to
467 be done through address registers; data registers are used for
468 comparison values and data.
470 Here's the register-usage picture for m68k boxes with GCC.
473 a0 & used directly by GCC \\
474 a1 & used directly by GCC \\
476 a2..a5 & callee-saved: available for STG registers \\
477 & (a5 may be special, ``global'' register for PIC?) \\
479 a6 & C-stack frame pointer \\
480 a7 & C-stack pointer \\
482 d0 & used directly by GCC \\
483 d1 & used directly by GCC \\
484 d2 & really needed for local optimisation by GCC \\
486 d3..d7 & callee-saved: available for STG registers
488 fp0 & call-clobbered \\
489 fp1 & call-clobbered \\
490 fp2..fp7 & callee-saved: available for STG registers
496 #define REG(x) __asm__(#x)
498 #if defined(FLUSH_REG_MAP)
499 #define REG_FlushP a2
500 #define REG_FStack a3
501 #define REG_FlushTemp a4
503 #if defined(MARK_REG_MAP)
505 #define REG_MStack a3
507 #define REG_BitArray a5
508 #define REG_HeapBase d3
509 #define REG_HeapLim d4
511 #if defined(SCAN_REG_MAP)
514 #define REG_LinkLim a4
516 #if defined(SCAV_REG_MAP)
520 #define REG_OldGen a4
523 #define REG_OldGen a4
524 #define REG_AllocGen a5
528 #else /* default: MAIN_REG_MAP */
531 #define CALLEE_SAVES_FltReg1
532 #define CALLEE_SAVES_DblReg1
533 #if !defined(CONCURRENT)
534 # define CALLEE_SAVES_FltReg2
535 # define CALLEE_SAVES_FltReg3
536 # define CALLEE_SAVES_FltReg4
537 # define CALLEE_SAVES_DblReg2
539 #define CALLEE_SAVES_Base
540 #define CALLEE_SAVES_SpB
541 #define CALLEE_SAVES_SpA
542 #define CALLEE_SAVES_Hp
543 #define CALLEE_SAVES_SuA
544 #define CALLEE_SAVES_SuB
546 #define CALLEE_SAVES_R1
547 #define CALLEE_SAVES_R2
548 #define CALLEE_SAVES_Ret
550 /* caller saves -- none */
567 #if !defined(CONCURRENT)
568 /* The extra float registers are not worth the tradeoff in
569 context-switch time for most programs (for now, at least).
577 /* The extra double registers are not worth the tradeoff in
578 context-switch time for most programs (for now, at least).
580 #if !defined(CONCURRENT)
584 #endif /* SCAV_REG_MAP */
585 #endif /* SCAN_REG_MAP */
586 #endif /* MARK_REG_MAP */
587 #endif /* FLUSH_REG_MAP */
592 %************************************************************************
594 \subsubsection[mapping-mipsel]{The DECstation (MIPS) register mapping}
596 %************************************************************************
598 Here's at least some simple stuff about registers on a MIPS.
600 \tr{s0}--\tr{s7} are callee-save integer registers; they are our
601 ``prize'' stolen registers. There is also a wad of callee-save
602 floating-point registers, \tr{$f20}--\tr{$f31}; we'll use some of
605 \tr{t0}--\tr{t9} are caller-save (``temporary?'') integer registers.
606 We can steal some, but we might have to save/restore around ccalls.
609 #if mipsel_TARGET_ARCH || mipseb_TARGET_ARCH
611 #define REG(x) __asm__("$" #x)
613 #if defined(MARK_REG_MAP)
615 #define REG_MStack 17
617 #define REG_BitArray 19
618 #define REG_HeapBase 20
619 #define REG_HeapLim 21
621 #if defined(SCAN_REG_MAP)
624 #define REG_LinkLim 18
626 #if defined(SCAV_REG_MAP)
629 #if defined(GCap) || defined(GCgn)
630 #define REG_OldGen 18
631 #endif /* GCap || GCgn */
632 #else /* default: MAIN_REG_MAP */
635 #define CALLEE_SAVES_FltReg1
636 #define CALLEE_SAVES_FltReg2
637 #define CALLEE_SAVES_FltReg3
638 #define CALLEE_SAVES_FltReg4
639 #define CALLEE_SAVES_DblReg1
640 #define CALLEE_SAVES_DblReg2
641 #define CALLEE_SAVES_SpA
642 #define CALLEE_SAVES_SuA
643 #define CALLEE_SAVES_SpB
644 #define CALLEE_SAVES_SuB
645 #define CALLEE_SAVES_Hp
646 #define CALLEE_SAVES_HpLim
648 #define CALLEE_SAVES_Ret
651 #define CALLER_SAVES_R1
652 #define CALLER_SAVES_R2
653 #define CALLER_SAVES_R3
654 #define CALLER_SAVES_R4
655 #define CALLER_SAVES_R5
656 #define CALLER_SAVES_R6
657 #define CALLER_SAVES_R7
658 #define CALLER_SAVES_R8
660 #define CALLER_SAVES_USER
689 #define REG_StkStub 23
691 #endif /* SCAV_REG_MAP */
692 #endif /* SCAN_REG_MAP */
693 #endif /* MARK_REG_MAP */
695 #endif /* mipse[lb] */
698 %************************************************************************
700 \subsubsection[mapping-powerpc]{The PowerPC register mapping}
702 %************************************************************************
704 0 system glue? (caller-save, volatile)
705 1 SP (callee-save, non-volatile)
706 2 RTOC (callee-save, non-volatile)
707 3-10 args/return (caller-save, volatile)
708 11,12 system glue? (caller-save, volatile)
709 13-31 (callee-save, non-volatile)
711 f0 (caller-save, volatile)
712 f1-f13 args/return (caller-save, volatile)
713 f14-f31 (callee-save, non-volatile)
715 \tr{13}--\tr{31} are wonderful callee-save registers.
716 \tr{0}--\tr{12} are caller-save registers.
718 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
720 I think we can do the Whole Business with callee-save registers only!
723 #if powerpc_TARGET_ARCH || rs6000_TARGET_ARCH
725 #define REG(x) __asm__(#x)
727 #if defined(MARK_REG_MAP)
729 #define REG_MStack r23
730 #define REG_MRoot r24
731 #define REG_BitArray r25
732 #define REG_HeapBase r26
733 #define REG_HeapLim r27
735 #if defined(SCAN_REG_MAP)
738 #define REG_LinkLim r24
740 #if defined(SCAV_REG_MAP)
743 #if defined(GCap) || defined(GCgn)
744 #define REG_OldGen r24
745 #endif /* GCap || GCgn */
746 #else /* default: MAIN_REG_MAP */
749 #define CALLEE_SAVES_FltReg1
750 #define CALLEE_SAVES_FltReg2
751 #define CALLEE_SAVES_FltReg3
752 #define CALLEE_SAVES_FltReg4
753 #define CALLEE_SAVES_DblReg1
754 #define CALLEE_SAVES_DblReg2
755 #define CALLEE_SAVES_SpA
756 #define CALLEE_SAVES_SuA
757 #define CALLEE_SAVES_SpB
758 #define CALLEE_SAVES_SuB
759 #define CALLEE_SAVES_Hp
760 #define CALLEE_SAVES_HpLim
762 #define CALLEE_SAVES_Ret
764 #define CALLEE_SAVES_R1
765 #define CALLEE_SAVES_R2
766 #define CALLEE_SAVES_R3
767 #define CALLEE_SAVES_R4
768 #define CALLEE_SAVES_R5
769 #define CALLEE_SAVES_R6
770 #define CALLEE_SAVES_R7
771 #define CALLEE_SAVES_R8
782 #define REG_Flt1 fr14
783 #define REG_Flt2 fr15
784 #define REG_Flt3 fr16
785 #define REG_Flt4 fr17
787 #define REG_Dbl1 fr18
788 #define REG_Dbl2 fr19
796 #define REG_HpLim r27
800 #define REG_StkStub r29
802 #endif /* SCAV_REG_MAP */
803 #endif /* SCAN_REG_MAP */
804 #endif /* MARK_REG_MAP */
809 %************************************************************************
811 \subsubsection[mapping-sparc]{The Sun SPARC register mapping}
813 %************************************************************************
815 The SPARC register (window) story: Remember, within the Haskell
816 Threaded World, we essentially ``shut down'' the register-window
817 mechanism---the window doesn't move at all while in this World. It
818 {\em does} move, of course, if we call out to arbitrary~C...
820 The \tr{%i}, \tr{%l}, and \tr{%o} registers (8 each) are the input,
821 local, and output registers visible in one register window. The 8
822 \tr{%g} (global) registers are visible all the time.
825 \tr{%o0}..\tr{%o7} & not available; can be zapped by callee \\
826 & (\tr{%o6} is C-stack ptr; \tr{%o7} hold ret addrs) \\
827 \tr{%i0}..\tr{%i7} & available (except \tr{%i6} is used as frame ptr) \\
828 & (and \tr{%i7} tends to have ret-addr-ish things) \\
829 \tr{%l0}..\tr{%l7} & available \\
830 \tr{%g0}..\tr{%g4} & not available; prone to stomping by division, etc.\\
831 \tr{%g5}..\tr{%g7} & not available; reserved for the OS \\
834 Note: \tr{%g3} is {\em definitely} clobbered in the builtin divide
835 code (and our save/restore machinery is NOT GOOD ENOUGH for that);
836 discretion being the better part of valor, we also don't take
840 #if sparc_TARGET_ARCH
842 #define REG(x) __asm__("%" #x)
844 #if defined(MARK_REG_MAP)
846 #define REG_MStack i1
848 #define REG_BitArray i3
849 #define REG_HeapBase i4
850 #define REG_HeapLim i5
852 #if defined(SCAN_REG_MAP)
853 #define REG_ScanBase g4
854 /* NB: *not* defining this (so that everything is done w/ global variables)
855 does *not* work; I suspect that the Sca[nv]RegTable is not being
856 initialised somewhere... WDP 95/10
859 #if defined(SCAV_REG_MAP)
860 #define REG_ScavBase g4
861 /* see comment above */
862 #else /* default: MAIN_REG_MAP */
864 /* callee saves (nothing) */
866 /* caller saves (fp registers) */
868 #define CALLER_SAVES_USER
870 #define CALLER_SAVES_FltReg1
871 #define CALLER_SAVES_FltReg2
872 #define CALLER_SAVES_FltReg3
873 #define CALLER_SAVES_FltReg4
874 #define CALLER_SAVES_DblReg1
875 #define CALLER_SAVES_DblReg2
902 #define REG_StkStub i7
904 #define NCG_Reserved_I1 g1
905 #define NCG_Reserved_I2 g2
906 #define NCG_Reserved_F1 f14
907 #define NCG_Reserved_F2 f15
908 #define NCG_Reserved_D1 f16
909 #define NCG_Reserved_D2 f18
911 #endif /* SCAV_REG_MAP */
912 #endif /* SCAN_REG_MAP */
913 #endif /* MARK_REG_MAP */
918 Concluding multi-slurp protection:
921 #endif /* __STG_GCC_REGS__ || COMPILING_NCG */
923 #endif /* MACHREGS_H */