34 type DLX_Word = Word32
35 type VDLXTrans = VTrans DLXReg DLX_Word
36 type VReg a = Virtual a Int
37 type VTrans r w = Trans DLX_Op (VReg r)
39 fillIn x= fillInCells x
43 = ImmIns ImmOpcode reg reg i |
44 RegReg RegOpcode AluOp reg reg reg |
47 deriving (Eq,Show, Read)
50 data BranchFunc = Never | Always | IfEqZero | IfNeqZero
51 deriving (Eq,Show, Read)
53 data ImmOpcode = LoadStoreImm LoadStoreOp |
58 deriving (Eq,Show, Read)
60 data RegOpcode = MOVI2S | MOVS2I |
62 deriving (Eq,Show, Read)
68 deriving (Eq,Show, Read)
72 instance Register DLXReg where
79 -- bug fix? Thu Nov 19 18:12:24 PST 1998
81 isspecpc x = SpecPC == x
83 type DLXCell a = DLX_Cell DLXReg a
84 type DLX_Trans a = Trans DLX_Op (DLXCell a)
85 type DLX_Instr a = Instr DLXReg a
87 type DLX_InstrMem a = InstrMemoryState DLX_Word (DLX_Instr a)
90 type SrcReg = DLXReg -- Source register
91 type DstReg = DLXReg -- Destination register
95 regNothing R0 = Reg R0 (Val 0)
96 regNothing reg = Reg reg NotKnown
98 dlx2trans :: Word2 i a => Instr DLXReg i -> DLX_Trans a
100 dlx2trans (ImmIns (LoadStoreImm loadOp@(Load _ _ )) dest src offset)
101 = Trans [regNothing dest] (MemOp loadOp)
102 [regNothing src,Imm (toWord offset)] []
103 -- [regNothing src,Imm (toWord offset),regNothing Dummy] []
106 dlx2trans (ImmIns (LoadStoreImm storeOp@(Store _ )) writeAddr writeReg offset)
107 = Trans [regNothing Dummy] (MemOp storeOp) [regNothing writeAddr,
109 regNothing writeReg] []
111 dlx2trans (ImmIns (ALUImm SetHi) dest _ imm)
112 = Trans [destCell] (ExecOp SetHi) [Imm (toWord imm)] []
114 destCell = regNothing dest
116 dlx2trans (ImmIns (ALUImm aluFunc) dest src imm)
117 = Trans [destCell] (ExecOp aluFunc) [srcCell,Imm (toWord imm)] []
119 destCell = regNothing dest
120 srcCell = regNothing src
122 dlx2trans (ImmIns BEQZ _ src pcOffset)
123 = Trans [pcNothing'] (CondExecOp (Add Signed) Input1) [regNothing src,
125 Imm (toWord pcOffset)]
128 dlx2trans (ImmIns BNEZ _ src pcOffset)
129 = Trans [pcNothing'] (CondExecOp Input1 (Add Signed)) [regNothing src,
131 Imm (toWord pcOffset)]
134 dlx2trans (ImmIns JR _ src _ )
135 = Trans [pcNothing'] (ExecOp Input1) [regNothing src] []
138 dlx2trans (RegReg ALU aluFunc dest src1 src2)
139 = Trans [regNothing dest] (ExecOp aluFunc) [regNothing src1, regNothing src2] []
141 dlx2trans (RegReg unknownOp _ _ _ _ )
142 = error ("Can't translate " ++ show unknownOp)
144 dlx2trans (Jmp J offset)
145 = Trans [pcNothing'] (ExecOp (Add Signed)) [pcNothing', Imm (toWord offset)] []
147 dlx2trans (ImmIns JALR _ src _ )
148 = Trans [pcNothing',regNothing R31]
149 (ParExecOp Input1 Input2)
150 [regNothing src, pcNothing'] []
152 dlx2trans (Jmp JAL offset)
153 = Trans [pcNothing',regNothing R31]
154 (ParExecOp (Add Signed) Input2)
155 [Imm (toWord offset),pcNothing']
159 dlx2trans (Jmp TRAP offset )
160 = Trans [pcNothing',regNothing IAR]
161 (ParExecOp Input1 Input2)
162 [Imm (toWord offset),pcNothing']
166 dlx2trans (Jmp RFE _ )
167 = Trans [pcNothing'] (ExecOp Input1) [regNothing IAR] []
170 -- = Trans [Reg Dummy (Val 0)] (NoOp "dlx2trans") [] []
171 = Trans [] (NoOp "dlx2trans") [] []
175 pcNothing' = Reg PC NotKnown
178 instance Show a => Probe (DLXCell a)
179 instance Probe DLXReg
181 instance Probe DLX_Op where
182 outp (ExecOp (Add _ )) = "+"
183 outp (ExecOp (Sub _ )) = "-"
184 outp (ExecOp (Div _ )) = "/"
185 outp (ExecOp (Mult _ )) = "*"
186 outp (ExecOp op) = show op
187 outp (MemOp (Load _ _)) = "Load"
188 outp (MemOp (Store _)) = "Store"
189 outp (ParExecOp op1 op2) = "PAR("++outp op1++","++outp op2 ++ ")"
193 instance Show a => Probe (DLX_Trans a) where
194 outp (Trans [] op [] i) = outp op ++ outInfo i
195 outp (Trans [x] (CondExecOp op1 op2) [c,y,z] i)
196 = outp x ++ " <- " ++ "(if0 " ++ outp c ++ " ("
197 ++ outp op1 ++ "," ++ outp op2 ++ ")) "
198 ++ outp y ++ " " ++ outp z
200 outp (Trans dummy (MemOp (Store x)) [c,y,z] i)
201 = outp (MemOp (Store x)) ++" "++ outp c ++"("++ outp y ++") <- "
202 ++ outp z ++ outInfo i
203 outp (Trans [o] op [x,y] i)
204 = outp o ++ " <- " ++ outp x ++ " " ++ outp op ++ " " ++ outp y
206 outp (Trans [] op l i) = outp op ++" "++ outList l ++ outInfo i
207 outp (Trans [o] op l i)
208 = outp o ++ " <- " ++ outp op ++" "++ outList l ++ outInfo i
209 outp (Trans l1 op l2 i)
210 = outList l1 ++" <- "++ outp op ++" "++ outList l2 ++ outInfo i
213 outInfo l = " {" ++ foldr1 (\x y -> x ++ "," ++ y) (map outp l) ++ "}"
217 outList l = "[" ++ foldr1 (\x y -> x ++ "," ++ y) (map outp l) ++ "]"