9 import qualified PreludeSig as Sig
11 import qualified TransSig as T
12 import qualified BoundedSet as Set
18 type RS i c r w = (Int,[EU i (c (VReg r) w)]) ->
19 (Signal Bool,Signal [VTrans r w]) ->
23 --rs :: (Register r,Word w) => RS StandardOp c r w
24 rs (n,execUnits) (mispredicted,input)
30 \(instrs,mispredicted,computed,rejected) ->
32 then do { Set.clear set
35 else do { Set.insert set instrs
36 ; Set.insert set rejected
37 ; broadcast' set computed
38 ; ready <- Set.rmSuch set isComputable
43 wires = bundle4 (input,mispredicted,computed,rejected)
44 (computed,rejected) = unbundle2 $ delay ([],[]) $
45 execUnit mispredicted ready
47 execUnit = schedule execUnits
49 broadcast' set computed
50 = do { s <- Set.read set
51 ; let dests = concat $ map getDst computed
52 ; Set.iterateSet set (flip fillInSrcCells dests)