1 /* -----------------------------------------------------------------------------
3 * (c) The GHC Team, 1998-1999
5 * Registers used in STG code. Might or might not correspond to
6 * actual machine registers.
8 * ---------------------------------------------------------------------------*/
13 /* This file is #included into Haskell code in the compiler: #defines
14 * only in here please.
18 * Defining NO_REGS causes no global registers to be used. NO_REGS is
19 * typically defined by GHC, via a command-line option passed to gcc,
20 * when the -funregisterised flag is given.
22 * NB. When NO_REGS is on, calling & return conventions may be
23 * different. For example, all function arguments will be passed on
24 * the stack, and components of an unboxed tuple will be returned on
25 * the stack rather than in registers.
29 /* NOTE: when testing the platform in this file we must test either
30 * *_HOST_ARCH and *_TARGET_ARCH, depending on whether COMPILING_GHC
31 * is set. This is because when we're compiling the RTS and HC code,
32 * the platform we're running on is the HOST, but when compiling GHC
33 * we want to know about the register mapping on the TARGET platform.
36 #define alpha_REGS alpha_TARGET_ARCH
37 #define hppa1_1_REGS hppa1_1_TARGET_ARCH
38 #define i386_REGS i386_TARGET_ARCH
39 #define x86_64_REGS x86_64_TARGET_ARCH
40 #define m68k_REGS m68k_TARGET_ARCH
41 #define mips_REGS (mipsel_TARGET_ARCH || mipseb_TARGET_ARCH)
42 #define powerpc_REGS (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH)
43 #define ia64_REGS ia64_TARGET_ARCH
44 #define sparc_REGS sparc_TARGET_ARCH
45 #define darwin_REGS darwin_TARGET_OS
47 #define alpha_REGS alpha_HOST_ARCH
48 #define hppa1_1_REGS hppa1_1_HOST_ARCH
49 #define i386_REGS i386_HOST_ARCH
50 #define x86_64_REGS x86_64_HOST_ARCH
51 #define m68k_REGS m68k_HOST_ARCH
52 #define mips_REGS (mipsel_HOST_ARCH || mipseb_HOST_ARCH)
53 #define powerpc_REGS (powerpc_HOST_ARCH || powerpc64_HOST_ARCH || rs6000_HOST_ARCH)
54 #define ia64_REGS ia64_HOST_ARCH
55 #define sparc_REGS sparc_HOST_ARCH
56 #define darwin_REGS darwin_HOST_OS
59 /* ----------------------------------------------------------------------------
60 Caller saves and callee-saves regs.
62 Caller-saves regs have to be saved around C-calls made from STG
63 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
64 is designated caller-saves in that machine's C calling convention.
65 -------------------------------------------------------------------------- */
67 /* -----------------------------------------------------------------------------
68 The DEC Alpha register mapping
71 \tr{$9}--\tr{$14} are our ``prize'' callee-save registers.
72 \tr{$15} is the frame pointer, and \tr{$16}--\tr{$21} are argument
73 registers. (These are off-limits.) We can steal some of the \tr{$22}-and-up
74 caller-save registers provided we do the appropriate save/restore stuff.
76 \tr{$f2}--\tr{$f9} are some callee-save floating-point registers.
78 We cannot use \tr{$23} (aka t9), \tr{$24} (aka t10), \tr{$25} (aka
79 t11), \tr{$27} (aka pv), or \tr{$28} (aka at), because they are
80 occasionally required by the assembler to handle non-primitive
81 instructions (e.g. ldb, remq). Sigh!
101 -------------------------------------------------------------------------- */
104 # define REG(x) __asm__("$" #x)
106 # define CALLER_SAVES_R2
107 # define CALLER_SAVES_R3
108 # define CALLER_SAVES_R4
109 # define CALLER_SAVES_R5
110 # define CALLER_SAVES_R6
111 # define CALLER_SAVES_R7
112 # define CALLER_SAVES_R8
114 # define CALLER_SAVES_USER
134 # define REG_SpLim 11
137 # define REG_HpLim 13
139 # define NCG_Reserved_I1 22
140 # define NCG_Reserved_I2 27
141 # define NCG_Reserved_F1 f29
142 # define NCG_Reserved_F2 f30
144 #endif /* alpha_REGS */
146 /* -----------------------------------------------------------------------------
147 The HP-PA register mapping
149 We cater for HP-PA 1.1.
151 \tr{%r0}--\tr{%r1} are special.
152 \tr{%r2} is the return pointer.
153 \tr{%r3} is the frame pointer.
154 \tr{%r4}--\tr{%r18} are callee-save registers.
155 \tr{%r19} is a linkage table register for HPUX 8.0 shared libraries.
156 \tr{%r20}--\tr{%r22} are caller-save registers.
157 \tr{%r23}--\tr{%r26} are parameter registers.
158 \tr{%r27} is a global data pointer.
159 \tr{%r28}--\tr{%r29} are temporaries.
160 \tr{%r30} is the stack pointer.
161 \tr{%r31} is a temporary.
163 \tr{%fr12}--\tr{%fr15} are some callee-save floating-point registers.
164 \tr{%fr8}--\tr{%fr11} are some available caller-save fl-pt registers.
165 -------------------------------------------------------------------------- */
169 #define REG(x) __asm__("%" #x)
185 #define REG_D1 fr20 /* L & R */
186 #define REG_D2 fr21 /* L & R */
194 #define NCG_Reserved_I1 r28
195 #define NCG_Reserved_I2 r29
196 #define NCG_Reserved_F1 fr8
197 #define NCG_Reserved_F2 fr8R
198 #define NCG_Reserved_D1 fr10
199 #define NCG_Reserved_D2 fr11
203 /* -----------------------------------------------------------------------------
204 The x86 register mapping
206 Ok, we've only got 6 general purpose registers, a frame pointer and a
207 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
208 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
209 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
218 Leaving SpLim, and HpLim out of the picture.
219 -------------------------------------------------------------------------- */
224 #define REG(x) __asm__("%" #x)
226 #ifndef not_doing_dynamic_linking
231 #ifndef STOLEN_X86_REGS
232 #define STOLEN_X86_REGS 4
235 #if STOLEN_X86_REGS >= 3
239 #if STOLEN_X86_REGS >= 4
243 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
244 #define MAX_REAL_FLOAT_REG 0
245 #define MAX_REAL_DOUBLE_REG 0
246 #define MAX_REAL_LONG_REG 0
250 /* -----------------------------------------------------------------------------
251 The x86-64 register mapping
253 %rax caller-saves, don't steal this one
255 %rcx arg reg, caller-saves
256 %rdx arg reg, caller-saves
257 %rsi arg reg, caller-saves
258 %rdi arg reg, caller-saves
259 %rbp YES (our *prime* register)
260 %rsp (unavailable - stack pointer)
261 %r8 arg reg, caller-saves
262 %r9 arg reg, caller-saves
270 %xmm0-7 arg regs, caller-saves
271 %xmm8-15 caller-saves
273 Use the caller-saves regs for Rn, because we don't always have to
274 save those (as opposed to Sp/Hp/SpLim etc. which always have to be
277 --------------------------------------------------------------------------- */
281 #define REG(x) __asm__("%" #x)
291 #define REG_SpLim r14
292 #define REG_HpLim r15
302 #define CALLER_SAVES_R2
303 #define CALLER_SAVES_R3
304 #define CALLER_SAVES_R4
305 #define CALLER_SAVES_R5
307 #define CALLER_SAVES_F1
308 #define CALLER_SAVES_F2
309 #define CALLER_SAVES_F3
310 #define CALLER_SAVES_F4
312 #define CALLER_SAVES_D1
313 #define CALLER_SAVES_D2
315 #define MAX_REAL_VANILLA_REG 5
316 #define MAX_REAL_FLOAT_REG 4
317 #define MAX_REAL_DOUBLE_REG 2
318 #define MAX_REAL_LONG_REG 0
322 /* -----------------------------------------------------------------------------
323 The Motorola 680x0 register mapping
325 A Sun3 (mc680x0) has eight address registers, \tr{a0} to \tr{a7}, and
326 eight data registers, \tr{d0} to \tr{d7}. Address operations have to
327 be done through address registers; data registers are used for
328 comparison values and data.
330 Here's the register-usage picture for m68k boxes with GCC.
333 a0 & used directly by GCC \\
334 a1 & used directly by GCC \\
336 a2..a5 & callee-saved: available for STG registers \\
337 & (a5 may be special, ``global'' register for PIC?) \\
339 a6 & C-stack frame pointer \\
340 a7 & C-stack pointer \\
342 d0 & used directly by GCC \\
343 d1 & used directly by GCC \\
344 d2 & really needed for local optimisation by GCC \\
346 d3..d7 & callee-saved: available for STG registers
348 fp0 & call-clobbered \\
349 fp1 & call-clobbered \\
350 fp2..fp7 & callee-saved: available for STG registers
352 -------------------------------------------------------------------------- */
356 #define REG(x) __asm__(#x)
368 #define MAX_REAL_VANILLA_REG 2
382 /* -----------------------------------------------------------------------------
383 The DECstation (MIPS) register mapping
385 Here's at least some simple stuff about registers on a MIPS.
387 \tr{s0}--\tr{s7} are callee-save integer registers; they are our
388 ``prize'' stolen registers. There is also a wad of callee-save
389 floating-point registers, \tr{$f20}--\tr{$f31}; we'll use some of
392 \tr{t0}--\tr{t9} are caller-save (``temporary?'') integer registers.
393 We can steal some, but we might have to save/restore around ccalls.
394 -------------------------------------------------------------------------- */
398 #define REG(x) __asm__("$" #x)
400 #define CALLER_SAVES_R1
401 #define CALLER_SAVES_R2
402 #define CALLER_SAVES_R3
403 #define CALLER_SAVES_R4
404 #define CALLER_SAVES_R5
405 #define CALLER_SAVES_R6
406 #define CALLER_SAVES_R7
407 #define CALLER_SAVES_R8
409 #define CALLER_SAVES_USER
434 #endif /* mipse[lb] */
436 /* -----------------------------------------------------------------------------
437 The PowerPC register mapping
439 0 system glue? (caller-save, volatile)
440 1 SP (callee-save, non-volatile)
441 2 AIX, powerpc64-linux:
442 RTOC (a strange special case)
444 (caller-save, volatile)
446 reserved for use by system
448 3-10 args/return (caller-save, volatile)
449 11,12 system glue? (caller-save, volatile)
450 13 on 64-bit: reserved for thread state pointer
451 on 32-bit: (callee-save, non-volatile)
452 14-31 (callee-save, non-volatile)
454 f0 (caller-save, volatile)
455 f1-f13 args/return (caller-save, volatile)
456 f14-f31 (callee-save, non-volatile)
458 \tr{14}--\tr{31} are wonderful callee-save registers on all ppc OSes.
459 \tr{0}--\tr{12} are caller-save registers.
461 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
463 We can do the Whole Business with callee-save registers only!
464 -------------------------------------------------------------------------- */
468 #define REG(x) __asm__(#x)
502 #define REG_SpLim r24
505 #define REG_HpLim r26
511 /* -----------------------------------------------------------------------------
512 The IA64 register mapping
514 We place the general registers in the locals area of the register stack,
515 so that the call mechanism takes care of saving them for us. We reserve
516 the first 16 for gcc's use - since gcc uses the highest used register to
517 determine the register stack frame size, this gives us a constant size
518 register stack frame.
520 \tr{f16-f32} are the callee-saved floating point registers.
521 -------------------------------------------------------------------------- */
525 #define REG(x) __asm__(#x)
545 #define REG_SpLim loc26
548 #define REG_HpLim loc28
552 /* -----------------------------------------------------------------------------
553 The Sun SPARC register mapping
555 The SPARC register (window) story: Remember, within the Haskell
556 Threaded World, we essentially ``shut down'' the register-window
557 mechanism---the window doesn't move at all while in this World. It
558 *does* move, of course, if we call out to arbitrary~C...
560 The %i, %l, and %o registers (8 each) are the input, local, and
561 output registers visible in one register window. The 8 %g (global)
562 registers are visible all the time.
564 %o0..%o7 not available; can be zapped by callee
565 (%o6 is C-stack ptr; %o7 hold ret addrs)
566 %i0..%i7 available (except %i6 is used as frame ptr)
567 (and %i7 tends to have ret-addr-ish things)
569 %g0..%g4 not available; prone to stomping by division, etc.
570 %g5..%g7 not available; reserved for the OS
572 Note: %g3 is *definitely* clobbered in the builtin divide code (and
573 our save/restore machinery is NOT GOOD ENOUGH for that); discretion
574 being the better part of valor, we also don't take %g4.
576 The paired nature of the floating point registers causes complications for
577 the native code generator. For convenience, we pretend that the first 22
578 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
579 float (single) regs. The NCG acts accordingly. That means that the
580 following FP assignment is rather fragile, and should only be changed
581 with extreme care. The current scheme is:
583 %f0 /%f1 FP return from C
586 %f6 /%f7 ncg double spill tmp #1
587 %f8 /%f9 ncg double spill tmp #2
588 %f10/%f11 allocatable
589 %f12/%f13 allocatable
590 %f14/%f15 allocatable
591 %f16/%f17 allocatable
592 %f18/%f19 allocatable
593 %f20/%f21 allocatable
599 %f26 ncg single spill tmp #1
600 %f27 ncg single spill tmp #2
606 -------------------------------------------------------------------------- */
610 #define REG(x) __asm__("%" #x)
612 #define CALLER_SAVES_USER
614 #define CALLER_SAVES_F1
615 #define CALLER_SAVES_F2
616 #define CALLER_SAVES_F3
617 #define CALLER_SAVES_F4
618 #define CALLER_SAVES_D1
619 #define CALLER_SAVES_D2
641 #define NCG_SpillTmp_I1 g1
642 #define NCG_SpillTmp_I2 g2
643 #define NCG_SpillTmp_F1 f26
644 #define NCG_SpillTmp_F2 f27
645 #define NCG_SpillTmp_D1 f6
646 #define NCG_SpillTmp_D2 f8
648 #define NCG_FirstFloatReg f22
654 /* -----------------------------------------------------------------------------
655 * These constants define how many stg registers will be used for
656 * passing arguments (and results, in the case of an unboxed-tuple
659 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
660 * highest STG register to occupy a real machine register, otherwise
661 * the calling conventions will needlessly shuffle data between the
662 * stack and memory-resident STG registers. We might occasionally
663 * set these macros to other values for testing, though.
665 * Registers above these values might still be used, for instance to
666 * communicate with PrimOps and RTS functions.
669 #ifndef MAX_REAL_VANILLA_REG
671 # define MAX_REAL_VANILLA_REG 8
672 # elif defined(REG_R7)
673 # define MAX_REAL_VANILLA_REG 7
674 # elif defined(REG_R6)
675 # define MAX_REAL_VANILLA_REG 6
676 # elif defined(REG_R5)
677 # define MAX_REAL_VANILLA_REG 5
678 # elif defined(REG_R4)
679 # define MAX_REAL_VANILLA_REG 4
680 # elif defined(REG_R3)
681 # define MAX_REAL_VANILLA_REG 3
682 # elif defined(REG_R2)
683 # define MAX_REAL_VANILLA_REG 2
684 # elif defined(REG_R1)
685 # define MAX_REAL_VANILLA_REG 1
687 # define MAX_REAL_VANILLA_REG 0
691 #ifndef MAX_REAL_FLOAT_REG
693 # define MAX_REAL_FLOAT_REG 4
694 # elif defined(REG_F3)
695 # define MAX_REAL_FLOAT_REG 3
696 # elif defined(REG_F2)
697 # define MAX_REAL_FLOAT_REG 2
698 # elif defined(REG_F1)
699 # define MAX_REAL_FLOAT_REG 1
701 # define MAX_REAL_FLOAT_REG 0
705 #ifndef MAX_REAL_DOUBLE_REG
707 # define MAX_REAL_DOUBLE_REG 2
708 # elif defined(REG_D1)
709 # define MAX_REAL_DOUBLE_REG 1
711 # define MAX_REAL_DOUBLE_REG 0
715 #ifndef MAX_REAL_LONG_REG
717 # define MAX_REAL_LONG_REG 1
719 # define MAX_REAL_LONG_REG 0
723 /* define NO_ARG_REGS if we have no argument registers at all (we can
724 * optimise certain code paths using this predicate).
726 #if MAX_REAL_VANILLA_REG < 2
732 #endif /* MACHREGS_H */