1 /* -----------------------------------------------------------------------------
3 * (c) The GHC Team, 1998-1999
5 * Registers used in STG code. Might or might not correspond to
6 * actual machine registers.
8 * ---------------------------------------------------------------------------*/
13 /* This file is #included into Haskell code in the compiler: #defines
14 * only in here please.
18 * Defining NO_REGS causes no global registers to be used. NO_REGS is
19 * typically defined by GHC, via a command-line option passed to gcc,
20 * when the -funregisterised flag is given.
22 * NB. When NO_REGS is on, calling & return conventions may be
23 * different. For example, all function arguments will be passed on
24 * the stack, and components of an unboxed tuple will be returned on
25 * the stack rather than in registers.
29 /* NOTE: when testing the platform in this file we must test either
30 * *_HOST_ARCH and *_TARGET_ARCH, depending on whether COMPILING_GHC
31 * is set. This is because when we're compiling the RTS and HC code,
32 * the platform we're running on is the HOST, but when compiling GHC
33 * we want to know about the register mapping on the TARGET platform.
36 #define alpha_REGS alpha_TARGET_ARCH
37 #define hppa1_1_REGS hppa1_1_TARGET_ARCH
38 #define i386_REGS i386_TARGET_ARCH
39 #define x86_64_REGS x86_64_TARGET_ARCH
40 #define m68k_REGS m68k_TARGET_ARCH
41 #define mips_REGS (mipsel_TARGET_ARCH || mipseb_TARGET_ARCH)
42 #define powerpc_REGS (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH)
43 #define ia64_REGS ia64_TARGET_ARCH
44 #define sparc_REGS sparc_TARGET_ARCH
45 #define darwin_REGS darwin_TARGET_OS
47 #define alpha_REGS alpha_HOST_ARCH
48 #define hppa1_1_REGS hppa1_1_HOST_ARCH
49 #define i386_REGS i386_HOST_ARCH
50 #define x86_64_REGS x86_64_HOST_ARCH
51 #define m68k_REGS m68k_HOST_ARCH
52 #define mips_REGS (mipsel_HOST_ARCH || mipseb_HOST_ARCH)
53 #define powerpc_REGS (powerpc_HOST_ARCH || powerpc64_HOST_ARCH || rs6000_HOST_ARCH)
54 #define ia64_REGS ia64_HOST_ARCH
55 #define sparc_REGS sparc_HOST_ARCH
56 #define darwin_REGS darwin_HOST_OS
59 /* ----------------------------------------------------------------------------
60 Caller saves and callee-saves regs.
62 Caller-saves regs have to be saved around C-calls made from STG
63 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
64 is designated caller-saves in that machine's C calling convention.
65 -------------------------------------------------------------------------- */
67 /* -----------------------------------------------------------------------------
68 The DEC Alpha register mapping
71 \tr{$9}--\tr{$14} are our ``prize'' callee-save registers.
72 \tr{$15} is the frame pointer, and \tr{$16}--\tr{$21} are argument
73 registers. (These are off-limits.) We can steal some of the \tr{$22}-and-up
74 caller-save registers provided we do the appropriate save/restore stuff.
76 \tr{$f2}--\tr{$f9} are some callee-save floating-point registers.
78 We cannot use \tr{$23} (aka t9), \tr{$24} (aka t10), \tr{$25} (aka
79 t11), \tr{$27} (aka pv), or \tr{$28} (aka at), because they are
80 occasionally required by the assembler to handle non-primitive
81 instructions (e.g. ldb, remq). Sigh!
100 -------------------------------------------------------------------------- */
103 # define REG(x) __asm__("$" #x)
105 # define CALLER_SAVES_R2
106 # define CALLER_SAVES_R3
107 # define CALLER_SAVES_R4
108 # define CALLER_SAVES_R5
109 # define CALLER_SAVES_R6
110 # define CALLER_SAVES_R7
111 # define CALLER_SAVES_R8
113 # define CALLER_SAVES_USER
133 # define REG_SpLim 11
137 # define NCG_Reserved_I1 22
138 # define NCG_Reserved_I2 27
139 # define NCG_Reserved_F1 f29
140 # define NCG_Reserved_F2 f30
142 #endif /* alpha_REGS */
144 /* -----------------------------------------------------------------------------
145 The HP-PA register mapping
147 We cater for HP-PA 1.1.
149 \tr{%r0}--\tr{%r1} are special.
150 \tr{%r2} is the return pointer.
151 \tr{%r3} is the frame pointer.
152 \tr{%r4}--\tr{%r18} are callee-save registers.
153 \tr{%r19} is a linkage table register for HPUX 8.0 shared libraries.
154 \tr{%r20}--\tr{%r22} are caller-save registers.
155 \tr{%r23}--\tr{%r26} are parameter registers.
156 \tr{%r27} is a global data pointer.
157 \tr{%r28}--\tr{%r29} are temporaries.
158 \tr{%r30} is the stack pointer.
159 \tr{%r31} is a temporary.
161 \tr{%fr12}--\tr{%fr15} are some callee-save floating-point registers.
162 \tr{%fr8}--\tr{%fr11} are some available caller-save fl-pt registers.
163 -------------------------------------------------------------------------- */
167 #define REG(x) __asm__("%" #x)
183 #define REG_D1 fr20 /* L & R */
184 #define REG_D2 fr21 /* L & R */
191 #define NCG_Reserved_I1 r28
192 #define NCG_Reserved_I2 r29
193 #define NCG_Reserved_F1 fr8
194 #define NCG_Reserved_F2 fr8R
195 #define NCG_Reserved_D1 fr10
196 #define NCG_Reserved_D2 fr11
200 /* -----------------------------------------------------------------------------
201 The x86 register mapping
203 Ok, we've only got 6 general purpose registers, a frame pointer and a
204 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
205 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
206 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
215 Leaving SpLim out of the picture.
216 -------------------------------------------------------------------------- */
221 #define REG(x) __asm__("%" #x)
223 #ifndef not_doing_dynamic_linking
228 #ifndef STOLEN_X86_REGS
229 #define STOLEN_X86_REGS 4
232 #if STOLEN_X86_REGS >= 3
236 #if STOLEN_X86_REGS >= 4
240 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
241 #define MAX_REAL_FLOAT_REG 0
242 #define MAX_REAL_DOUBLE_REG 0
243 #define MAX_REAL_LONG_REG 0
247 /* -----------------------------------------------------------------------------
248 The x86-64 register mapping
250 %rax caller-saves, don't steal this one
252 %rcx arg reg, caller-saves
253 %rdx arg reg, caller-saves
254 %rsi arg reg, caller-saves
255 %rdi arg reg, caller-saves
256 %rbp YES (our *prime* register)
257 %rsp (unavailable - stack pointer)
258 %r8 arg reg, caller-saves
259 %r9 arg reg, caller-saves
267 %xmm0-7 arg regs, caller-saves
268 %xmm8-15 caller-saves
270 Use the caller-saves regs for Rn, because we don't always have to
271 save those (as opposed to Sp/Hp/SpLim etc. which always have to be
274 --------------------------------------------------------------------------- */
278 #define REG(x) __asm__("%" #x)
289 #define REG_SpLim r15
299 #define CALLER_SAVES_R3
300 #define CALLER_SAVES_R4
301 #define CALLER_SAVES_R5
302 #define CALLER_SAVES_R6
304 #define CALLER_SAVES_F1
305 #define CALLER_SAVES_F2
306 #define CALLER_SAVES_F3
307 #define CALLER_SAVES_F4
309 #define CALLER_SAVES_D1
310 #define CALLER_SAVES_D2
312 #define MAX_REAL_VANILLA_REG 6
313 #define MAX_REAL_FLOAT_REG 4
314 #define MAX_REAL_DOUBLE_REG 2
315 #define MAX_REAL_LONG_REG 0
319 /* -----------------------------------------------------------------------------
320 The Motorola 680x0 register mapping
322 A Sun3 (mc680x0) has eight address registers, \tr{a0} to \tr{a7}, and
323 eight data registers, \tr{d0} to \tr{d7}. Address operations have to
324 be done through address registers; data registers are used for
325 comparison values and data.
327 Here's the register-usage picture for m68k boxes with GCC.
330 a0 & used directly by GCC \\
331 a1 & used directly by GCC \\
333 a2..a5 & callee-saved: available for STG registers \\
334 & (a5 may be special, ``global'' register for PIC?) \\
336 a6 & C-stack frame pointer \\
337 a7 & C-stack pointer \\
339 d0 & used directly by GCC \\
340 d1 & used directly by GCC \\
341 d2 & really needed for local optimisation by GCC \\
343 d3..d7 & callee-saved: available for STG registers
345 fp0 & call-clobbered \\
346 fp1 & call-clobbered \\
347 fp2..fp7 & callee-saved: available for STG registers
349 -------------------------------------------------------------------------- */
353 #define REG(x) __asm__(#x)
364 #define MAX_REAL_VANILLA_REG 2
378 /* -----------------------------------------------------------------------------
379 The DECstation (MIPS) register mapping
381 Here's at least some simple stuff about registers on a MIPS.
383 \tr{s0}--\tr{s7} are callee-save integer registers; they are our
384 ``prize'' stolen registers. There is also a wad of callee-save
385 floating-point registers, \tr{$f20}--\tr{$f31}; we'll use some of
388 \tr{t0}--\tr{t9} are caller-save (``temporary?'') integer registers.
389 We can steal some, but we might have to save/restore around ccalls.
390 -------------------------------------------------------------------------- */
394 #define REG(x) __asm__("$" #x)
396 #define CALLER_SAVES_R5
397 #define CALLER_SAVES_R6
398 #define CALLER_SAVES_R7
399 #define CALLER_SAVES_R8
401 #define CALLER_SAVES_USER
427 #endif /* mipse[lb] */
429 /* -----------------------------------------------------------------------------
430 The PowerPC register mapping
432 0 system glue? (caller-save, volatile)
433 1 SP (callee-save, non-volatile)
434 2 AIX, powerpc64-linux:
435 RTOC (a strange special case)
437 (caller-save, volatile)
439 reserved for use by system
441 3-10 args/return (caller-save, volatile)
442 11,12 system glue? (caller-save, volatile)
443 13 on 64-bit: reserved for thread state pointer
444 on 32-bit: (callee-save, non-volatile)
445 14-31 (callee-save, non-volatile)
447 f0 (caller-save, volatile)
448 f1-f13 args/return (caller-save, volatile)
449 f14-f31 (callee-save, non-volatile)
451 \tr{14}--\tr{31} are wonderful callee-save registers on all ppc OSes.
452 \tr{0}--\tr{12} are caller-save registers.
454 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
456 We can do the Whole Business with callee-save registers only!
457 -------------------------------------------------------------------------- */
461 #define REG(x) __asm__(#x)
495 #define REG_SpLim r24
503 /* -----------------------------------------------------------------------------
504 The IA64 register mapping
506 We place the general registers in the locals area of the register stack,
507 so that the call mechanism takes care of saving them for us. We reserve
508 the first 16 for gcc's use - since gcc uses the highest used register to
509 determine the register stack frame size, this gives us a constant size
510 register stack frame.
512 \tr{f16-f32} are the callee-saved floating point registers.
513 -------------------------------------------------------------------------- */
517 #define REG(x) __asm__(#x)
537 #define REG_SpLim loc26
543 /* -----------------------------------------------------------------------------
544 The Sun SPARC register mapping
546 The SPARC register (window) story: Remember, within the Haskell
547 Threaded World, we essentially ``shut down'' the register-window
548 mechanism---the window doesn't move at all while in this World. It
549 *does* move, of course, if we call out to arbitrary~C...
551 The %i, %l, and %o registers (8 each) are the input, local, and
552 output registers visible in one register window. The 8 %g (global)
553 registers are visible all the time.
556 scratch: volatile across C-fn calls. used by linker.
557 app: usable by application
558 system: reserved for system
560 alloc: allocated to in the register allocator, intra-closure only
562 GHC usage v8 ABI v9 ABI
565 %g1 alloc scratch scrach
568 %g4 alloc app scratch
573 Output: can be zapped by callee
574 %o0-o5 alloc caller saves
578 Local: maintained by register windowing mechanism
598 The paired nature of the floating point registers causes complications for
599 the native code generator. For convenience, we pretend that the first 22
600 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
601 float (single) regs. The NCG acts accordingly. That means that the
602 following FP assignment is rather fragile, and should only be changed
603 with extreme care. The current scheme is:
605 %f0 /%f1 FP return from C
608 %f6 /%f7 ncg double spill tmp #1
609 %f8 /%f9 ncg double spill tmp #2
610 %f10/%f11 allocatable
611 %f12/%f13 allocatable
612 %f14/%f15 allocatable
613 %f16/%f17 allocatable
614 %f18/%f19 allocatable
615 %f20/%f21 allocatable
621 %f26 ncg single spill tmp #1
622 %f27 ncg single spill tmp #2
628 -------------------------------------------------------------------------- */
632 #define REG(x) __asm__("%" #x)
634 #define CALLER_SAVES_USER
636 #define CALLER_SAVES_F1
637 #define CALLER_SAVES_F2
638 #define CALLER_SAVES_F3
639 #define CALLER_SAVES_F4
640 #define CALLER_SAVES_D1
641 #define CALLER_SAVES_D2
665 #define NCG_SpillTmp_I1 g1
666 #define NCG_SpillTmp_I2 g2
667 #define NCG_SpillTmp_F1 f26
668 #define NCG_SpillTmp_F2 f27
669 #define NCG_SpillTmp_D1 f6
670 #define NCG_SpillTmp_D2 f8
673 #define NCG_FirstFloatReg f22
679 /* -----------------------------------------------------------------------------
680 * These constants define how many stg registers will be used for
681 * passing arguments (and results, in the case of an unboxed-tuple
684 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
685 * highest STG register to occupy a real machine register, otherwise
686 * the calling conventions will needlessly shuffle data between the
687 * stack and memory-resident STG registers. We might occasionally
688 * set these macros to other values for testing, though.
690 * Registers above these values might still be used, for instance to
691 * communicate with PrimOps and RTS functions.
694 #ifndef MAX_REAL_VANILLA_REG
696 # define MAX_REAL_VANILLA_REG 8
697 # elif defined(REG_R7)
698 # define MAX_REAL_VANILLA_REG 7
699 # elif defined(REG_R6)
700 # define MAX_REAL_VANILLA_REG 6
701 # elif defined(REG_R5)
702 # define MAX_REAL_VANILLA_REG 5
703 # elif defined(REG_R4)
704 # define MAX_REAL_VANILLA_REG 4
705 # elif defined(REG_R3)
706 # define MAX_REAL_VANILLA_REG 3
707 # elif defined(REG_R2)
708 # define MAX_REAL_VANILLA_REG 2
709 # elif defined(REG_R1)
710 # define MAX_REAL_VANILLA_REG 1
712 # define MAX_REAL_VANILLA_REG 0
716 #ifndef MAX_REAL_FLOAT_REG
718 # define MAX_REAL_FLOAT_REG 4
719 # elif defined(REG_F3)
720 # define MAX_REAL_FLOAT_REG 3
721 # elif defined(REG_F2)
722 # define MAX_REAL_FLOAT_REG 2
723 # elif defined(REG_F1)
724 # define MAX_REAL_FLOAT_REG 1
726 # define MAX_REAL_FLOAT_REG 0
730 #ifndef MAX_REAL_DOUBLE_REG
732 # define MAX_REAL_DOUBLE_REG 2
733 # elif defined(REG_D1)
734 # define MAX_REAL_DOUBLE_REG 1
736 # define MAX_REAL_DOUBLE_REG 0
740 #ifndef MAX_REAL_LONG_REG
742 # define MAX_REAL_LONG_REG 1
744 # define MAX_REAL_LONG_REG 0
748 /* define NO_ARG_REGS if we have no argument registers at all (we can
749 * optimise certain code paths using this predicate).
751 #if MAX_REAL_VANILLA_REG < 2
757 #endif /* MACHREGS_H */