1 /* ----------------------------------------------------------------------------
3 * (c) The GHC Team, 2005-2008
5 * Macros for multi-CPU support
7 * -------------------------------------------------------------------------- */
12 /* THREADED_RTS is currently not compatible with the following options:
14 * PROFILING (but only 1 CPU supported)
16 * Unregisterised builds are ok, but only 1 CPU supported.
19 #if defined(THREADED_RTS)
21 #if defined(TICKY_TICKY)
22 #error Build options incompatible with THREADED_RTS.
25 /* ----------------------------------------------------------------------------
27 ------------------------------------------------------------------------- */
30 // We only want write_barrier() declared in .hc files. Defining the
31 // other inline functions here causes type mismatch errors from gcc,
32 // because the generated C code is assuming that there are no
33 // prototypes in scope.
36 * The atomic exchange operation: xchg(p,w) exchanges the value
37 * pointed to by p with the value w, returning the old value.
39 * Used for locking closures during updates (see lockClosure() below)
40 * and the MVar primops.
42 EXTERN_INLINE StgWord xchg(StgPtr p, StgWord w);
45 * Compare-and-swap. Atomically does this:
49 * if (r == o) { *p = n };
53 EXTERN_INLINE StgWord cas(StgVolatilePtr p, StgWord o, StgWord n);
55 #endif // !IN_STG_CODE
58 * Prevents write operations from moving across this call in either
61 EXTERN_INLINE void write_barrier(void);
64 * Prevents loads from moving before earlier stores.
66 EXTERN_INLINE void store_load_barrier(void);
68 /* ----------------------------------------------------------------------------
70 ------------------------------------------------------------------------- */
75 * NB: the xchg instruction is implicitly locked, so we do not need
79 xchg(StgPtr p, StgWord w)
82 #if i386_HOST_ARCH || x86_64_HOST_ARCH
84 __asm__ __volatile__ (
86 :"+r" (result), "+m" (*p)
87 : /* no input-only operands */
89 #elif powerpc_HOST_ARCH
90 __asm__ __volatile__ (
91 "1: lwarx %0, 0, %2\n"
99 __asm__ __volatile__ (
101 : "+r" (result), "+m" (*p)
102 : /* no input-only operands */
104 #elif !defined(WITHSMP)
108 #error xchg() unimplemented on this architecture
114 * CMPXCHG - the single-word atomic compare-and-exchange instruction. Used
115 * in the STM implementation.
117 EXTERN_INLINE StgWord
118 cas(StgVolatilePtr p, StgWord o, StgWord n)
120 #if i386_HOST_ARCH || x86_64_HOST_ARCH
121 __asm__ __volatile__ (
122 "lock\ncmpxchg %3,%1"
123 :"=a"(o), "=m" (*(volatile unsigned int *)p)
126 #elif powerpc_HOST_ARCH
128 __asm__ __volatile__ (
129 "1: lwarx %0, 0, %3\n"
132 " stwcx. %2, 0, %3\n"
136 :"r" (o), "r" (n), "r" (p)
140 #elif sparc_HOST_ARCH
141 __asm__ __volatile__ (
148 #elif !defined(WITHSMP)
156 #error cas() unimplemented on this architecture
160 #endif // !IN_STG_CODE
163 * Write barrier - ensure that all preceding writes have happened
164 * before all following writes.
166 * We need to tell both the compiler AND the CPU about the barrier.
167 * This is a brute force solution; better results might be obtained by
168 * using volatile type declarations to get fine-grained ordering
169 * control in C, and optionally a memory barrier instruction on CPUs
170 * that require it (not x86 or x86_64).
173 write_barrier(void) {
174 #if i386_HOST_ARCH || x86_64_HOST_ARCH
175 __asm__ __volatile__ ("" : : : "memory");
176 #elif powerpc_HOST_ARCH
177 __asm__ __volatile__ ("lwsync" : : : "memory");
178 #elif sparc_HOST_ARCH
179 /* Sparc in TSO mode does not require write/write barriers. */
180 __asm__ __volatile__ ("" : : : "memory");
181 #elif !defined(WITHSMP)
184 #error memory barriers unimplemented on this architecture
189 store_load_barrier(void) {
191 __asm__ __volatile__ ("lock; addl $0,0(%%esp)" : : : "memory");
192 #elif x86_64_HOST_ARCH
193 __asm__ __volatile__ ("lock; addq $0,0(%%rsp)" : : : "memory");
194 #elif powerpc_HOST_ARCH
195 __asm__ __volatile__ ("msync" : : : "memory");
196 #elif sparc_HOST_ARCH
197 /* Sparc in TSO mode does not require write/write barriers. */
198 __asm__ __volatile__ ("membar" : : : "memory");
199 #elif !defined(WITHSMP)
202 #error memory barriers unimplemented on this architecture
206 /* ---------------------------------------------------------------------- */
207 #else /* !THREADED_RTS */
209 #define write_barrier() /* nothing */
211 #define store_load_barrier() /* nothing */
213 INLINE_HEADER StgWord
214 xchg(StgPtr p, StgWord w)
221 STATIC_INLINE StgWord
222 cas(StgVolatilePtr p, StgWord o, StgWord n)
232 #endif /* !THREADED_RTS */