1 /* ----------------------------------------------------------------------------
3 * (c) The GHC Team, 2005
5 * Macros for THREADED_RTS support
7 * -------------------------------------------------------------------------- */
12 /* THREADED_RTS is currently not compatible with the following options:
14 * PROFILING (but only 1 CPU supported)
16 * Unregisterised builds are ok, but only 1 CPU supported.
19 #if defined(THREADED_RTS)
21 #if defined(TICKY_TICKY)
22 #error Build options incompatible with THREADED_RTS.
26 * XCHG - the atomic exchange instruction. Used for locking closures
27 * during updates (see lockClosure() below) and the MVar primops.
29 * NB: the xchg instruction is implicitly locked, so we do not need
33 xchg(StgPtr p, StgWord w)
36 #if i386_HOST_ARCH || x86_64_HOST_ARCH
38 __asm__ __volatile__ (
40 :"+r" (result), "+m" (*p)
41 : /* no input-only operands */
43 #elif powerpc_HOST_ARCH
44 __asm__ __volatile__ (
45 "1: lwarx %0, 0, %2\n"
52 #error xchg() unimplemented on this architecture
58 * CMPXCHG - the single-word atomic compare-and-exchange instruction. Used
59 * in the STM implementation.
62 cas(StgVolatilePtr p, StgWord o, StgWord n)
64 #if i386_HOST_ARCH || x86_64_HOST_ARCH
65 __asm__ __volatile__ (
67 :"=a"(o), "=m" (*(volatile unsigned int *)p)
70 #elif powerpc_HOST_ARCH
72 __asm__ __volatile__ (
73 "1: lwarx %0, 0, %3\n"
80 :"r" (o), "r" (n), "r" (p)
84 #error cas() unimplemented on this architecture
89 * Write barrier - ensure that all preceding writes have happened
90 * before all following writes.
92 * We need to tell both the compiler AND the CPU about the barrier.
93 * This is a brute force solution; better results might be obtained by
94 * using volatile type declarations to get fine-grained ordering
95 * control in C, and optionally a memory barrier instruction on CPUs
96 * that require it (not x86 or x86_64).
100 #if i386_HOST_ARCH || x86_64_HOST_ARCH
101 __asm__ __volatile__ ("" : : : "memory");
102 #elif powerpc_HOST_ARCH
103 __asm__ __volatile__ ("lwsync" : : : "memory");
105 #error memory barriers unimplemented on this architecture
110 * Locking/unlocking closures
112 * This is used primarily in the implementation of MVars.
114 #define SPIN_COUNT 4000
116 INLINE_HEADER StgInfoTable *
117 lockClosure(StgClosure *p)
119 #if i386_HOST_ARCH || x86_64_HOST_ARCH || powerpc_HOST_ARCH
124 info = xchg((P_)(void *)&p->header.info, (W_)&stg_WHITEHOLE_info);
125 if (info != (W_)&stg_WHITEHOLE_info) return (StgInfoTable *)info;
126 } while (++i < SPIN_COUNT);
135 unlockClosure(StgClosure *p, StgInfoTable *info)
137 #if i386_HOST_ARCH || x86_64_HOST_ARCH || powerpc_HOST_ARCH
138 // This is a strictly ordered write, so we need a wb():
140 p->header.info = info;
146 #else /* !THREADED_RTS */
148 #define wb() /* nothing */
150 INLINE_HEADER StgWord
151 xchg(StgPtr p, StgWord w)
158 #endif /* !THREADED_RTS */