1 /* ----------------------------------------------------------------------------
3 * (c) The GHC Team, 2005
5 * Macros for THREADED_RTS support
7 * -------------------------------------------------------------------------- */
12 /* THREADED_RTS is currently not compatible with the following options:
14 * PROFILING (but only 1 CPU supported)
16 * Unregisterised builds are ok, but only 1 CPU supported.
19 #if defined(THREADED_RTS)
21 #if defined(TICKY_TICKY)
22 #error Build options incompatible with THREADED_RTS.
26 * XCHG - the atomic exchange instruction. Used for locking closures
27 * during updates (see lockClosure() below) and the MVar primops.
29 * NB: the xchg instruction is implicitly locked, so we do not need
33 xchg(StgPtr p, StgWord w)
36 #if i386_HOST_ARCH || x86_64_HOST_ARCH
38 __asm__ __volatile__ (
40 :"+r" (result), "+m" (*p)
41 : /* no input-only operands */
43 #elif powerpc_HOST_ARCH
44 __asm__ __volatile__ (
45 "1: lwarx %0, 0, %2\n"
53 __asm__ __volatile__ (
55 : "+r" (result), "+m" (*p)
56 : /* no input-only operands */
58 #elif !defined(WITHSMP)
62 #error xchg() unimplemented on this architecture
68 * CMPXCHG - the single-word atomic compare-and-exchange instruction. Used
69 * in the STM implementation.
72 cas(StgVolatilePtr p, StgWord o, StgWord n)
74 #if i386_HOST_ARCH || x86_64_HOST_ARCH
75 __asm__ __volatile__ (
77 :"=a"(o), "=m" (*(volatile unsigned int *)p)
80 #elif powerpc_HOST_ARCH
82 __asm__ __volatile__ (
83 "1: lwarx %0, 0, %3\n"
90 :"r" (o), "r" (n), "r" (p)
95 __asm__ __volatile__ (
102 #elif !defined(WITHSMP)
110 #error cas() unimplemented on this architecture
115 * Write barrier - ensure that all preceding writes have happened
116 * before all following writes.
118 * We need to tell both the compiler AND the CPU about the barrier.
119 * This is a brute force solution; better results might be obtained by
120 * using volatile type declarations to get fine-grained ordering
121 * control in C, and optionally a memory barrier instruction on CPUs
122 * that require it (not x86 or x86_64).
125 write_barrier(void) {
126 #if i386_HOST_ARCH || x86_64_HOST_ARCH
127 __asm__ __volatile__ ("" : : : "memory");
128 #elif powerpc_HOST_ARCH
129 __asm__ __volatile__ ("lwsync" : : : "memory");
130 #elif sparc_HOST_ARCH
131 /* Sparc in TSO mode does not require write/write barriers. */
132 __asm__ __volatile__ ("" : : : "memory");
133 #elif !defined(WITHSMP)
136 #error memory barriers unimplemented on this architecture
141 * Locking/unlocking closures
143 * This is used primarily in the implementation of MVars.
145 #define SPIN_COUNT 4000
147 INLINE_HEADER StgInfoTable *
148 lockClosure(StgClosure *p)
154 info = xchg((P_)(void *)&p->header.info, (W_)&stg_WHITEHOLE_info);
155 if (info != (W_)&stg_WHITEHOLE_info) return (StgInfoTable *)info;
156 } while (++i < SPIN_COUNT);
162 unlockClosure(StgClosure *p, StgInfoTable *info)
164 // This is a strictly ordered write, so we need a wb():
166 p->header.info = info;
169 #else /* !THREADED_RTS */
171 #define write_barrier() /* nothing */
173 INLINE_HEADER StgWord
174 xchg(StgPtr p, StgWord w)
181 INLINE_HEADER StgInfoTable *
182 lockClosure(StgClosure *p)
183 { return (StgInfoTable *)p->header.info; }
186 unlockClosure(StgClosure *p STG_UNUSED, StgInfoTable *info STG_UNUSED)
189 #endif /* !THREADED_RTS */
191 // Handy specialised versions of lockClosure()/unlockClosure()
192 INLINE_HEADER void lockTSO(StgTSO *tso)
193 { lockClosure((StgClosure *)tso); }
195 INLINE_HEADER void unlockTSO(StgTSO *tso)
196 { unlockClosure((StgClosure*)tso, (StgInfoTable*)&stg_TSO_info); }