1 /* -----------------------------------------------------------------------------
3 * (c) The GHC Team, 1998-2009
5 * Registers used in STG code. Might or might not correspond to
6 * actual machine registers.
8 * Do not #include this file directly: #include "Rts.h" instead.
10 * To understand the structure of the RTS headers, see the wiki:
11 * http://hackage.haskell.org/trac/ghc/wiki/Commentary/SourceTree/Includes
13 * ---------------------------------------------------------------------------*/
18 /* This file is #included into Haskell code in the compiler: #defines
19 * only in here please.
23 * Defining NO_REGS causes no global registers to be used. NO_REGS is
24 * typically defined by GHC, via a command-line option passed to gcc,
25 * when the -funregisterised flag is given.
27 * NB. When NO_REGS is on, calling & return conventions may be
28 * different. For example, all function arguments will be passed on
29 * the stack, and components of an unboxed tuple will be returned on
30 * the stack rather than in registers.
34 /* NOTE: when testing the platform in this file we must test either
35 * *_HOST_ARCH and *_TARGET_ARCH, depending on whether COMPILING_GHC
36 * is set. This is because when we're compiling the RTS and HC code,
37 * the platform we're running on is the HOST, but when compiling GHC
38 * we want to know about the register mapping on the TARGET platform.
41 #define alpha_REGS alpha_TARGET_ARCH
42 #define hppa1_1_REGS hppa1_1_TARGET_ARCH
43 #define i386_REGS i386_TARGET_ARCH
44 #define x86_64_REGS x86_64_TARGET_ARCH
45 #define m68k_REGS m68k_TARGET_ARCH
46 #define mips_REGS (mipsel_TARGET_ARCH || mipseb_TARGET_ARCH)
47 #define powerpc_REGS (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH)
48 #define ia64_REGS ia64_TARGET_ARCH
49 #define sparc_REGS sparc_TARGET_ARCH
50 #define darwin_REGS darwin_TARGET_OS
52 #define alpha_REGS alpha_HOST_ARCH
53 #define hppa1_1_REGS hppa1_1_HOST_ARCH
54 #define i386_REGS i386_HOST_ARCH
55 #define x86_64_REGS x86_64_HOST_ARCH
56 #define m68k_REGS m68k_HOST_ARCH
57 #define mips_REGS (mipsel_HOST_ARCH || mipseb_HOST_ARCH)
58 #define powerpc_REGS (powerpc_HOST_ARCH || powerpc64_HOST_ARCH || rs6000_HOST_ARCH)
59 #define ia64_REGS ia64_HOST_ARCH
60 #define sparc_REGS sparc_HOST_ARCH
61 #define darwin_REGS darwin_HOST_OS
64 /* ----------------------------------------------------------------------------
65 Caller saves and callee-saves regs.
67 Caller-saves regs have to be saved around C-calls made from STG
68 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
69 is designated caller-saves in that machine's C calling convention.
71 As it stands, the only registers that are ever marked caller saves
72 are the RX, FX, DX and USER registers; as a result, if you
73 decide to caller save a system register (e.g. SP, HP, etc), note that
74 this code path is completely untested! -- EZY
75 -------------------------------------------------------------------------- */
77 /* -----------------------------------------------------------------------------
78 The DEC Alpha register mapping
81 \tr{$9}--\tr{$14} are our ``prize'' callee-save registers.
82 \tr{$15} is the frame pointer, and \tr{$16}--\tr{$21} are argument
83 registers. (These are off-limits.) We can steal some of the \tr{$22}-and-up
84 caller-save registers provided we do the appropriate save/restore stuff.
86 \tr{$f2}--\tr{$f9} are some callee-save floating-point registers.
88 We cannot use \tr{$23} (aka t9), \tr{$24} (aka t10), \tr{$25} (aka
89 t11), \tr{$27} (aka pv), or \tr{$28} (aka at), because they are
90 occasionally required by the assembler to handle non-primitive
91 instructions (e.g. ldb, remq). Sigh!
110 -------------------------------------------------------------------------- */
113 # define REG(x) __asm__("$" #x)
115 # define CALLER_SAVES_R2
116 # define CALLER_SAVES_R3
117 # define CALLER_SAVES_R4
118 # define CALLER_SAVES_R5
119 # define CALLER_SAVES_R6
120 # define CALLER_SAVES_R7
121 # define CALLER_SAVES_R8
123 # define CALLER_SAVES_USER
143 # define REG_SpLim 11
147 # define NCG_Reserved_I1 22
148 # define NCG_Reserved_I2 27
149 # define NCG_Reserved_F1 f29
150 # define NCG_Reserved_F2 f30
152 #endif /* alpha_REGS */
154 /* -----------------------------------------------------------------------------
155 The HP-PA register mapping
157 We cater for HP-PA 1.1.
159 \tr{%r0}--\tr{%r1} are special.
160 \tr{%r2} is the return pointer.
161 \tr{%r3} is the frame pointer.
162 \tr{%r4}--\tr{%r18} are callee-save registers.
163 \tr{%r19} is a linkage table register for HPUX 8.0 shared libraries.
164 \tr{%r20}--\tr{%r22} are caller-save registers.
165 \tr{%r23}--\tr{%r26} are parameter registers.
166 \tr{%r27} is a global data pointer.
167 \tr{%r28}--\tr{%r29} are temporaries.
168 \tr{%r30} is the stack pointer.
169 \tr{%r31} is a temporary.
171 \tr{%fr12}--\tr{%fr15} are some callee-save floating-point registers.
172 \tr{%fr8}--\tr{%fr11} are some available caller-save fl-pt registers.
173 -------------------------------------------------------------------------- */
177 #define REG(x) __asm__("%" #x)
193 #define REG_D1 fr20 /* L & R */
194 #define REG_D2 fr21 /* L & R */
201 #define NCG_Reserved_I1 r28
202 #define NCG_Reserved_I2 r29
203 #define NCG_Reserved_F1 fr8
204 #define NCG_Reserved_F2 fr8R
205 #define NCG_Reserved_D1 fr10
206 #define NCG_Reserved_D2 fr11
210 /* -----------------------------------------------------------------------------
211 The x86 register mapping
213 Ok, we've only got 6 general purpose registers, a frame pointer and a
214 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
215 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
216 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
225 Leaving SpLim out of the picture.
226 -------------------------------------------------------------------------- */
231 #define REG(x) __asm__("%" #x)
233 #ifndef not_doing_dynamic_linking
238 #ifndef STOLEN_X86_REGS
239 #define STOLEN_X86_REGS 4
242 #if STOLEN_X86_REGS >= 3
246 #if STOLEN_X86_REGS >= 4
250 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
251 #define MAX_REAL_FLOAT_REG 0
252 #define MAX_REAL_DOUBLE_REG 0
253 #define MAX_REAL_LONG_REG 0
257 /* -----------------------------------------------------------------------------
258 The x86-64 register mapping
260 %rax caller-saves, don't steal this one
262 %rcx arg reg, caller-saves
263 %rdx arg reg, caller-saves
264 %rsi arg reg, caller-saves
265 %rdi arg reg, caller-saves
266 %rbp YES (our *prime* register)
267 %rsp (unavailable - stack pointer)
268 %r8 arg reg, caller-saves
269 %r9 arg reg, caller-saves
277 %xmm0-7 arg regs, caller-saves
278 %xmm8-15 caller-saves
280 Use the caller-saves regs for Rn, because we don't always have to
281 save those (as opposed to Sp/Hp/SpLim etc. which always have to be
284 --------------------------------------------------------------------------- */
288 #define REG(x) __asm__("%" #x)
299 #define REG_SpLim r15
309 #define CALLER_SAVES_R3
310 #define CALLER_SAVES_R4
311 #define CALLER_SAVES_R5
312 #define CALLER_SAVES_R6
314 #define CALLER_SAVES_F1
315 #define CALLER_SAVES_F2
316 #define CALLER_SAVES_F3
317 #define CALLER_SAVES_F4
319 #define CALLER_SAVES_D1
320 #define CALLER_SAVES_D2
322 #define MAX_REAL_VANILLA_REG 6
323 #define MAX_REAL_FLOAT_REG 4
324 #define MAX_REAL_DOUBLE_REG 2
325 #define MAX_REAL_LONG_REG 0
329 /* -----------------------------------------------------------------------------
330 The Motorola 680x0 register mapping
332 A Sun3 (mc680x0) has eight address registers, \tr{a0} to \tr{a7}, and
333 eight data registers, \tr{d0} to \tr{d7}. Address operations have to
334 be done through address registers; data registers are used for
335 comparison values and data.
337 Here's the register-usage picture for m68k boxes with GCC.
340 a0 & used directly by GCC \\
341 a1 & used directly by GCC \\
343 a2..a5 & callee-saved: available for STG registers \\
344 & (a5 may be special, ``global'' register for PIC?) \\
346 a6 & C-stack frame pointer \\
347 a7 & C-stack pointer \\
349 d0 & used directly by GCC \\
350 d1 & used directly by GCC \\
351 d2 & really needed for local optimisation by GCC \\
353 d3..d7 & callee-saved: available for STG registers
355 fp0 & call-clobbered \\
356 fp1 & call-clobbered \\
357 fp2..fp7 & callee-saved: available for STG registers
359 -------------------------------------------------------------------------- */
363 #define REG(x) __asm__(#x)
374 #define MAX_REAL_VANILLA_REG 2
388 /* -----------------------------------------------------------------------------
389 The DECstation (MIPS) register mapping
391 Here's at least some simple stuff about registers on a MIPS.
393 \tr{s0}--\tr{s7} are callee-save integer registers; they are our
394 ``prize'' stolen registers. There is also a wad of callee-save
395 floating-point registers, \tr{$f20}--\tr{$f31}; we'll use some of
398 \tr{t0}--\tr{t9} are caller-save (``temporary?'') integer registers.
399 We can steal some, but we might have to save/restore around ccalls.
400 -------------------------------------------------------------------------- */
404 #define REG(x) __asm__("$" #x)
406 #define CALLER_SAVES_R5
407 #define CALLER_SAVES_R6
408 #define CALLER_SAVES_R7
409 #define CALLER_SAVES_R8
411 #define CALLER_SAVES_USER
437 #endif /* mipse[lb] */
439 /* -----------------------------------------------------------------------------
440 The PowerPC register mapping
442 0 system glue? (caller-save, volatile)
443 1 SP (callee-save, non-volatile)
444 2 AIX, powerpc64-linux:
445 RTOC (a strange special case)
447 (caller-save, volatile)
449 reserved for use by system
451 3-10 args/return (caller-save, volatile)
452 11,12 system glue? (caller-save, volatile)
453 13 on 64-bit: reserved for thread state pointer
454 on 32-bit: (callee-save, non-volatile)
455 14-31 (callee-save, non-volatile)
457 f0 (caller-save, volatile)
458 f1-f13 args/return (caller-save, volatile)
459 f14-f31 (callee-save, non-volatile)
461 \tr{14}--\tr{31} are wonderful callee-save registers on all ppc OSes.
462 \tr{0}--\tr{12} are caller-save registers.
464 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
466 We can do the Whole Business with callee-save registers only!
467 -------------------------------------------------------------------------- */
471 #define REG(x) __asm__(#x)
505 #define REG_SpLim r24
513 /* -----------------------------------------------------------------------------
514 The IA64 register mapping
516 We place the general registers in the locals area of the register stack,
517 so that the call mechanism takes care of saving them for us. We reserve
518 the first 16 for gcc's use - since gcc uses the highest used register to
519 determine the register stack frame size, this gives us a constant size
520 register stack frame.
522 \tr{f16-f32} are the callee-saved floating point registers.
523 -------------------------------------------------------------------------- */
527 #define REG(x) __asm__(#x)
547 #define REG_SpLim loc26
553 /* -----------------------------------------------------------------------------
554 The Sun SPARC register mapping
556 !! IMPORTANT: if you change this register mapping you must also update
557 compiler/nativeGen/SPARC/Regs.hs. That file handles the
558 mapping for the NCG. This one only affects via-c code.
560 The SPARC register (window) story: Remember, within the Haskell
561 Threaded World, we essentially ``shut down'' the register-window
562 mechanism---the window doesn't move at all while in this World. It
563 *does* move, of course, if we call out to arbitrary~C...
565 The %i, %l, and %o registers (8 each) are the input, local, and
566 output registers visible in one register window. The 8 %g (global)
567 registers are visible all the time.
570 scratch: volatile across C-fn calls. used by linker.
571 app: usable by application
572 system: reserved for system
574 alloc: allocated to in the register allocator, intra-closure only
576 GHC usage v8 ABI v9 ABI
579 %g1 alloc scratch scrach
582 %g4 alloc app scratch
587 Output: can be zapped by callee
588 %o0-o5 alloc caller saves
592 Local: maintained by register windowing mechanism
612 The paired nature of the floating point registers causes complications for
613 the native code generator. For convenience, we pretend that the first 22
614 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
615 float (single) regs. The NCG acts accordingly. That means that the
616 following FP assignment is rather fragile, and should only be changed
617 with extreme care. The current scheme is:
619 %f0 /%f1 FP return from C
622 %f6 /%f7 ncg double spill tmp #1
623 %f8 /%f9 ncg double spill tmp #2
624 %f10/%f11 allocatable
625 %f12/%f13 allocatable
626 %f14/%f15 allocatable
627 %f16/%f17 allocatable
628 %f18/%f19 allocatable
629 %f20/%f21 allocatable
635 %f26 ncg single spill tmp #1
636 %f27 ncg single spill tmp #2
642 -------------------------------------------------------------------------- */
646 #define REG(x) __asm__("%" #x)
648 #define CALLER_SAVES_USER
650 #define CALLER_SAVES_F1
651 #define CALLER_SAVES_F2
652 #define CALLER_SAVES_F3
653 #define CALLER_SAVES_F4
654 #define CALLER_SAVES_D1
655 #define CALLER_SAVES_D2
669 /* for each of the double arg regs,
670 Dn_2 is the high half. */
686 #define NCG_SpillTmp_I1 g1
687 #define NCG_SpillTmp_I2 g2
688 #define NCG_SpillTmp_F1 f26
689 #define NCG_SpillTmp_F2 f27
690 #define NCG_SpillTmp_D1 f6
691 #define NCG_SpillTmp_D2 f8
694 #define NCG_FirstFloatReg f22
700 /* -----------------------------------------------------------------------------
701 * These constants define how many stg registers will be used for
702 * passing arguments (and results, in the case of an unboxed-tuple
705 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
706 * highest STG register to occupy a real machine register, otherwise
707 * the calling conventions will needlessly shuffle data between the
708 * stack and memory-resident STG registers. We might occasionally
709 * set these macros to other values for testing, though.
711 * Registers above these values might still be used, for instance to
712 * communicate with PrimOps and RTS functions.
715 #ifndef MAX_REAL_VANILLA_REG
717 # define MAX_REAL_VANILLA_REG 8
718 # elif defined(REG_R7)
719 # define MAX_REAL_VANILLA_REG 7
720 # elif defined(REG_R6)
721 # define MAX_REAL_VANILLA_REG 6
722 # elif defined(REG_R5)
723 # define MAX_REAL_VANILLA_REG 5
724 # elif defined(REG_R4)
725 # define MAX_REAL_VANILLA_REG 4
726 # elif defined(REG_R3)
727 # define MAX_REAL_VANILLA_REG 3
728 # elif defined(REG_R2)
729 # define MAX_REAL_VANILLA_REG 2
730 # elif defined(REG_R1)
731 # define MAX_REAL_VANILLA_REG 1
733 # define MAX_REAL_VANILLA_REG 0
737 #ifndef MAX_REAL_FLOAT_REG
739 # define MAX_REAL_FLOAT_REG 4
740 # elif defined(REG_F3)
741 # define MAX_REAL_FLOAT_REG 3
742 # elif defined(REG_F2)
743 # define MAX_REAL_FLOAT_REG 2
744 # elif defined(REG_F1)
745 # define MAX_REAL_FLOAT_REG 1
747 # define MAX_REAL_FLOAT_REG 0
751 #ifndef MAX_REAL_DOUBLE_REG
753 # define MAX_REAL_DOUBLE_REG 2
754 # elif defined(REG_D1)
755 # define MAX_REAL_DOUBLE_REG 1
757 # define MAX_REAL_DOUBLE_REG 0
761 #ifndef MAX_REAL_LONG_REG
763 # define MAX_REAL_LONG_REG 1
765 # define MAX_REAL_LONG_REG 0
769 /* define NO_ARG_REGS if we have no argument registers at all (we can
770 * optimise certain code paths using this predicate).
772 #if MAX_REAL_VANILLA_REG < 2
778 #endif /* MACHREGS_H */