1 /* -----------------------------------------------------------------------------
3 * (c) The GHC Team, 1998-2009
5 * Registers used in STG code. Might or might not correspond to
6 * actual machine registers.
8 * Do not #include this file directly: #include "Rts.h" instead.
10 * To understand the structure of the RTS headers, see the wiki:
11 * http://hackage.haskell.org/trac/ghc/wiki/Commentary/SourceTree/Includes
13 * ---------------------------------------------------------------------------*/
18 /* This file is #included into Haskell code in the compiler: #defines
19 * only in here please.
23 * Defining NO_REGS causes no global registers to be used. NO_REGS is
24 * typically defined by GHC, via a command-line option passed to gcc,
25 * when the -funregisterised flag is given.
27 * NB. When NO_REGS is on, calling & return conventions may be
28 * different. For example, all function arguments will be passed on
29 * the stack, and components of an unboxed tuple will be returned on
30 * the stack rather than in registers.
34 /* NOTE: when testing the platform in this file we must test either
35 * *_HOST_ARCH and *_TARGET_ARCH, depending on whether COMPILING_GHC
36 * is set. This is because when we're compiling the RTS and HC code,
37 * the platform we're running on is the HOST, but when compiling GHC
38 * we want to know about the register mapping on the TARGET platform.
41 #define alpha_REGS alpha_TARGET_ARCH
42 #define hppa1_1_REGS hppa1_1_TARGET_ARCH
43 #define i386_REGS i386_TARGET_ARCH
44 #define x86_64_REGS x86_64_TARGET_ARCH
45 #define m68k_REGS m68k_TARGET_ARCH
46 #define mips_REGS (mipsel_TARGET_ARCH || mipseb_TARGET_ARCH)
47 #define powerpc_REGS (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH)
48 #define ia64_REGS ia64_TARGET_ARCH
49 #define sparc_REGS sparc_TARGET_ARCH
50 #define darwin_REGS darwin_TARGET_OS
52 #define alpha_REGS alpha_HOST_ARCH
53 #define hppa1_1_REGS hppa1_1_HOST_ARCH
54 #define i386_REGS i386_HOST_ARCH
55 #define x86_64_REGS x86_64_HOST_ARCH
56 #define m68k_REGS m68k_HOST_ARCH
57 #define mips_REGS (mipsel_HOST_ARCH || mipseb_HOST_ARCH)
58 #define powerpc_REGS (powerpc_HOST_ARCH || powerpc64_HOST_ARCH || rs6000_HOST_ARCH)
59 #define ia64_REGS ia64_HOST_ARCH
60 #define sparc_REGS sparc_HOST_ARCH
61 #define darwin_REGS darwin_HOST_OS
64 /* ----------------------------------------------------------------------------
65 Caller saves and callee-saves regs.
67 Caller-saves regs have to be saved around C-calls made from STG
68 land, so this file defines CALLER_SAVES_<reg> for each <reg> that
69 is designated caller-saves in that machine's C calling convention.
70 -------------------------------------------------------------------------- */
72 /* -----------------------------------------------------------------------------
73 The DEC Alpha register mapping
76 \tr{$9}--\tr{$14} are our ``prize'' callee-save registers.
77 \tr{$15} is the frame pointer, and \tr{$16}--\tr{$21} are argument
78 registers. (These are off-limits.) We can steal some of the \tr{$22}-and-up
79 caller-save registers provided we do the appropriate save/restore stuff.
81 \tr{$f2}--\tr{$f9} are some callee-save floating-point registers.
83 We cannot use \tr{$23} (aka t9), \tr{$24} (aka t10), \tr{$25} (aka
84 t11), \tr{$27} (aka pv), or \tr{$28} (aka at), because they are
85 occasionally required by the assembler to handle non-primitive
86 instructions (e.g. ldb, remq). Sigh!
105 -------------------------------------------------------------------------- */
108 # define REG(x) __asm__("$" #x)
110 # define CALLER_SAVES_R2
111 # define CALLER_SAVES_R3
112 # define CALLER_SAVES_R4
113 # define CALLER_SAVES_R5
114 # define CALLER_SAVES_R6
115 # define CALLER_SAVES_R7
116 # define CALLER_SAVES_R8
118 # define CALLER_SAVES_USER
138 # define REG_SpLim 11
142 # define NCG_Reserved_I1 22
143 # define NCG_Reserved_I2 27
144 # define NCG_Reserved_F1 f29
145 # define NCG_Reserved_F2 f30
147 #endif /* alpha_REGS */
149 /* -----------------------------------------------------------------------------
150 The HP-PA register mapping
152 We cater for HP-PA 1.1.
154 \tr{%r0}--\tr{%r1} are special.
155 \tr{%r2} is the return pointer.
156 \tr{%r3} is the frame pointer.
157 \tr{%r4}--\tr{%r18} are callee-save registers.
158 \tr{%r19} is a linkage table register for HPUX 8.0 shared libraries.
159 \tr{%r20}--\tr{%r22} are caller-save registers.
160 \tr{%r23}--\tr{%r26} are parameter registers.
161 \tr{%r27} is a global data pointer.
162 \tr{%r28}--\tr{%r29} are temporaries.
163 \tr{%r30} is the stack pointer.
164 \tr{%r31} is a temporary.
166 \tr{%fr12}--\tr{%fr15} are some callee-save floating-point registers.
167 \tr{%fr8}--\tr{%fr11} are some available caller-save fl-pt registers.
168 -------------------------------------------------------------------------- */
172 #define REG(x) __asm__("%" #x)
188 #define REG_D1 fr20 /* L & R */
189 #define REG_D2 fr21 /* L & R */
196 #define NCG_Reserved_I1 r28
197 #define NCG_Reserved_I2 r29
198 #define NCG_Reserved_F1 fr8
199 #define NCG_Reserved_F2 fr8R
200 #define NCG_Reserved_D1 fr10
201 #define NCG_Reserved_D2 fr11
205 /* -----------------------------------------------------------------------------
206 The x86 register mapping
208 Ok, we've only got 6 general purpose registers, a frame pointer and a
209 stack pointer. \tr{%eax} and \tr{%edx} are return values from C functions,
210 hence they get trashed across ccalls and are caller saves. \tr{%ebx},
211 \tr{%esi}, \tr{%edi}, \tr{%ebp} are all callee-saves.
220 Leaving SpLim out of the picture.
221 -------------------------------------------------------------------------- */
226 #define REG(x) __asm__("%" #x)
228 #ifndef not_doing_dynamic_linking
233 #ifndef STOLEN_X86_REGS
234 #define STOLEN_X86_REGS 4
237 #if STOLEN_X86_REGS >= 3
241 #if STOLEN_X86_REGS >= 4
245 #define MAX_REAL_VANILLA_REG 1 /* always, since it defines the entry conv */
246 #define MAX_REAL_FLOAT_REG 0
247 #define MAX_REAL_DOUBLE_REG 0
248 #define MAX_REAL_LONG_REG 0
252 /* -----------------------------------------------------------------------------
253 The x86-64 register mapping
255 %rax caller-saves, don't steal this one
257 %rcx arg reg, caller-saves
258 %rdx arg reg, caller-saves
259 %rsi arg reg, caller-saves
260 %rdi arg reg, caller-saves
261 %rbp YES (our *prime* register)
262 %rsp (unavailable - stack pointer)
263 %r8 arg reg, caller-saves
264 %r9 arg reg, caller-saves
272 %xmm0-7 arg regs, caller-saves
273 %xmm8-15 caller-saves
275 Use the caller-saves regs for Rn, because we don't always have to
276 save those (as opposed to Sp/Hp/SpLim etc. which always have to be
279 --------------------------------------------------------------------------- */
283 #define REG(x) __asm__("%" #x)
294 #define REG_SpLim r15
304 #define CALLER_SAVES_R3
305 #define CALLER_SAVES_R4
306 #define CALLER_SAVES_R5
307 #define CALLER_SAVES_R6
309 #define CALLER_SAVES_F1
310 #define CALLER_SAVES_F2
311 #define CALLER_SAVES_F3
312 #define CALLER_SAVES_F4
314 #define CALLER_SAVES_D1
315 #define CALLER_SAVES_D2
317 #define MAX_REAL_VANILLA_REG 6
318 #define MAX_REAL_FLOAT_REG 4
319 #define MAX_REAL_DOUBLE_REG 2
320 #define MAX_REAL_LONG_REG 0
324 /* -----------------------------------------------------------------------------
325 The Motorola 680x0 register mapping
327 A Sun3 (mc680x0) has eight address registers, \tr{a0} to \tr{a7}, and
328 eight data registers, \tr{d0} to \tr{d7}. Address operations have to
329 be done through address registers; data registers are used for
330 comparison values and data.
332 Here's the register-usage picture for m68k boxes with GCC.
335 a0 & used directly by GCC \\
336 a1 & used directly by GCC \\
338 a2..a5 & callee-saved: available for STG registers \\
339 & (a5 may be special, ``global'' register for PIC?) \\
341 a6 & C-stack frame pointer \\
342 a7 & C-stack pointer \\
344 d0 & used directly by GCC \\
345 d1 & used directly by GCC \\
346 d2 & really needed for local optimisation by GCC \\
348 d3..d7 & callee-saved: available for STG registers
350 fp0 & call-clobbered \\
351 fp1 & call-clobbered \\
352 fp2..fp7 & callee-saved: available for STG registers
354 -------------------------------------------------------------------------- */
358 #define REG(x) __asm__(#x)
369 #define MAX_REAL_VANILLA_REG 2
383 /* -----------------------------------------------------------------------------
384 The DECstation (MIPS) register mapping
386 Here's at least some simple stuff about registers on a MIPS.
388 \tr{s0}--\tr{s7} are callee-save integer registers; they are our
389 ``prize'' stolen registers. There is also a wad of callee-save
390 floating-point registers, \tr{$f20}--\tr{$f31}; we'll use some of
393 \tr{t0}--\tr{t9} are caller-save (``temporary?'') integer registers.
394 We can steal some, but we might have to save/restore around ccalls.
395 -------------------------------------------------------------------------- */
399 #define REG(x) __asm__("$" #x)
401 #define CALLER_SAVES_R5
402 #define CALLER_SAVES_R6
403 #define CALLER_SAVES_R7
404 #define CALLER_SAVES_R8
406 #define CALLER_SAVES_USER
432 #endif /* mipse[lb] */
434 /* -----------------------------------------------------------------------------
435 The PowerPC register mapping
437 0 system glue? (caller-save, volatile)
438 1 SP (callee-save, non-volatile)
439 2 AIX, powerpc64-linux:
440 RTOC (a strange special case)
442 (caller-save, volatile)
444 reserved for use by system
446 3-10 args/return (caller-save, volatile)
447 11,12 system glue? (caller-save, volatile)
448 13 on 64-bit: reserved for thread state pointer
449 on 32-bit: (callee-save, non-volatile)
450 14-31 (callee-save, non-volatile)
452 f0 (caller-save, volatile)
453 f1-f13 args/return (caller-save, volatile)
454 f14-f31 (callee-save, non-volatile)
456 \tr{14}--\tr{31} are wonderful callee-save registers on all ppc OSes.
457 \tr{0}--\tr{12} are caller-save registers.
459 \tr{%f14}--\tr{%f31} are callee-save floating-point registers.
461 We can do the Whole Business with callee-save registers only!
462 -------------------------------------------------------------------------- */
466 #define REG(x) __asm__(#x)
500 #define REG_SpLim r24
508 /* -----------------------------------------------------------------------------
509 The IA64 register mapping
511 We place the general registers in the locals area of the register stack,
512 so that the call mechanism takes care of saving them for us. We reserve
513 the first 16 for gcc's use - since gcc uses the highest used register to
514 determine the register stack frame size, this gives us a constant size
515 register stack frame.
517 \tr{f16-f32} are the callee-saved floating point registers.
518 -------------------------------------------------------------------------- */
522 #define REG(x) __asm__(#x)
542 #define REG_SpLim loc26
548 /* -----------------------------------------------------------------------------
549 The Sun SPARC register mapping
551 !! IMPORTANT: if you change this register mapping you must also update
552 compiler/nativeGen/SPARC/Regs.hs. That file handles the
553 mapping for the NCG. This one only affects via-c code.
555 The SPARC register (window) story: Remember, within the Haskell
556 Threaded World, we essentially ``shut down'' the register-window
557 mechanism---the window doesn't move at all while in this World. It
558 *does* move, of course, if we call out to arbitrary~C...
560 The %i, %l, and %o registers (8 each) are the input, local, and
561 output registers visible in one register window. The 8 %g (global)
562 registers are visible all the time.
565 scratch: volatile across C-fn calls. used by linker.
566 app: usable by application
567 system: reserved for system
569 alloc: allocated to in the register allocator, intra-closure only
571 GHC usage v8 ABI v9 ABI
574 %g1 alloc scratch scrach
577 %g4 alloc app scratch
582 Output: can be zapped by callee
583 %o0-o5 alloc caller saves
587 Local: maintained by register windowing mechanism
607 The paired nature of the floating point registers causes complications for
608 the native code generator. For convenience, we pretend that the first 22
609 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
610 float (single) regs. The NCG acts accordingly. That means that the
611 following FP assignment is rather fragile, and should only be changed
612 with extreme care. The current scheme is:
614 %f0 /%f1 FP return from C
617 %f6 /%f7 ncg double spill tmp #1
618 %f8 /%f9 ncg double spill tmp #2
619 %f10/%f11 allocatable
620 %f12/%f13 allocatable
621 %f14/%f15 allocatable
622 %f16/%f17 allocatable
623 %f18/%f19 allocatable
624 %f20/%f21 allocatable
630 %f26 ncg single spill tmp #1
631 %f27 ncg single spill tmp #2
637 -------------------------------------------------------------------------- */
641 #define REG(x) __asm__("%" #x)
643 #define CALLER_SAVES_USER
645 #define CALLER_SAVES_F1
646 #define CALLER_SAVES_F2
647 #define CALLER_SAVES_F3
648 #define CALLER_SAVES_F4
649 #define CALLER_SAVES_D1
650 #define CALLER_SAVES_D2
664 /* for each of the double arg regs,
665 Dn_2 is the high half. */
681 #define NCG_SpillTmp_I1 g1
682 #define NCG_SpillTmp_I2 g2
683 #define NCG_SpillTmp_F1 f26
684 #define NCG_SpillTmp_F2 f27
685 #define NCG_SpillTmp_D1 f6
686 #define NCG_SpillTmp_D2 f8
689 #define NCG_FirstFloatReg f22
695 /* -----------------------------------------------------------------------------
696 * These constants define how many stg registers will be used for
697 * passing arguments (and results, in the case of an unboxed-tuple
700 * We usually set MAX_REAL_VANILLA_REG and co. to be the number of the
701 * highest STG register to occupy a real machine register, otherwise
702 * the calling conventions will needlessly shuffle data between the
703 * stack and memory-resident STG registers. We might occasionally
704 * set these macros to other values for testing, though.
706 * Registers above these values might still be used, for instance to
707 * communicate with PrimOps and RTS functions.
710 #ifndef MAX_REAL_VANILLA_REG
712 # define MAX_REAL_VANILLA_REG 8
713 # elif defined(REG_R7)
714 # define MAX_REAL_VANILLA_REG 7
715 # elif defined(REG_R6)
716 # define MAX_REAL_VANILLA_REG 6
717 # elif defined(REG_R5)
718 # define MAX_REAL_VANILLA_REG 5
719 # elif defined(REG_R4)
720 # define MAX_REAL_VANILLA_REG 4
721 # elif defined(REG_R3)
722 # define MAX_REAL_VANILLA_REG 3
723 # elif defined(REG_R2)
724 # define MAX_REAL_VANILLA_REG 2
725 # elif defined(REG_R1)
726 # define MAX_REAL_VANILLA_REG 1
728 # define MAX_REAL_VANILLA_REG 0
732 #ifndef MAX_REAL_FLOAT_REG
734 # define MAX_REAL_FLOAT_REG 4
735 # elif defined(REG_F3)
736 # define MAX_REAL_FLOAT_REG 3
737 # elif defined(REG_F2)
738 # define MAX_REAL_FLOAT_REG 2
739 # elif defined(REG_F1)
740 # define MAX_REAL_FLOAT_REG 1
742 # define MAX_REAL_FLOAT_REG 0
746 #ifndef MAX_REAL_DOUBLE_REG
748 # define MAX_REAL_DOUBLE_REG 2
749 # elif defined(REG_D1)
750 # define MAX_REAL_DOUBLE_REG 1
752 # define MAX_REAL_DOUBLE_REG 0
756 #ifndef MAX_REAL_LONG_REG
758 # define MAX_REAL_LONG_REG 1
760 # define MAX_REAL_LONG_REG 0
764 /* define NO_ARG_REGS if we have no argument registers at all (we can
765 * optimise certain code paths using this predicate).
767 #if MAX_REAL_VANILLA_REG < 2
773 #endif /* MACHREGS_H */