1 ********************** TSMC 90nm Header **************************
3 ******************************************************************
4 * Set Process, Voltage and Temperature corner
5 ******************************************************************
8 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT
9 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_RES
10 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_18
11 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_na18
12 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_DIO_esd
13 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_DIO_18
16 .param sup=0.9 * Supply voltage
17 .temp 80 * Temperature
19 ******************************************************************
20 * Standard Parameters and Options
21 ******************************************************************
26 .param strong0=0 * Used in verilog, just needs to be defined to run hspice
27 .param strong1=1 * Used in verilog, just needs to be defined to run hspice
29 .options ACCT OPTS post
34 .param AVT0N = AGAUSS(0.0, '0.01 / 0.1' , 1)
35 .param AVT0P = AGAUSS(0.0, '0.01 / 0.1' , 1)
36 .param ABN = AGAUSS(0.0, '0.02 / 0.1' , 1)
37 .param ABP = AGAUSS(0.0, '0.02 / 0.1' , 1)
39 ******************************************************************
41 ******************************************************************
42 * .hsimparam HSIMDCINIT=0
43 .hsimparam HSIMVDD=0.9
46 * .param HSIMOUTPUT=fsdb
47 * .param HSIMOUTPUTTBL=rawfile
51 .param HSIMPRINTSIMSTATUS=1
52 .param HSIMOUTPUTFLUSH=200n
59 * defaults -- play with these?
61 * .param HSIMPORTV=0.001
62 * .param HSIMPORTCR=0.01
71 * these are here to keep hsim from "optimizing away" the signals we care about
87 * .print v(marinagu@0/outdockw@3/marinaou@1/*)
88 * .print v(marinagu@0/jtagcent@0/*)