3 == Ports ===========================================================
10 == Constants ========================================================
11 ADD: add the two arguments; treat link as carry
12 SUB: subtract the two arguments; treat link as carry
16 SORT: output min(in1,in2) followed by max(in1,in2) (FIXME: redundant?)
18 == TeX ==============================================================
19 This ship is a two-input arithmetic unit. It features several
20 opcodes, such as {\tt ADD} and {\tt SUB}. In my opinion, it is
23 FIXME: implement all the link bit stuff
25 Use carry-in bit to create a selector? Perhaps a waste of an ALU.
27 Carry-save / carry completion stuff.
29 Flags: zero, negative, overflow, ?
36 == Fleeterpreter ====================================================
37 public void service() {
38 if (box_in1.dataReadyForShip() &&
39 box_in2.dataReadyForShip() &&
40 box_inOp.dataReadyForShip() &&
41 box_out.readyForItemFromShip()) {
42 int a = box_in1.removeDataForShip();
43 int b = box_in2.removeDataForShip();
44 int op = box_inOp.removeDataForShip();
46 case 0: box_out.addDataFromShip(a+b); // ADD
48 case 1: box_out.addDataFromShip(a-b); // SUB
50 default: box_out.addDataFromShip(0);
56 == FleetSim ==============================================================
58 == FPGA ==============================================================
61 reg [(`DATAWIDTH-1):0] reg_a;
63 reg [(`DATAWIDTH-1):0] reg_b;
65 reg [(`DATAWIDTH-1):0] reg_op;
67 always @(posedge clk) begin
69 `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
72 `onread(in2_r, in2_a) have_b = 1; reg_b = in2_d; end
75 `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
78 if (have_a && have_b && have_op) begin
80 0: out_d = reg_a + reg_b;
81 1: out_d = reg_a - reg_b;
84 `onwrite(out_r, out_a)
95 == Contributors =========================================================
96 Adam Megacz <megacz@cs.berkeley.edu>