3 == Ports ===========================================================
14 == Constants ========================================================
15 == TeX ==============================================================
17 {\tt Alu3} is a three-input adder which produces a pair of outputs in
18 carry-save form. It has no opcode input.
20 This ship also contains a private ``bit fifo'' similar to the {\tt
21 BitFifo} ship, except that only the dequeueing (output) interface is
22 exposed to the programmer. Each addition operation performed causes
23 the lowest bit of the {\it save} output to be enqueued into the bit
24 fifo. This can be used to produce a very efficient multiplier; see
25 the test case for this ship for more details.
27 \subsection*{Semantics}
29 When a value is present at each of {\tt in1}, {\tt in2} and {\tt in3},
30 these three values are consumed. The {\it carry} result of carry-save
31 addition is placed in {\tt out1}, and the {\it save} result of
32 carry-save addition is placed in {\tt out2}.
36 Is the second output supposed to be shifted?
38 Provide a way to clear/flush the internal bitfifo.
40 Do we even need this? Can we do the same thing with {\tt Lut3} and
41 {\tt BitFifo} together?
44 == Fleeterpreter ====================================================
46 BitFifo.BitStorage outBits = new BitFifo.BitStorage(74);
47 public void service() {
48 if (outBits.size() >= 37) {
49 if (box_outBits.readyForDataFromShip()) {
50 box_outBits.addDataFromShip(outBits.get(37));
53 if (box_in1.dataReadyForShip() &&
54 box_in2.dataReadyForShip() &&
55 box_in3.dataReadyForShip() &&
56 outBits.hasSpace(1) &&
57 box_out1.readyForDataFromShip() &&
58 box_out2.readyForDataFromShip()) {
59 long v1 = box_in1.removeDataForShip();
60 long v2 = box_in2.removeDataForShip();
61 long v3 = box_in3.removeDataForShip();
63 o1 = ((v1 & v2) | (v2 & v3) | (v1 & v3))/* << 1*/;
64 o2 = (v1 ^ v2 ^ v3) >> 1;
65 outBits.add((v1 ^ v2 ^ v3) & 0x1L, 1);
66 box_out1.addDataFromShip(o1);
67 box_out2.addDataFromShip(o2);
71 == FleetSim ==============================================================
73 == FPGA ==============================================================
75 reg [73:0] bitstorage; initial bitstorage = 0;
76 reg [7:0] bitstorage_count; initial bitstorage_count = 0;
78 always @(posedge clk) begin
82 bitstorage_count <= 0;
84 if (out1_r && out1_a) out1_r <= 0;
85 if (out2_r && out2_a) out2_r <= 0;
86 if (outBits_r && outBits_a) outBits_r <= 0;
87 if (!in1_r && in1_a) in1_a <= 0;
88 if (!in2_r && in2_a) in2_a <= 0;
89 if (!in3_r && in3_a) in3_a <= 0;
90 if (!out1_r && !out2_r && !outBits_r && in1_r && in2_r && in3_r) begin
91 out1_d <= { ((in1_d & in2_d)
94 out2_d <= { 1'b0, (in1_d[(`DATAWIDTH-1):1] ^
95 in2_d[(`DATAWIDTH-1):1] ^
96 in3_d[(`DATAWIDTH-1):1]) };
97 if (bitstorage_count >= `DATAWIDTH-1) begin
98 outBits_d <= bitstorage[(`DATAWIDTH-1):0];
100 bitstorage_count <= 0;
101 bitstorage <= bitstorage >> `DATAWIDTH;
103 bitstorage[bitstorage_count] <= (in1_d[0] ^ in2_d[0] ^ in3_d[0]);
104 bitstorage_count <= bitstorage_count+1;
116 == Test ========================================================================
119 #ship bitfifo : BitFifo
122 #ship rotator : Rotator
128 // 0: 100100100111110000000
129 // sel 011110100001001000000
130 // 1: 111000101000011000011
131 // r: 111000100110111000000
133 alu3.in1: literal 1; deliver; load repeat counter with 36; deliver;
134 alu3.in2: literal 0; deliver; literal 1; load repeat counter with 36; deliver;
135 alu3.in3: literal 4; deliver; load repeat counter with 36; deliver;
137 alu3.out1: take; sendto debug.in; [*] take;
138 alu3.out2: take; wait; sendto debug.in; [*] take;
139 alu3.outBits: take; wait; sendto debug.in;
149 == Contributors =========================================================
150 Amir Kamil <kamil@cs.berkeley.edu>
151 Adam Megacz <megacz@cs.berkeley.edu>