3 == Ports:Interpreter ===========================================================
7 == Ports:Bee2 ===========================================================
11 percolate down: Clkin_p 1
12 percolate down: Clkin_m 1
13 percolate up: clk_out 1
15 percolate down: RDWR_B 1
16 percolate down: CS_B 1
18 percolate up: INIT_B 1
20 percolate up: rst_out 1
21 percolate down: rst_in 1
23 == Ports:ML509 ===========================================================
27 percolate down: uart_in 1
28 percolate up: uart_out 1
29 percolate up: rst_out 1
30 percolate down: rst_in 1
31 percolate down: clk_pin 1
32 percolate up: clk_out 1
34 percolate up: gpio_led_c 1
35 percolate up: gpio_led_e 1
36 percolate up: gpio_led_n 1
37 percolate up: gpio_led_s 1
38 percolate up: gpio_led_w 1
39 percolate down: gpio_dip_sw1 1
42 == TeX ==============================================================
44 This ship is used for debugging. It has only one port, {\tt in}.
45 Programmers should send debug report values to this port. How such
46 values are reported back to the programmer doing the debugging is left
51 Provide an {\tt inOp} port and use opcode ports \cite{am25} to
52 effectively allow multiple independent ``debug streams''
54 Provide a way to programmatically read back the output of the debug
57 == Fleeterpreter ====================================================
58 public void service() {
59 if (box_in.dataReadyForShip())
60 ((Interpreter)getFleet()).debug(new BitVector(37).set(box_in.removeDataForShip()));
63 == FPGA:Bee2 ==============================================================
73 wire [7:0] write_data;
82 OBUF obuf_cclk( .I( CCLK_int ), .O( CCLK ) );
83 IOBUF iobuf_d0( .I( D_O[0] ), .IO( D[0] ), .O( D_I[0] ), .T( D_T[0] ) );
84 IOBUF iobuf_d1( .I( D_O[1] ), .IO( D[1] ), .O( D_I[1] ), .T( D_T[1] ) );
85 IOBUF iobuf_d2( .I( D_O[2] ), .IO( D[2] ), .O( D_I[2] ), .T( D_T[2] ) );
86 IOBUF iobuf_d3( .I( D_O[3] ), .IO( D[3] ), .O( D_I[3] ), .T( D_T[3] ) );
87 IOBUF iobuf_d4( .I( D_O[4] ), .IO( D[4] ), .O( D_I[4] ), .T( D_T[4] ) );
88 IOBUF iobuf_d5( .I( D_O[5] ), .IO( D[5] ), .O( D_I[5] ), .T( D_T[5] ) );
89 IOBUF iobuf_d6( .I( D_O[6] ), .IO( D[6] ), .O( D_I[6] ), .T( D_T[6] ) );
90 IOBUF iobuf_d7( .I( D_O[7] ), .IO( D[7] ), .O( D_I[7] ), .T( D_T[7] ) );
92 // Clock buffer and reset
96 IBUFGDS_LVDS_25 diff_usrclk_buf( .I( Clkin_p ), .IB( Clkin_m ), .O( clk_fast ) );
98 wire clkdiv0_unbuffered;
101 // BUFG bufg1 (.I(clkdiv0_unbuffered), .O(clk_out));
102 // BUFG bufg1 (.I(clk_fast), .O(clk_out));
103 // BUFG bufg1 (.I(clk0_unbuffered), .O(clk_out));
104 BUFG bufg2 (.I(clk0_unbuffered), .O(clk0_fb));
109 BUFG bufg1 (.I(foo2), .O(clk_out));
111 always @(posedge clk_fast) begin
119 .CLKIN_PERIOD (10.0),
120 .DUTY_CYCLE_CORRECTION ("TRUE"),
121 .DLL_FREQUENCY_MODE ("LOW"),
122 .STARTUP_WAIT ("FALSE")
126 .CLK0 (clk0_unbuffered),
130 // BUFG GBUF_FOR_MUX_CLOCK (.I(clk_half), .O(clk_out));
131 // BUFG GBUF_FOR_MUX_CLOCK (.I(clk_fast), .O(clk_out));
135 FD rstr0( .D( 1'b0 ), .Q( rstr[0] ), .C( clk ) ); defparam rstr0.INIT = 1'b1;
136 FD rstr1( .D( rstr[0] ), .Q( rstr[1] ), .C( clk ) ); defparam rstr1.INIT = 1'b1;
137 FD rstr2( .D( rstr[1] ), .Q( rstr[2] ), .C( clk ) ); defparam rstr2.INIT = 1'b1;
138 FD rstr3( .D( rstr[2] ), .Q( rstr[3] ), .C( clk ) ); defparam rstr3.INIT = 1'b1;
139 assign User_Rst = |rstr;
142 .WrFifo_Din( write_data ),
143 .WrFifo_WrEn( write_enable ),
144 .WrFifo_Full( write_full ),
146 .RdFifo_Dout( read_data ),
147 .RdFifo_RdEn( read_enable ),
148 .RdFifo_Empty( read_empty ),
150 .User_Rst( User_Rst ),
152 .Sys_Rst( User_Rst ),
153 .Sys_Clk( clk_fast ),
163 wire data_to_host_full;
164 reg [7:0] data_to_host;
165 wire data_to_fleet_empty;
166 wire [7:0] data_to_fleet;
167 reg data_to_host_write_enable;
168 reg data_to_fleet_read_enable;
170 assign data_to_fleet = read_data;
171 assign read_enable = data_to_fleet_read_enable;
172 assign write_enable = data_to_host_write_enable;
173 assign write_data = data_to_host;
174 assign data_to_fleet_empty = read_empty;
175 assign data_to_host_full = write_full;
177 initial data_to_fleet_read_enable = 1;
178 initial data_to_host_write_enable = 0;
180 reg [7:0] force_reset;
181 assign rst_out = User_Rst || (force_reset!=0);
183 /// Common //////////////////////////////////////////////////////////////////////////////
188 reg [`WORDWIDTH-1:0] data_to_host_full_word;
192 assign out_d_ = out_d;
197 always @(posedge clk) begin
198 if (/*rst_in*/User_Rst) begin
209 data_to_host_write_enable <= 0;
210 if (force_reset == 1) begin
212 data_to_host_write_enable <= 1;
217 end else if (force_reset != 0) begin
218 force_reset <= force_reset-1;
219 end else if (count_out==0 && `in_full) begin
221 data_to_host_full_word <= in_d;
223 end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable && credits!=0) begin
224 data_to_host <= { 2'b0, data_to_host_full_word[5:0] };
225 data_to_host_full_word <= (data_to_host_full_word >> 6);
226 data_to_host_write_enable <= 1;
227 count_out <= count_out-1;
228 credits = credits - 1;
232 data_to_fleet_read_enable <= 0;
233 if (!data_to_fleet_empty && !data_to_fleet_read_enable) begin
235 // Note: if the switch fabric refuses to accept a new item,
236 // we can get deadlocked in a state where sending a reset
237 // code (2'b11) won't have any effect. Probably need to go
238 // back to using the break signal.
241 if (data_to_fleet[7:6] == 2'b00 && `out_empty) begin
242 data_to_fleet_read_enable <= 1;
243 out_d <= { out_d[43:0], data_to_fleet[5:0] };
244 if (count_in==9) begin
248 count_in <= count_in+1;
251 // command 1: flow control credit
252 end else if (data_to_fleet[7:6] == 2'b01) begin
253 data_to_fleet_read_enable <= 1;
254 credits = credits + data_to_fleet[5:0];
256 // command 3: reset (and echo back reset code)
257 end else if (data_to_fleet[7:6] == 2'b11) begin
258 data_to_fleet_read_enable <= 1;
259 data_to_host <= data_to_fleet;
270 == UCF:Bee2 =================================================================
272 ######################################
274 ######################################
276 NET Clkin_p LOC = AP21 | IOSTANDARD = LVDS_25;
277 NET Clkin_m LOC = AN21 | IOSTANDARD = LVDS_25;
279 NET rst_in LOC = H4 | IOSTANDARD = LVCMOS18;
281 NET clk_out PERIOD=50MHz;
282 //NET clk_out PERIOD=100MHz;
283 //NET clk_fast PERIOD=100MHz;
284 NET Clkin_p PERIOD=100MHz;
285 NET Clkin_m PERIOD=100MHz;
287 ######################################
288 ## SelectMAP interface pins
289 ######################################
291 NET D<0> LOC = AU9 | IOSTANDARD = LVCMOS25;
292 NET D<1> LOC = AV9 | IOSTANDARD = LVCMOS25;
293 NET D<2> LOC = AY9 | IOSTANDARD = LVCMOS25;
294 NET D<3> LOC = AW9 | IOSTANDARD = LVCMOS25;
295 NET D<4> LOC = AW34 | IOSTANDARD = LVCMOS25;
296 NET D<5> LOC = AY34 | IOSTANDARD = LVCMOS25;
297 NET D<6> LOC = AV34 | IOSTANDARD = LVCMOS25;
298 NET D<7> LOC = AU34 | IOSTANDARD = LVCMOS25;
300 NET RDWR_B LOC = AR34 | IOSTANDARD = LVCMOS25;
301 NET CS_B LOC = AT34 | IOSTANDARD = LVCMOS25;
302 NET INIT_B LOC = AR9 | IOSTANDARD = LVCMOS25;
303 NET CCLK LOC = C14 | IOSTANDARD = LVCMOS25;
309 == FPGA:ML509 ==============================================================
311 assign gpio_led_n = 0;
312 assign gpio_led_s = 0;
313 assign gpio_led_e = 1;
314 assign gpio_led_w = 1;
325 bscanvirtex(.TDO(tdo),
352 .strobe_o (strobe_o),
362 always @(posedge clk) begin
372 reg [`WORDWIDTH-1:0] data_to_host_full_word;
376 assign out_d_ = out_d;
378 wire data_to_host_full;
379 reg [7:0] data_to_host;
380 wire data_to_fleet_empty;
381 wire [7:0] data_to_fleet;
382 reg data_to_host_write_enable;
383 reg data_to_fleet_read_enable;
384 reg [7:0] force_reset;
386 assign clk_out = clk_pin;
394 assign rst_out = rst_in || (force_reset!=0) /* || break */;
396 // fst=3 means clock divider is 3+2=5 for a 50Mhz clock => 10Mhz
397 // using a 33Mhz clock,
398 // 33.333Mhz / 38400hz * 4 = 217.013 => 215+2,1 => 215,1
399 // using a 100Mhz clock,
400 // 100Mhz / 38400hz * 4 = 651.039 => 215+2,3 => 215,3
401 // using a 100Mhz clock, 115200baud
402 // 100Mhz / 115200hz * 4 = 217.013 => 215+2,1 => 215,1
403 // sasc_brg sasc_brg(clk, !rst_in, 215, 3, sio_ce, sio_ce_x4);
404 sasc_brg sasc_brg(clk, !rst_in, 215, 1, sio_ce, sio_ce_x4);
405 sasc_top sasc_top(clk, !rst_in,
414 data_to_fleet_read_enable,
415 data_to_host_write_enable,
424 always @(posedge clk) begin
425 if (rst_in /* || break */) begin
436 data_to_host_write_enable <= 0;
437 if (force_reset == 1) begin
439 data_to_host_write_enable <= 1;
444 end else if (force_reset != 0) begin
445 force_reset <= force_reset-1;
446 end else if (count_out==0 && `in_full) begin
448 data_to_host_full_word <= in_d;
450 end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable && credits!=0) begin
451 data_to_host <= { 2'b0, data_to_host_full_word[5:0] };
452 data_to_host_full_word <= (data_to_host_full_word >> 6);
453 data_to_host_write_enable <= 1;
454 count_out <= count_out-1;
455 credits = credits - 1;
459 data_to_fleet_read_enable <= 0;
460 if (!data_to_fleet_empty && !data_to_fleet_read_enable) begin
462 // Note: if the switch fabric refuses to accept a new item,
463 // we can get deadlocked in a state where sending a reset
464 // code (2'b11) won't have any effect. Probably need to go
465 // back to using the break signal.
468 if (data_to_fleet[7:6] == 2'b00 && `out_empty) begin
469 data_to_fleet_read_enable <= 1;
470 out_d <= { out_d[43:0], data_to_fleet[5:0] };
471 if (count_in==9) begin
475 count_in <= count_in+1;
478 // command 1: flow control credit
479 end else if (data_to_fleet[7:6] == 2'b01) begin
480 data_to_fleet_read_enable <= 1;
481 credits = credits + data_to_fleet[5:0];
484 // uncommenting this requires changing data_to_host_write_enable
485 // to a blocking assignment, and seems to cause data loss whenever
486 // more than four items are in flight.
488 end else if (data_to_fleet[7:6] == 2'b10 && !data_to_host_full && !data_to_host_write_enable) begin
489 data_to_fleet_read_enable <= 1;
490 data_to_host <= data_to_fleet;
491 data_to_host_write_enable = 1;
494 // command 3: reset (and echo back reset code)
495 end else if (data_to_fleet[7:6] == 2'b11) begin
496 data_to_fleet_read_enable <= 1;
497 data_to_host <= data_to_fleet;
507 == UCF:ML509 =================================================================
509 Net clk_pin LOC=AH15;
510 Net clk_pin PERIOD = 10 ns HIGH 50%; # 100Mhz
513 #Net clk_pin LOC=AH17;
514 #Net clk_pin TNM_NET = clk_pin;
515 #TIMESPEC TS_clk_pin = PERIOD clk_pin 30 ns HIGH 50%; # 33Mhz
521 #Net uart_cts LOC=G6;
522 #Net uart_cts IOSTANDARD = LVCMOS33;
525 #Net uart_rts LOC=F6;
526 #Net uart_rts IOSTANDARD = LVCMOS33;
529 Net uart_in LOC=AG15;
530 #Net uart_in IOSTANDARD = LVCMOS33;
534 Net uart_out LOC=AG20;
535 #Net uart_out IOSTANDARD = LVCMOS33;
539 NET gpio_led_c LOC="E8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
540 NET gpio_led_e LOC="AG23"; # Bank 2, Vcco=3.3V
541 NET gpio_led_n LOC="AF13"; # Bank 2, Vcco=3.3V
542 NET gpio_led_s LOC="AG12"; # Bank 2, Vcco=3.3V
543 NET gpio_led_w LOC="AF23"; # Bank 2, Vcco=3.3V
544 NET gpio_dip_sw1 LOC="U25"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
547 == Test ================================================================
556 == Contributors =========================================================
557 Adam Megacz <megacz@cs.berkeley.edu>