3 == Ports ===========================================================
7 percolate down: uart_in 1
8 percolate up: uart_out 1
9 percolate up: rst_out 1
10 percolate down: rst_in 1
12 == Constants ========================================================
14 == TeX ==============================================================
16 percolate up: uart_rts 1
17 percolate down: uart_cts 1
19 This ship is used for debugging. It has only one port, {\tt in}.
20 Programmers should send debug report values to this port. How such
21 values are reported back to the programmer doing the debugging is left
26 Provide an {\tt inOp} port and use opcode ports \cite{am25} to
27 effectively allow multiple independent ``debug streams''
29 Provide a way to programmatically read back the output of the debug
32 == Fleeterpreter ====================================================
33 public void service() {
34 if (box_in.dataReadyForShip())
35 ((Interpreter)getFleet()).debug(box_in.removeDataForShip());
38 == FleetSim ==============================================================
40 == FPGA ==============================================================
47 reg [`WORDWIDTH-1:0] data_to_host_full_word;
51 assign out_d_ = out_d;
53 wire data_to_host_full;
54 reg [7:0] data_to_host;
55 wire data_to_fleet_empty;
56 wire [7:0] data_to_fleet;
57 reg data_to_host_write_enable;
58 reg data_to_fleet_read_enable;
66 assign rst_out = rst_in && !break;
68 sasc_brg sasc_brg(clk, rst_in, 3, 65, sio_ce, sio_ce_x4);
69 sasc_top sasc_top(clk, rst_in,
78 data_to_fleet_read_enable,
79 data_to_host_write_enable,
85 // break and break are _active high_
86 always @(posedge clk) break_last <= break;
87 assign break_i = break && !break_last;
88 assign break_done = !break && break_last;
91 always @(posedge clk) begin
102 data_to_host_write_enable <= 0;
104 end else if (break_done) begin
105 data_to_host_write_enable <= 1;
108 end else if (send_k) begin
109 data_to_host_write_enable <= 1;
112 end else if (count_out==0 && `in_full) begin
114 data_to_host_full_word <= in_d;
116 end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable) begin
117 data_to_host <= data_to_host_full_word[7:0];
118 data_to_host_full_word <= (data_to_host_full_word >> 8);
119 data_to_host_write_enable <= 1;
120 count_out <= count_out-1;
124 data_to_fleet_read_enable <= 0;
125 if (!data_to_fleet_empty && `out_empty && !data_to_fleet_read_enable) begin
126 out_d <= { out_d[41:0], data_to_fleet[7:0] };
127 data_to_fleet_read_enable <= 1;
128 if (count_in==7) begin
132 count_in <= count_in+1;
139 == Test ================================================================
148 == Contributors =========================================================
149 Adam Megacz <megacz@cs.berkeley.edu>