3 == Ports ===========================================================
7 percolate down: uart_in 1
8 percolate up: uart_out 1
9 percolate up: rst_out 1
10 percolate down: rst_in 1
12 == Constants ========================================================
14 == TeX ==============================================================
16 percolate up: uart_rts 1
17 percolate down: uart_cts 1
19 This ship is used for debugging. It has only one port, {\tt in}.
20 Programmers should send debug report values to this port. How such
21 values are reported back to the programmer doing the debugging is left
26 Provide an {\tt inOp} port and use opcode ports \cite{am25} to
27 effectively allow multiple independent ``debug streams''
29 Provide a way to programmatically read back the output of the debug
32 == Fleeterpreter ====================================================
33 public void service() {
34 if (box_in.dataReadyForShip())
35 ((Interpreter)getFleet()).debug(box_in.removeDataForShip());
38 == FleetSim ==============================================================
40 == FPGA ==============================================================
47 reg [`WORDWIDTH-1:0] data_to_host_full_word;
51 assign out_d_ = out_d;
53 wire data_to_host_full;
54 reg [7:0] data_to_host;
55 wire data_to_fleet_empty;
56 wire [7:0] data_to_fleet;
57 reg data_to_host_write_enable;
58 reg data_to_fleet_read_enable;
66 assign rst_out = rst_in || break;
68 // fst=3 means clock divider is 3+2=5 for a 50Mhz clock => 10Mhz
69 // using a 33Mhz clock,
70 // 33.333Mhz / 38400hz * 4 = 217.013 => 215+2,1
71 sasc_brg sasc_brg(clk, !rst_in, 215, 1, sio_ce, sio_ce_x4);
72 sasc_top sasc_top(clk, !rst_in,
81 data_to_fleet_read_enable,
82 data_to_host_write_enable,
88 // break and break are _active high_
89 always @(posedge clk) break_last <= break;
90 assign break_i = break && !break_last;
91 assign break_done = !break && break_last;
94 always @(posedge clk) begin
104 data_to_host_write_enable <= 0;
106 end else if (break_done) begin
107 data_to_host_write_enable <= 1;
110 end else if (send_k) begin
111 data_to_host_write_enable <= 1;
114 end else if (count_out==0 && `in_full) begin
116 data_to_host_full_word <= in_d;
118 end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable) begin
119 data_to_host <= { 2'b0, data_to_host_full_word[5:0] };
120 data_to_host_full_word <= (data_to_host_full_word >> 6);
121 data_to_host_write_enable <= 1;
122 count_out <= count_out-1;
126 data_to_fleet_read_enable <= 0;
127 if (!data_to_fleet_empty && `out_empty && !data_to_fleet_read_enable) begin
128 out_d <= { out_d[41:0], data_to_fleet[7:0] };
129 data_to_fleet_read_enable <= 1;
130 if (count_in==7) begin
134 count_in <= count_in+1;
141 == Test ================================================================
150 == Contributors =========================================================
151 Adam Megacz <megacz@cs.berkeley.edu>