3 == Ports ===========================================================
7 percolate down: Clkin_p 1
8 percolate down: Clkin_m 1
9 percolate up: clk_out 1
11 percolate down: RDWR_B 1
12 percolate down: CS_B 1
14 percolate up: INIT_B 1
16 percolate up: rst_out 1
17 percolate down: rst_in 1
19 == Constants ========================================================
21 == TeX ==============================================================
23 percolate up: uart_rts 1
24 percolate down: uart_cts 1
26 This ship is used for debugging. It has only one port, {\tt in}.
27 Programmers should send debug report values to this port. How such
28 values are reported back to the programmer doing the debugging is left
33 Provide an {\tt inOp} port and use opcode ports \cite{am25} to
34 effectively allow multiple independent ``debug streams''
36 Provide a way to programmatically read back the output of the debug
39 == Fleeterpreter ====================================================
40 public void service() {
41 if (box_in.dataReadyForShip())
42 ((Interpreter)getFleet()).debug(new BitVector(37).set(box_in.removeDataForShip()));
45 == FleetSim ==============================================================
47 == FPGA ==============================================================
57 wire [7:0] write_data;
66 OBUF obuf_cclk( .I( CCLK_int ), .O( CCLK ) );
67 IOBUF iobuf_d0( .I( D_O[0] ), .IO( D[0] ), .O( D_I[0] ), .T( D_T[0] ) );
68 IOBUF iobuf_d1( .I( D_O[1] ), .IO( D[1] ), .O( D_I[1] ), .T( D_T[1] ) );
69 IOBUF iobuf_d2( .I( D_O[2] ), .IO( D[2] ), .O( D_I[2] ), .T( D_T[2] ) );
70 IOBUF iobuf_d3( .I( D_O[3] ), .IO( D[3] ), .O( D_I[3] ), .T( D_T[3] ) );
71 IOBUF iobuf_d4( .I( D_O[4] ), .IO( D[4] ), .O( D_I[4] ), .T( D_T[4] ) );
72 IOBUF iobuf_d5( .I( D_O[5] ), .IO( D[5] ), .O( D_I[5] ), .T( D_T[5] ) );
73 IOBUF iobuf_d6( .I( D_O[6] ), .IO( D[6] ), .O( D_I[6] ), .T( D_T[6] ) );
74 IOBUF iobuf_d7( .I( D_O[7] ), .IO( D[7] ), .O( D_I[7] ), .T( D_T[7] ) );
76 // Clock buffer and reset
80 IBUFGDS_LVDS_25 diff_usrclk_buf( .I( Clkin_p ), .IB( Clkin_m ), .O( clk_fast ) );
82 wire clkdiv0_unbuffered;
85 // BUFG bufg1 (.I(clkdiv0_unbuffered), .O(clk_out));
86 // BUFG bufg1 (.I(clk_fast), .O(clk_out));
87 // BUFG bufg1 (.I(clk0_unbuffered), .O(clk_out));
88 BUFG bufg2 (.I(clk0_unbuffered), .O(clk0_fb));
93 BUFG bufg1 (.I(foo2), .O(clk_out));
95 always @(posedge clk_fast) begin
103 .CLKIN_PERIOD (10.0),
104 .DUTY_CYCLE_CORRECTION ("TRUE"),
105 .DLL_FREQUENCY_MODE ("LOW"),
106 .STARTUP_WAIT ("FALSE")
110 .CLK0 (clk0_unbuffered),
114 // BUFG GBUF_FOR_MUX_CLOCK (.I(clk_half), .O(clk_out));
115 // BUFG GBUF_FOR_MUX_CLOCK (.I(clk_fast), .O(clk_out));
119 FD rstr0( .D( 1'b0 ), .Q( rstr[0] ), .C( clk ) ); defparam rstr0.INIT = 1'b1;
120 FD rstr1( .D( rstr[0] ), .Q( rstr[1] ), .C( clk ) ); defparam rstr1.INIT = 1'b1;
121 FD rstr2( .D( rstr[1] ), .Q( rstr[2] ), .C( clk ) ); defparam rstr2.INIT = 1'b1;
122 FD rstr3( .D( rstr[2] ), .Q( rstr[3] ), .C( clk ) ); defparam rstr3.INIT = 1'b1;
123 assign User_Rst = |rstr;
126 .WrFifo_Din( write_data ),
127 .WrFifo_WrEn( write_enable ),
128 .WrFifo_Full( write_full ),
130 .RdFifo_Dout( read_data ),
131 .RdFifo_RdEn( read_enable ),
132 .RdFifo_Empty( read_empty ),
134 .User_Rst( User_Rst ),
136 .Sys_Rst( User_Rst ),
137 .Sys_Clk( clk_fast ),
147 wire data_to_host_full;
148 reg [7:0] data_to_host;
149 wire data_to_fleet_empty;
150 wire [7:0] data_to_fleet;
151 reg data_to_host_write_enable;
152 reg data_to_fleet_read_enable;
154 assign data_to_fleet = read_data;
155 assign read_enable = data_to_fleet_read_enable;
156 assign write_enable = data_to_host_write_enable;
157 assign write_data = data_to_host;
158 assign data_to_fleet_empty = read_empty;
159 assign data_to_host_full = write_full;
161 initial data_to_fleet_read_enable = 1;
162 initial data_to_host_write_enable = 0;
164 reg [7:0] force_reset;
165 assign rst_out = User_Rst || (force_reset!=0);
167 /// Common //////////////////////////////////////////////////////////////////////////////
172 reg [`WORDWIDTH-1:0] data_to_host_full_word;
176 assign out_d_ = out_d;
181 always @(posedge clk) begin
182 if (/*rst_in*/User_Rst) begin
193 data_to_host_write_enable <= 0;
194 if (force_reset == 1) begin
196 data_to_host_write_enable <= 1;
201 end else if (force_reset != 0) begin
202 force_reset <= force_reset-1;
203 end else if (count_out==0 && `in_full) begin
205 data_to_host_full_word <= in_d;
207 end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable && credits!=0) begin
208 data_to_host <= { 2'b0, data_to_host_full_word[5:0] };
209 data_to_host_full_word <= (data_to_host_full_word >> 6);
210 data_to_host_write_enable <= 1;
211 count_out <= count_out-1;
212 credits = credits - 1;
216 data_to_fleet_read_enable <= 0;
217 if (!data_to_fleet_empty && !data_to_fleet_read_enable) begin
219 // Note: if the switch fabric refuses to accept a new item,
220 // we can get deadlocked in a state where sending a reset
221 // code (2'b11) won't have any effect. Probably need to go
222 // back to using the break signal.
225 if (data_to_fleet[7:6] == 2'b00 && `out_empty) begin
226 data_to_fleet_read_enable <= 1;
227 out_d <= { out_d[43:0], data_to_fleet[5:0] };
228 if (count_in==9) begin
232 count_in <= count_in+1;
235 // command 1: flow control credit
236 end else if (data_to_fleet[7:6] == 2'b01) begin
237 data_to_fleet_read_enable <= 1;
238 credits = credits + data_to_fleet[5:0];
240 // command 3: reset (and echo back reset code)
241 end else if (data_to_fleet[7:6] == 2'b11) begin
242 data_to_fleet_read_enable <= 1;
243 data_to_host <= data_to_fleet;
254 == UCF =================================================================
256 ######################################
258 ######################################
260 NET Clkin_p LOC = AP21 | IOSTANDARD = LVDS_25;
261 NET Clkin_m LOC = AN21 | IOSTANDARD = LVDS_25;
263 NET rst_in LOC = H4 | IOSTANDARD = LVCMOS18;
265 NET clk_out PERIOD=50MHz;
266 //NET clk_out PERIOD=100MHz;
267 //NET clk_fast PERIOD=100MHz;
268 NET Clkin_p PERIOD=100MHz;
269 NET Clkin_m PERIOD=100MHz;
271 ######################################
272 ## SelectMAP interface pins
273 ######################################
275 NET D<0> LOC = AU9 | IOSTANDARD = LVCMOS25;
276 NET D<1> LOC = AV9 | IOSTANDARD = LVCMOS25;
277 NET D<2> LOC = AY9 | IOSTANDARD = LVCMOS25;
278 NET D<3> LOC = AW9 | IOSTANDARD = LVCMOS25;
279 NET D<4> LOC = AW34 | IOSTANDARD = LVCMOS25;
280 NET D<5> LOC = AY34 | IOSTANDARD = LVCMOS25;
281 NET D<6> LOC = AV34 | IOSTANDARD = LVCMOS25;
282 NET D<7> LOC = AU34 | IOSTANDARD = LVCMOS25;
284 NET RDWR_B LOC = AR34 | IOSTANDARD = LVCMOS25;
285 NET CS_B LOC = AT34 | IOSTANDARD = LVCMOS25;
286 NET INIT_B LOC = AR9 | IOSTANDARD = LVCMOS25;
287 NET CCLK LOC = C14 | IOSTANDARD = LVCMOS25;
294 == Test ================================================================
303 == Contributors =========================================================
304 Adam Megacz <megacz@cs.berkeley.edu>