3 == Ports ===========================================================
11 == Fleeterpreter ====================================================
12 private long[] mem = new long[0];
13 public long readMem(int addr) { return mem[addr]; }
14 public void writeMem(int addr, long val) {
15 if (addr >= mem.length) {
16 long[] newmem = new long[addr * 2 + 1];
17 System.arraycopy(mem, 0, newmem, 0, mem.length);
23 public void service() {
24 if (box_read_addr.dataReadyForShip() &&
25 box_read_data.readyForItemFromShip()) {
26 box_read_data.addDataFromShip((int)readMem(box_read_addr.removeDataForShip()));
29 if (box_write_addr.dataReadyForShip() &&
30 box_write_data.dataReadyForShip() &&
31 box_write_done.readyForItemFromShip()) {
32 writeMem(box_write_addr.removeDataForShip(),
33 box_write_data.removeDataForShip());
34 box_write_done.addTokenFromShip();
38 == ArchSim ==============================================================
40 == FPGA ==============================================================
42 `define BRAM_ADDR_WIDTH 14
43 `define BRAM_DATA_WIDTH `DATAWIDTH
44 `define BRAM_NAME dscratch_bram
48 read_addr_r, read_addr_a_, read_addr_d,
49 read_data_r_, read_data_a, read_data_d_,
50 write_addr_r, write_addr_a_, write_addr_d,
51 write_data_r, write_data_a_, write_data_d,
52 write_done_r_, write_done_a, write_done_d_
56 `input(read_addr_r, read_addr_a, read_addr_a_, [(`DATAWIDTH-1):0], read_addr_d)
57 `output(read_data_r, read_data_r_, read_data_a, [(`DATAWIDTH-1):0], read_data_d_)
58 `defreg(read_data_d_, [(`DATAWIDTH-1):0], read_data_d)
60 `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d)
61 `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
62 `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_)
63 `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d)
67 assign bram_we_ = bram_we;
68 wire [(`BRAM_DATA_WIDTH-1):0] bram_read_data;
69 reg [(`BRAM_ADDR_WIDTH-1):0] bram_write_address;
70 wire [(`BRAM_ADDR_WIDTH-1):0] bram_read_address;
71 reg [(`BRAM_DATA_WIDTH-1):0] bram_write_data;
72 wire [(`BRAM_DATA_WIDTH-1):0] bram_write_data_;
73 assign bram_write_data_ = bram_write_data;
74 `BRAM_NAME mybram(clk,
75 bram_we_, bram_write_address,
76 bram_read_address, bram_write_data_,
77 not_connected, bram_read_data);
81 reg have_read; initial have_read = 0;
82 reg read_pending; initial read_pending = 0;
83 assign bram_read_address = read_addr_d;
85 always @(posedge clk) begin
88 `onwrite(write_done_r, write_done_a)
92 if (!write_addr_r && write_addr_a) write_addr_a = 0;
93 if (!write_data_r && write_data_a) write_data_a = 0;
94 if (write_addr_r && write_data_r) begin
99 bram_write_address = write_addr_d;
100 bram_write_data = write_data_d;
104 if (read_pending) begin
107 read_data_d <= bram_read_data;
108 end else if (have_read) begin
109 `onwrite(read_data_r, read_data_a)
113 `onread(read_addr_r, read_addr_a)
114 // ======= Careful with the timing here! =====================
115 // We MUST capture bram_read_data on the very next clock since
116 // read_addr_d is free to change after the next clock
117 // ===========================================================
127 == Constants ========================================================
128 == TeX ==============================================================
130 == Contributors =========================================================
131 Adam Megacz <megacz@cs.berkeley.edu>