3 == Ports ===========================================================
10 == Fleeterpreter ====================================================
12 private long[] mem = new long[0];
13 public long readMem(int addr) { return mem[addr]; }
14 public void writeMem(int addr, long val) {
15 if (addr >= mem.length) {
16 long[] newmem = new long[addr * 2 + 1];
17 System.arraycopy(mem, 0, newmem, 0, mem.length);
23 public void dispatch(int addr, int size) {
24 for(int i=addr; i<addr+size; i++) {
25 Instruction instr = ((Interpreter)getFleet()).readInstruction(readMem(i));
26 ((Interpreter)getFleet()).dispatch(instr, i);
30 public void service() {
31 if (box_cbd.dataReadyForShip()) {
32 int val = box_cbd.removeDataForShip();
34 int size = val & 0x3f;
38 if (box_write_addr.dataReadyForShip() &&
39 box_write_data.dataReadyForShip() &&
40 box_write_done.readyForItemFromShip()) {
41 Interpreter f = (Interpreter)getFleet();
42 f.writeMem(box_write_addr.removeDataForShip(),
43 box_write_data.removeDataForShip());
44 box_write_done.addTokenFromShip();
48 public void boot(byte[] instructions) {
49 Interpreter fleet = (Interpreter)getFleet();
50 // load the iscratch and take note of the 0-address CBD
52 for(int i=0; i<instructions.length; i+=6) {
54 for(int j=0; j<6; j++)
55 word = (word << 8) | (instructions[i+j] & 0xff);
57 if (i==0) launch = word;
60 // dispatch the 0-address CBD
61 int base = (int)(launch >> 6);
62 base = base & ~(0xffffffff << 18);
63 int size = (int)launch;
64 size = size & ~(0xffffffff << 6);
68 == Constants ========================================================
69 == TeX ==============================================================
70 == ArchSim ==============================================================
71 == FPGA ==============================================================
73 `define BRAM_ADDR_WIDTH 14
74 `define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
75 `define BRAM_NAME iscratch_bram
79 write_addr_r, write_addr_a_, write_addr_d,
80 write_data_r, write_data_a_, write_data_d,
81 write_done_r_, write_done_a, write_done_d_,
83 preload_r, preload_a_, preload_d,
84 ihorn_r_, ihorn_a, ihorn_d_,
85 dhorn_r_, dhorn_a, dhorn_d_
89 `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d)
90 `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
91 `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_)
92 `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d)
94 `input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d)
95 `input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d)
96 `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
97 `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
98 `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
99 `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
102 initial ihorn_full = 0;
104 initial dhorn_full = 0;
106 initial command_valid = 0;
108 reg [(`BRAM_ADDR_WIDTH-1):0] preload_pos;
109 reg [(`BRAM_ADDR_WIDTH-1):0] preload_size;
110 initial preload_size = 0;
112 reg [(`BRAM_ADDR_WIDTH-1):0] current_instruction_read_from;
113 reg [(`BRAM_ADDR_WIDTH-1):0] temp_base;
114 reg [(`CODEBAG_SIZE_BITS-1):0] temp_size;
115 reg [(`BRAM_ADDR_WIDTH-1):0] cbd_base;
116 reg [(`CODEBAG_SIZE_BITS-1):0] cbd_size;
117 reg [(`CODEBAG_SIZE_BITS-1):0] cbd_pos;
118 reg [(`INSTRUCTION_WIDTH-1):0] command;
119 reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
122 reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
123 reg [(`DATAWIDTH-1):0] data;
126 reg [(`BRAM_ADDR_WIDTH-1):0] write_addr;
127 reg [(`BRAM_DATA_WIDTH-1):0] write_data;
129 wire [(`BRAM_DATA_WIDTH-1):0] ramread;
131 reg command_valid_read;
132 initial command_valid_read = 0;
135 initial launched = 0;
137 iscratch_bram mybram(clk, write_flag, write_addr, current_instruction_read_from, write_data, not_connected, ramread);
139 always @(posedge clk) begin
143 if (!write_addr_r && write_addr_a) write_addr_a = 0;
144 if (!write_data_r && write_data_a) write_data_a = 0;
146 if (command_valid_read) begin
147 command_valid_read <= 0;
150 end else if (send_done) begin
151 `onwrite(write_done_r, write_done_a)
155 end else if (write_addr_r && write_data_r) begin
160 write_addr <= write_addr_d;
161 write_data <= write_data_d;
163 end else if (ihorn_full && launched) begin
164 `onwrite(ihorn_r, ihorn_a)
168 end else if (dhorn_full) begin
169 `onwrite(dhorn_r, dhorn_a)
173 end else if (command_valid) begin
176 case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
183 temp = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
184 temp = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
185 data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
186 data[(`CODEBAG_SIZE_BITS-1):0] = command[(`CODEBAG_SIZE_BITS-1):0];
187 `packet_data(dhorn_d) <= temp;
188 `packet_dest(dhorn_d) <=
189 command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
193 `packet_data(dhorn_d) <= command[23:0];
194 `packet_dest(dhorn_d) <= command[34:24];
198 `packet_data(dhorn_d) <= command[23:0] + current_instruction_read_from;
199 `packet_dest(dhorn_d) <= command[34:24];
203 end else if (cbd_pos < cbd_size) begin
204 current_instruction_read_from <= cbd_base+cbd_pos;
205 command_valid_read <= 1;
206 cbd_pos <= cbd_pos + 1;
209 `onread(cbd_r, cbd_a)
211 cbd_size <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
212 cbd_base <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
215 `onread(preload_r, preload_a)
216 if (preload_size == 0) begin
217 preload_size <= preload_d;
218 end else if (!launched) begin
220 write_data <= preload_d;
221 write_addr <= preload_pos;
222 if (preload_pos == 0) begin
223 temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
224 temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
226 if ((preload_pos+1) == preload_size) begin
228 cbd_base <= temp_base;
229 cbd_size <= temp_size;
232 preload_pos <= preload_pos + 1;
244 == Contributors =========================================================
245 Adam Megacz <megacz@cs.berkeley.edu>