3 == Ports ===========================================================
7 data in: inAddr.readMany
8 data in: inAddr.writeMany
15 == Fleeterpreter ====================================================
16 private long[] mem = new long[0];
17 public long readMem(int addr) { return mem[addr]; }
18 public void writeMem(int addr, long val) {
19 if (addr >= mem.length) {
20 long[] newmem = new long[addr * 2 + 1];
21 System.arraycopy(mem, 0, newmem, 0, mem.length);
27 public void dispatch(int addr, int size) {
28 for(int i=addr; i<addr+size; i++) {
29 Instruction instr = ((Interpreter)getFleet()).readInstruction(readMem(i));
30 ((Interpreter)getFleet()).dispatch(instr, i);
34 public void boot(byte[] instructions) {
35 Interpreter fleet = (Interpreter)getFleet();
36 // load the iscratch and take note of the 0-address INCBD
38 for(int i=0; i<instructions.length; i+=6) {
40 for(int j=0; j<6; j++)
41 word = (word << 8) | (instructions[i+j] & 0xff);
43 if (i==0) launch = word;
46 // dispatch the 0-address INCBD
47 int base = (int)(launch >> 6);
48 base = base & ~(0xffffffff << 18);
49 int size = (int)launch;
50 size = size & ~(0xffffffff << 6);
54 private long stride = 0;
55 private long count = 0;
56 private long addr = 0;
57 private boolean writing = false;
59 public void service() {
60 if (box_inCBD.dataReadyForShip()) {
61 long val = box_inCBD.removeDataForShip();
63 long size = val & 0x3f;
64 dispatch((int)addr, (int)size);
66 if (count > 0 && writing) {
67 if (box_inData.dataReadyForShip() && box_out.readyForDataFromShip()) {
68 writeMem((int)addr, box_inData.removeDataForShip());
69 box_out.addDataFromShip(0);
74 } else if (count > 0 && !writing) {
75 if (box_out.readyForDataFromShip()) {
76 box_out.addDataFromShip(readMem((int)addr));
81 } else if (box_inAddr.dataReadyForShip() && box_out.readyForDataFromShip()) {
82 Packet packet = box_inAddr.peekPacketForShip();
83 if (packet.destination.getDestinationName().equals("read")) {
84 box_out.addDataFromShip(readMem((int)box_inAddr.removeDataForShip()));
85 } else if (packet.destination.getDestinationName().equals("write") && box_inData.dataReadyForShip()) {
86 writeMem((int)box_inAddr.removeDataForShip(),
87 box_inData.removeDataForShip());
88 box_out.addDataFromShip(0);
89 } else if (packet.destination.getDestinationName().equals("writeMany")
90 && box_inStride.dataReadyForShip()
91 && box_inCount.dataReadyForShip()) {
92 addr = box_inAddr.removeDataForShip();
93 stride = box_inStride.removeDataForShip();
94 count = box_inCount.removeDataForShip();
96 } else if (packet.destination.getDestinationName().equals("readMany")
97 && box_inStride.dataReadyForShip()
98 && box_inCount.dataReadyForShip()) {
99 addr = box_inAddr.removeDataForShip();
100 stride = box_inStride.removeDataForShip();
101 count = box_inCount.removeDataForShip();
107 == FleetSim ==============================================================
109 == FPGA ==============================================================
111 `define BRAM_ADDR_WIDTH 14
112 `define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
113 `define BRAM_NAME some_bram
116 module `BRAM_NAME(clk, we, a, dpra, di, spo, dpo);
119 input [(`BRAM_ADDR_WIDTH-1):0] a;
120 input [(`BRAM_ADDR_WIDTH-1):0] dpra;
121 input [(`BRAM_DATA_WIDTH-1):0] di;
122 output [(`BRAM_DATA_WIDTH-1):0] spo;
123 output [(`BRAM_DATA_WIDTH-1):0] dpo;
124 reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
125 reg [(`BRAM_ADDR_WIDTH-1):0] read_a;
126 reg [(`BRAM_ADDR_WIDTH-1):0] read_dpra;
127 always @(posedge clk) begin
133 assign spo = ram[read_a];
134 assign dpo = ram[read_dpra];
139 cbd_r, cbd_a_, cbd_d,
140 in_addr_r, in_addr_a_, in_addr_d,
141 write_data_r, write_data_a_, write_data_d,
142 stride_r, stride_a_, stride_d,
143 count_r, count_a_, count_d,
144 out_r_, out_a, out_d_,
145 preload_r, preload_a_, preload_d,
146 ihorn_r_, ihorn_a, ihorn_d_,
147 dhorn_r_, dhorn_a, dhorn_d_
151 `input(in_addr_r, in_addr_a, in_addr_a_, [(2+`DATAWIDTH-1):0], in_addr_d)
152 `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
153 `input(stride_r, stride_a, stride_a_, [(`DATAWIDTH-1):0], stride_d)
154 `input(count_r, count_a, count_a_, [(`DATAWIDTH-1):0], count_d)
155 `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
156 //`defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
158 `input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d)
159 `input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d)
160 `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
161 `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
162 `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
163 `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
166 initial ihorn_full = 0;
168 initial dhorn_full = 0;
170 initial command_valid = 0;
172 reg [(`BRAM_ADDR_WIDTH-1):0] preload_pos;
173 reg [(`BRAM_ADDR_WIDTH-1):0] preload_size;
174 initial preload_size = 0;
176 reg [(`BRAM_ADDR_WIDTH-1):0] current_instruction_read_from;
177 reg [(`BRAM_ADDR_WIDTH-1):0] temp_base;
178 reg [(`CODEBAG_SIZE_BITS-1):0] temp_size;
179 reg [(`BRAM_ADDR_WIDTH-1):0] cbd_base;
180 reg [(`CODEBAG_SIZE_BITS-1):0] cbd_size;
181 reg [(`CODEBAG_SIZE_BITS-1):0] cbd_pos;
182 reg [(`INSTRUCTION_WIDTH-1):0] command;
183 reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
187 reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
188 reg [(`DATAWIDTH-1):0] data;
191 reg [(`BRAM_ADDR_WIDTH-1):0] in_addr;
192 reg [(`BRAM_DATA_WIDTH-1):0] write_data;
194 wire [(`BRAM_DATA_WIDTH-1):0] ramread;
196 reg command_valid_read;
197 initial command_valid_read = 0;
200 initial launched = 0;
202 some_bram mybram(clk, write_flag, in_addr, current_instruction_read_from, write_data, not_connected, ramread);
203 assign out_d_ = ramread;
205 always @(posedge clk) begin
209 if (!in_addr_r && in_addr_a) in_addr_a = 0;
210 if (!write_data_r && write_data_a) write_data_a = 0;
212 if (command_valid_read) begin
213 command_valid_read <= 0;
216 end else if (send_done) begin
217 `onwrite(out_r, out_a)
221 end else if (send_read) begin
222 `onwrite(out_r, out_a)
226 end else if (in_addr_r && !in_addr_d[`DATAWIDTH]) begin
229 current_instruction_read_from <= in_addr_d[(`DATAWIDTH-1):0];
231 end else if (in_addr_r && in_addr_d[`DATAWIDTH] && write_data_r) begin
236 in_addr <= in_addr_d[(`DATAWIDTH-1):0];
237 write_data <= write_data_d;
239 end else if (ihorn_full && launched) begin
240 `onwrite(ihorn_r, ihorn_a)
244 end else if (dhorn_full) begin
245 `onwrite(dhorn_r, dhorn_a)
249 end else if (command_valid) begin
252 case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
259 temp = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
260 temp = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
261 data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
262 data[(`CODEBAG_SIZE_BITS-1):0] = command[(`CODEBAG_SIZE_BITS-1):0];
263 `packet_data(dhorn_d) <= temp;
264 `packet_dest(dhorn_d) <=
265 command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
269 `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] };
270 `packet_dest(dhorn_d) <= command[34:24];
274 `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] } + current_instruction_read_from;
275 `packet_dest(dhorn_d) <= command[34:24];
279 end else if (cbd_pos < cbd_size) begin
280 current_instruction_read_from <= cbd_base+cbd_pos;
281 command_valid_read <= 1;
282 cbd_pos <= cbd_pos + 1;
285 `onread(cbd_r, cbd_a)
287 cbd_size <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
288 cbd_base <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
291 `onread(preload_r, preload_a)
292 if (preload_size == 0) begin
293 preload_size <= preload_d;
294 end else if (!launched) begin
296 write_data <= preload_d;
297 in_addr <= preload_pos;
298 if (preload_pos == 0) begin
299 temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
300 temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
302 if ((preload_pos+1) == preload_size) begin
304 cbd_base <= temp_base;
305 cbd_size <= temp_size;
308 preload_pos <= preload_pos + 1;
320 == Test ==============================================================
326 // ships required in order to run this code
328 #ship memory : Memory
330 // instructions not in any codebag are part of the "root codebag"
331 // which is dispatched when the code is loaded
333 BOB: sendto memory.inCBD;
334 memory.inCBD: [*] take, deliver;
335 debug.in: [*] take, deliver;
338 // This codebag illustrates how to do a loop. Notice that this
339 // is actually an uncontrolled data emitter -- it could clog the
349 == Constants ========================================================
350 == TeX ==============================================================
353 TODO: multiple interfaces to a single memory
356 == Contributors =========================================================
357 Adam Megacz <megacz@cs.berkeley.edu>