ships/Memory.ship

   1 ship: Memory
   2
   3 == Ports ===========================================================
   4 data  in:    inCBD
   5 data  in:    inAddr.read
   6 data  in:    inAddr.write
   7 data  in:    inAddr.readMany
   8 data  in:    inAddr.writeMany
   9 data  in:    inData
  10 data  in:    inStride
  11 data  in:    inCount
  12
  13 data  out:   out
  14
  15 == Fleeterpreter ====================================================
  16     private long[] mem = new long[0];
  17     public long readMem(int addr) { return mem[addr]; }
  18     public void writeMem(int addr, long val) {
  19         if (addr >= mem.length) {
  20             long[] newmem = new long[addr * 2 + 1];
  21             System.arraycopy(mem, 0, newmem, 0, mem.length);
  22             mem = newmem;
  23         }
  24         mem[addr] = val;
  25     }
  26
  27     public void dispatch(int addr, int size) {
  28         for(int i=addr; i<addr+size; i++) {
  29             Instruction instr = ((Interpreter)getFleet()).readInstruction(readMem(i));
  30             ((Interpreter)getFleet()).dispatch(instr, i);
  31         }
  32     }
  33
  34     public void boot(byte[] instructions) {
  35         Interpreter fleet = (Interpreter)getFleet();
  36         // load the iscratch and take note of the 0-address INCBD
  37         long launch = 0;
  38         for(int i=0; i<instructions.length; i+=6) {
  39             long word = 0;
  40             for(int j=0; j<6; j++)
  41                 word = (word << 8) | (instructions[i+j] & 0xff);
  42             writeMem(i/6, word);
  43             if (i==0) launch = word;
  44         }
  45
  46         // dispatch the 0-address INCBD
  47         int base = (int)(launch >> 6);
  48         base = base & ~(0xffffffff << 18);
  49         int size = (int)launch;
  50         size = size & ~(0xffffffff <<  6);
  51         dispatch(base, size);
  52     }
  53
  54     public void service() {
  55         if (box_inCBD.dataReadyForShip()) {
  56             long val = box_inCBD.removeDataForShip();
  57             long addr = val >> 6;
  58             long size = val & 0x3f;
  59             dispatch((int)addr, (int)size);
  60         }
  61         if (box_inAddr.dataReadyForShip() && box_out.readyForItemFromShip()) {
  62             Packet packet = box_inAddr.peekPacketForShip();
  63             if (packet.destination.getDestinationName().equals("read")) {
  64                 box_out.addDataFromShip(readMem((int)box_inAddr.removeDataForShip()));
  65             } else if (packet.destination.getDestinationName().equals("write") && box_inData.dataReadyForShip()) {
  66                 writeMem((int)box_inAddr.removeDataForShip(),
  67                          box_inData.removeDataForShip());
  68                 box_out.addDataFromShip(0);
  69             }
  70         }
  71     }
  72
  73 == FleetSim ==============================================================
  74
  75 == FPGA ==============================================================
  76 `include "macros.v"
  77 `define BRAM_ADDR_WIDTH 14
  78 `define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
  79 `define BRAM_NAME some_bram
  80 `include "bram.inc"
  81
  82 module memory (clk,
  83                cbd_r,          cbd_a_,         cbd_d,
  84                in_addr_r,      in_addr_a_,     in_addr_d,
  85                write_data_r,   write_data_a_,  write_data_d,
  86                stride_r,       stride_a_,      stride_d,
  87                count_r,        count_a_,       count_d,
  88                out_r_,         out_a,          out_d_,
  89                preload_r,      preload_a_,     preload_d,
  90                ihorn_r_,       ihorn_a,        ihorn_d_,
  91                dhorn_r_,       dhorn_a,        dhorn_d_
  92               );
  93
  94   input  clk;
  95   `input(in_addr_r,      in_addr_a,     in_addr_a_,     [(`DATAWIDTH-1):0],         in_addr_d)
  96   `input(write_data_r,   write_data_a,  write_data_a_,  [(`DATAWIDTH-1):0],         write_data_d)
  97   `input(stride_r,       stride_a,      stride_a_,      [(`DATAWIDTH-1):0],         stride_d)
  98   `input(count_r,        count_a,       count_a_,       [(`DATAWIDTH-1):0],         count_d)
  99   `output(out_r,  out_r_, out_a,   [(`DATAWIDTH-1):0],         out_d_)
 100   `defreg(out_d_,                                [(`DATAWIDTH-1):0],         out_d)
 101
 102   `input(preload_r,      preload_a,     preload_a_,     [(`DATAWIDTH-1):0],         preload_d)
 103   `input(cbd_r,          cbd_a,         cbd_a_,         [(`DATAWIDTH-1):0],         cbd_d)
 104   `output(ihorn_r,       ihorn_r_,      ihorn_a,        [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
 105   `defreg(ihorn_d_,                                     [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
 106   `output(dhorn_r,       dhorn_r_,      dhorn_a,        [(`PACKET_WIDTH-1):0],      dhorn_d_)
 107   `defreg(dhorn_d_,                                     [(`PACKET_WIDTH-1):0],      dhorn_d)
 108
 109   reg ihorn_full;
 110   initial ihorn_full = 0;
 111   reg dhorn_full;
 112   initial dhorn_full = 0;
 113   reg command_valid;
 114   initial command_valid = 0;
 115
 116   reg [(`BRAM_ADDR_WIDTH-1):0]    preload_pos;
 117   reg [(`BRAM_ADDR_WIDTH-1):0]    preload_size;
 118   initial preload_size = 0;
 119
 120   reg [(`BRAM_ADDR_WIDTH-1):0]    current_instruction_read_from;
 121   reg [(`BRAM_ADDR_WIDTH-1):0]    temp_base;
 122   reg [(`CODEBAG_SIZE_BITS-1):0]  temp_size;
 123   reg [(`BRAM_ADDR_WIDTH-1):0]    cbd_base;
 124   reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_size;
 125   reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_pos;
 126   reg [(`INSTRUCTION_WIDTH-1):0]  command;
 127   reg [(`BRAM_DATA_WIDTH-1):0]    ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
 128   reg                             send_done;
 129
 130   reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
 131   reg [(`DATAWIDTH-1):0]                                     data;
 132
 133   reg                             write_flag;
 134   reg [(`BRAM_ADDR_WIDTH-1):0]    in_addr;
 135   reg [(`BRAM_DATA_WIDTH-1):0]    write_data;
 136
 137   wire [(`BRAM_DATA_WIDTH-1):0]   ramread;
 138
 139   reg command_valid_read;
 140   initial command_valid_read = 0;
 141
 142   reg launched;
 143   initial launched = 0;
 144
 145   some_bram mybram(clk, write_flag, in_addr, current_instruction_read_from, write_data, not_connected, ramread);
 146
 147   always @(posedge clk) begin
 148
 149     write_flag <= 0;
 150
 151     if (!in_addr_r && in_addr_a) in_addr_a = 0;
 152     if (!write_data_r && write_data_a) write_data_a = 0;
 153
 154     if (command_valid_read) begin
 155       command_valid_read  <= 0;
 156       command_valid       <= 1;
 157
 158     end else  if (send_done) begin
 159       `onwrite(out_r, out_a)
 160         send_done <= 0;
 161       end
 162
 163     end else if (in_addr_r && write_data_r) begin
 164       in_addr_a       = 1;
 165       write_data_a       = 1;
 166       send_done         <= 1;
 167       write_flag        <= 1;
 168       in_addr        <= in_addr_d;
 169       write_data        <= write_data_d;
 170
 171     end else if (ihorn_full && launched) begin
 172       `onwrite(ihorn_r, ihorn_a)
 173         ihorn_full <= 0;
 174       end
 175
 176     end else if (dhorn_full) begin
 177       `onwrite(dhorn_r, dhorn_a)
 178         dhorn_full <= 0;
 179       end
 180
 181     end else if (command_valid) begin
 182       command_valid <= 0;
 183       command = ramread;
 184       case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
 185         0: begin
 186             ihorn_full  <= 1;
 187             ihorn_d     <= command;
 188            end
 189         1: begin
 190             dhorn_full  <= 1;
 191             temp    = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
 192             temp    = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
 193             data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
 194             data[(`CODEBAG_SIZE_BITS-1):0]            = command[(`CODEBAG_SIZE_BITS-1):0];
 195             `packet_data(dhorn_d) <= temp;
 196             `packet_dest(dhorn_d) <=
 197                   command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
 198            end
 199         2: begin
 200             dhorn_full            <= 1;
 201             `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] };
 202             `packet_dest(dhorn_d) <= command[34:24];
 203            end
 204         3: begin
 205             dhorn_full            <= 1;
 206             `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] } + current_instruction_read_from;
 207             `packet_dest(dhorn_d) <= command[34:24];
 208            end
 209       endcase
 210
 211     end else if (cbd_pos < cbd_size) begin
 212       current_instruction_read_from <= cbd_base+cbd_pos;
 213       command_valid_read            <= 1;
 214       cbd_pos                       <= cbd_pos + 1;
 215
 216     end else begin
 217       `onread(cbd_r, cbd_a)
 218         cbd_pos       <= 0;
 219         cbd_size      <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
 220         cbd_base      <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
 221
 222       end else begin
 223         `onread(preload_r, preload_a)
 224           if (preload_size == 0) begin
 225             preload_size     <= preload_d;
 226           end else if (!launched) begin
 227             write_flag <= 1;
 228             write_data <= preload_d;
 229             in_addr <= preload_pos;
 230             if (preload_pos == 0) begin
 231               temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
 232               temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
 233             end
 234             if ((preload_pos+1) == preload_size) begin
 235               cbd_pos  <= 0;
 236               cbd_base <= temp_base;
 237               cbd_size <= temp_size;
 238               launched <= 1;
 239             end
 240             preload_pos      <= preload_pos + 1;
 241           end
 242         end
 243       end
 244     end
 245   end
 246 endmodule
 247
 248
 249
 250
 251
 252
 253
 254 == Constants ========================================================
 255 == TeX ==============================================================
 256
 257 == Contributors =========================================================
 258 Adam Megacz <megacz@cs.berkeley.edu>