3 == Ports ===========================================================
13 == Fleeterpreter ====================================================
14 private long[] mem = new long[0];
15 public long readMem(int addr) { return mem[addr]; }
16 public void writeMem(int addr, long val) {
17 if (addr >= mem.length) {
18 long[] newmem = new long[addr * 2 + 1];
19 System.arraycopy(mem, 0, newmem, 0, mem.length);
25 public void dispatch(int addr, int size) {
26 for(int i=addr; i<addr+size; i++) {
27 Instruction instr = ((Interpreter)getFleet()).readInstruction(readMem(i));
28 ((Interpreter)getFleet()).dispatch(instr, i);
32 public void boot(byte[] instructions) {
33 Interpreter fleet = (Interpreter)getFleet();
34 // load the iscratch and take note of the 0-address INCBD
36 for(int i=0; i<instructions.length; i+=6) {
38 for(int j=0; j<6; j++)
39 word = (word << 8) | (instructions[i+j] & 0xff);
41 if (i==0) launch = word;
44 // dispatch the 0-address INCBD
45 int base = (int)(launch >> 6);
46 base = base & ~(0xffffffff << 18);
47 int size = (int)launch;
48 size = size & ~(0xffffffff << 6);
52 private long stride = 0;
53 private long count = 0;
54 private long addr = 0;
55 private boolean writing = false;
57 public void service() {
58 if (box_inCBD.dataReadyForShip()) {
59 long val = box_inCBD.removeDataForShip();
61 long size = val & 0x3f;
62 dispatch((int)addr, (int)size);
64 if (count > 0 && writing) {
65 if (box_inDataWrite.dataReadyForShip() && box_out.readyForDataFromShip()) {
66 writeMem((int)addr, box_inDataWrite.removeDataForShip());
67 box_out.addDataFromShip(0);
72 } else if (count > 0 && !writing) {
73 if (box_out.readyForDataFromShip()) {
74 box_out.addDataFromShip(readMem((int)addr));
79 } else if (box_inAddrRead.dataReadyForShip() && box_out.readyForDataFromShip()) {
80 Packet packet = box_inAddrRead.peekPacketForShip();
81 if (packet.destination.getDestinationName().equals("read")) {
82 box_out.addDataFromShip(readMem((int)box_inAddrRead.removeDataForShip()));
83 } else if (packet.destination.getDestinationName().equals("write") && box_inDataWrite.dataReadyForShip()) {
84 writeMem((int)box_inAddrRead.removeDataForShip(),
85 box_inDataWrite.removeDataForShip());
86 box_out.addDataFromShip(0);
87 } else if (packet.destination.getDestinationName().equals("writeMany")
88 && box_inStride.dataReadyForShip()
89 && box_inCount.dataReadyForShip()) {
90 addr = box_inAddrRead.removeDataForShip();
91 stride = box_inStride.removeDataForShip();
92 count = box_inCount.removeDataForShip();
94 } else if (packet.destination.getDestinationName().equals("readMany")
95 && box_inStride.dataReadyForShip()
96 && box_inCount.dataReadyForShip()) {
97 addr = box_inAddrRead.removeDataForShip();
98 stride = box_inStride.removeDataForShip();
99 count = box_inCount.removeDataForShip();
105 == FleetSim ==============================================================
107 == FPGA ==============================================================
109 `define BRAM_ADDR_WIDTH 14
110 `define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
111 `define BRAM_NAME some_bram
114 module `BRAM_NAME(clk, we, a, dpra, di, spo, dpo);
117 input [(`BRAM_ADDR_WIDTH-1):0] a;
118 input [(`BRAM_ADDR_WIDTH-1):0] dpra;
119 input [(`BRAM_DATA_WIDTH-1):0] di;
120 output [(`BRAM_DATA_WIDTH-1):0] spo;
121 output [(`BRAM_DATA_WIDTH-1):0] dpo;
122 reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
123 reg [(`BRAM_ADDR_WIDTH-1):0] read_a;
124 reg [(`BRAM_ADDR_WIDTH-1):0] read_dpra;
125 always @(posedge clk) begin
131 assign spo = ram[read_a];
132 assign dpo = ram[read_dpra];
137 cbd_r, cbd_a_, cbd_d,
138 in_addr_r, in_addr_a_, in_addr_d,
139 write_addr_r, write_addr_a_, write_addr_d,
140 write_data_r, write_data_a_, write_data_d,
141 stride_r, stride_a_, stride_d,
142 count_r, count_a_, count_d,
143 out_r_, out_a, out_d_,
144 preload_r, preload_a_, preload_d,
145 ihorn_r_, ihorn_a, ihorn_d_,
146 dhorn_r_, dhorn_a, dhorn_d_
150 `input(in_addr_r, in_addr_a, in_addr_a_, [(2+`DATAWIDTH-1):0], in_addr_d)
151 `input(write_addr_r, write_addr_a, write_addr_a_, [(2+`DATAWIDTH-1):0], write_addr_d)
152 `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
153 `input(stride_r, stride_a, stride_a_, [(`DATAWIDTH-1):0], stride_d)
154 `input(count_r, count_a, count_a_, [(`DATAWIDTH-1):0], count_d)
155 `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
156 `input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d)
157 `input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d)
158 `output(ihorn_r, ihorn_r_, ihorn_a, [(`PACKET_WIDTH-1):0], ihorn_d_)
159 `defreg(ihorn_d_, [(`PACKET_WIDTH-1):0], ihorn_d)
160 `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
161 `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
164 initial ihorn_full = 0;
166 initial dhorn_full = 0;
168 initial command_valid = 0;
170 reg [(`BRAM_ADDR_WIDTH-1):0] preload_pos;
171 reg [(`BRAM_ADDR_WIDTH-1):0] preload_size;
172 initial preload_size = 0;
174 reg [(`BRAM_ADDR_WIDTH-1):0] current_instruction_read_from;
175 reg [(`BRAM_ADDR_WIDTH-1):0] temp_base;
176 reg [(`CODEBAG_SIZE_BITS-1):0] temp_size;
177 reg [(`BRAM_ADDR_WIDTH-1):0] cbd_base;
178 reg [(`CODEBAG_SIZE_BITS-1):0] cbd_size;
179 reg [(`CODEBAG_SIZE_BITS-1):0] cbd_pos;
180 reg [(`INSTRUCTION_WIDTH-1):0] command;
181 reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
185 reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
186 reg [(`DATAWIDTH-1):0] data;
189 reg [(`BRAM_ADDR_WIDTH-1):0] in_addr;
190 reg [(`BRAM_DATA_WIDTH-1):0] write_data;
192 wire [(`BRAM_DATA_WIDTH-1):0] ramread;
194 reg command_valid_read;
195 initial command_valid_read = 0;
198 initial launched = 0;
200 some_bram mybram(clk, write_flag, in_addr, current_instruction_read_from, write_data, not_connected, ramread);
201 assign out_d_ = ramread;
203 always @(posedge clk) begin
207 if (!in_addr_r && in_addr_a) in_addr_a = 0;
208 if (!write_data_r && write_data_a) write_data_a = 0;
209 if (!write_addr_r && write_addr_a) write_addr_a = 0;
211 if (command_valid_read) begin
212 command_valid_read <= 0;
215 end else if (send_done) begin
216 `onwrite(out_r, out_a)
220 end else if (send_read) begin
221 `onwrite(out_r, out_a)
225 end else if (in_addr_r) begin
228 current_instruction_read_from <= in_addr_d[(`DATAWIDTH-1):0];
230 end else if (write_addr_r && write_data_r) begin
235 in_addr <= write_addr_d[(`DATAWIDTH-1):0];
236 write_data <= write_data_d;
238 end else if (ihorn_full && launched) begin
239 `onwrite(ihorn_r, ihorn_a)
243 end else if (dhorn_full) begin
244 `onwrite(dhorn_r, dhorn_a)
248 end else if (command_valid) begin
252 `packet_data(ihorn_d) <= `instruction_data(command);
253 `packet_dest(ihorn_d) <= `instruction_dest(command);
255 end else if (cbd_pos < cbd_size) begin
256 current_instruction_read_from <= cbd_base+cbd_pos;
257 command_valid_read <= 1;
258 cbd_pos <= cbd_pos + 1;
261 `onread(cbd_r, cbd_a)
263 cbd_size <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
264 cbd_base <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
267 `onread(preload_r, preload_a)
268 if (preload_size == 0) begin
269 preload_size <= preload_d;
270 end else if (!launched) begin
272 write_data <= preload_d;
273 in_addr <= preload_pos;
274 if (preload_pos == 0) begin
275 temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
276 temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
278 if ((preload_pos+1) == preload_size) begin
280 cbd_base <= temp_base;
281 cbd_size <= temp_size;
284 preload_pos <= preload_pos + 1;
296 == Test ==============================================================
302 // ships required in order to run this code
304 #ship memory : Memory
306 // instructions not in any codebag are part of the "root codebag"
307 // which is dispatched when the code is loaded
321 == Constants ========================================================
322 == TeX ==============================================================
325 TODO: multiple interfaces to a single memory
328 == Contributors =========================================================
329 Adam Megacz <megacz@cs.berkeley.edu>