3 == Ports ===========================================================
7 data in: inAddr.readMany
8 data in: inAddr.writeMany
15 == Fleeterpreter ====================================================
16 private long[] mem = new long[0];
17 public long readMem(int addr) { return mem[addr]; }
18 public void writeMem(int addr, long val) {
19 if (addr >= mem.length) {
20 long[] newmem = new long[addr * 2 + 1];
21 System.arraycopy(mem, 0, newmem, 0, mem.length);
27 public void dispatch(int addr, int size) {
28 for(int i=addr; i<addr+size; i++) {
29 Instruction instr = ((Interpreter)getFleet()).readInstruction(readMem(i));
30 ((Interpreter)getFleet()).dispatch(instr, i);
34 public void boot(byte[] instructions) {
35 Interpreter fleet = (Interpreter)getFleet();
36 // load the iscratch and take note of the 0-address INCBD
38 for(int i=0; i<instructions.length; i+=6) {
40 for(int j=0; j<6; j++)
41 word = (word << 8) | (instructions[i+j] & 0xff);
43 if (i==0) launch = word;
46 // dispatch the 0-address INCBD
47 int base = (int)(launch >> 6);
48 base = base & ~(0xffffffff << 18);
49 int size = (int)launch;
50 size = size & ~(0xffffffff << 6);
54 private long stride = 0;
55 private long count = 0;
56 private long addr = 0;
57 private boolean writing = false;
59 public void service() {
60 if (box_inCBD.dataReadyForShip()) {
61 long val = box_inCBD.removeDataForShip();
63 long size = val & 0x3f;
64 dispatch((int)addr, (int)size);
66 if (count > 0 && writing) {
67 if (box_inData.dataReadyForShip() && box_out.readyForDataFromShip()) {
68 writeMem((int)addr, box_inData.removeDataForShip());
69 box_out.addDataFromShip(0);
74 } else if (count > 0 && !writing) {
75 if (box_out.readyForDataFromShip()) {
76 box_out.addDataFromShip(readMem((int)addr));
81 } else if (box_inAddr.dataReadyForShip() && box_out.readyForDataFromShip()) {
82 Packet packet = box_inAddr.peekPacketForShip();
83 if (packet.destination.getDestinationName().equals("read")) {
84 box_out.addDataFromShip(readMem((int)box_inAddr.removeDataForShip()));
85 } else if (packet.destination.getDestinationName().equals("write") && box_inData.dataReadyForShip()) {
86 writeMem((int)box_inAddr.removeDataForShip(),
87 box_inData.removeDataForShip());
88 box_out.addDataFromShip(0);
89 } else if (packet.destination.getDestinationName().equals("writeMany")
90 && box_inStride.dataReadyForShip()
91 && box_inCount.dataReadyForShip()) {
92 addr = box_inAddr.removeDataForShip();
93 stride = box_inStride.removeDataForShip();
94 count = box_inCount.removeDataForShip();
96 } else if (packet.destination.getDestinationName().equals("readMany")
97 && box_inStride.dataReadyForShip()
98 && box_inCount.dataReadyForShip()) {
99 addr = box_inAddr.removeDataForShip();
100 stride = box_inStride.removeDataForShip();
101 count = box_inCount.removeDataForShip();
107 == FleetSim ==============================================================
109 == FPGA ==============================================================
111 `define BRAM_ADDR_WIDTH 14
112 `define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
113 `define BRAM_NAME some_bram
117 cbd_r, cbd_a_, cbd_d,
118 in_addr_r, in_addr_a_, in_addr_d,
119 write_data_r, write_data_a_, write_data_d,
120 stride_r, stride_a_, stride_d,
121 count_r, count_a_, count_d,
122 out_r_, out_a, out_d_,
123 preload_r, preload_a_, preload_d,
124 ihorn_r_, ihorn_a, ihorn_d_,
125 dhorn_r_, dhorn_a, dhorn_d_
129 `input(in_addr_r, in_addr_a, in_addr_a_, [(2+`DATAWIDTH-1):0], in_addr_d)
130 `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
131 `input(stride_r, stride_a, stride_a_, [(`DATAWIDTH-1):0], stride_d)
132 `input(count_r, count_a, count_a_, [(`DATAWIDTH-1):0], count_d)
133 `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
134 //`defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
136 `input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d)
137 `input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d)
138 `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
139 `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
140 `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
141 `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
144 initial ihorn_full = 0;
146 initial dhorn_full = 0;
148 initial command_valid = 0;
150 reg [(`BRAM_ADDR_WIDTH-1):0] preload_pos;
151 reg [(`BRAM_ADDR_WIDTH-1):0] preload_size;
152 initial preload_size = 0;
154 reg [(`BRAM_ADDR_WIDTH-1):0] current_instruction_read_from;
155 reg [(`BRAM_ADDR_WIDTH-1):0] temp_base;
156 reg [(`CODEBAG_SIZE_BITS-1):0] temp_size;
157 reg [(`BRAM_ADDR_WIDTH-1):0] cbd_base;
158 reg [(`CODEBAG_SIZE_BITS-1):0] cbd_size;
159 reg [(`CODEBAG_SIZE_BITS-1):0] cbd_pos;
160 reg [(`INSTRUCTION_WIDTH-1):0] command;
161 reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
165 reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
166 reg [(`DATAWIDTH-1):0] data;
169 reg [(`BRAM_ADDR_WIDTH-1):0] in_addr;
170 reg [(`BRAM_DATA_WIDTH-1):0] write_data;
172 wire [(`BRAM_DATA_WIDTH-1):0] ramread;
174 reg command_valid_read;
175 initial command_valid_read = 0;
178 initial launched = 0;
180 some_bram mybram(clk, write_flag, in_addr, current_instruction_read_from, write_data, not_connected, ramread);
181 assign out_d_ = ramread;
183 always @(posedge clk) begin
187 if (!in_addr_r && in_addr_a) in_addr_a = 0;
188 if (!write_data_r && write_data_a) write_data_a = 0;
190 if (command_valid_read) begin
191 command_valid_read <= 0;
194 end else if (send_done) begin
195 `onwrite(out_r, out_a)
199 end else if (send_read) begin
200 `onwrite(out_r, out_a)
204 end else if (in_addr_r && !in_addr_d[`DATAWIDTH]) begin
207 current_instruction_read_from <= in_addr_d[(`DATAWIDTH-1):0];
209 end else if (in_addr_r && in_addr_d[`DATAWIDTH] && write_data_r) begin
214 in_addr <= in_addr_d[(`DATAWIDTH-1):0];
215 write_data <= write_data_d;
217 end else if (ihorn_full && launched) begin
218 `onwrite(ihorn_r, ihorn_a)
222 end else if (dhorn_full) begin
223 `onwrite(dhorn_r, dhorn_a)
227 end else if (command_valid) begin
230 case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
237 temp = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
238 temp = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
239 data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
240 data[(`CODEBAG_SIZE_BITS-1):0] = command[(`CODEBAG_SIZE_BITS-1):0];
241 `packet_data(dhorn_d) <= temp;
242 `packet_dest(dhorn_d) <=
243 command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
247 `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] };
248 `packet_dest(dhorn_d) <= command[34:24];
252 `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] } + current_instruction_read_from;
253 `packet_dest(dhorn_d) <= command[34:24];
257 end else if (cbd_pos < cbd_size) begin
258 current_instruction_read_from <= cbd_base+cbd_pos;
259 command_valid_read <= 1;
260 cbd_pos <= cbd_pos + 1;
263 `onread(cbd_r, cbd_a)
265 cbd_size <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
266 cbd_base <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
269 `onread(preload_r, preload_a)
270 if (preload_size == 0) begin
271 preload_size <= preload_d;
272 end else if (!launched) begin
274 write_data <= preload_d;
275 in_addr <= preload_pos;
276 if (preload_pos == 0) begin
277 temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
278 temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
280 if ((preload_pos+1) == preload_size) begin
282 cbd_base <= temp_base;
283 cbd_size <= temp_size;
286 preload_pos <= preload_pos + 1;
298 == Test ==============================================================
304 // ships required in order to run this code
306 #ship memory : Memory
308 // instructions not in any codebag are part of the "root codebag"
309 // which is dispatched when the code is loaded
311 BOB: sendto memory.inCBD;
312 memory.inCBD: [*] take, deliver;
313 debug.in: [*] take, deliver;
316 // This codebag illustrates how to do a loop. Notice that this
317 // is actually an uncontrolled data emitter -- it could clog the
327 == Constants ========================================================
328 == TeX ==============================================================
331 TODO: multiple interfaces to a single memory
334 == Contributors =========================================================
335 Adam Megacz <megacz@cs.berkeley.edu>