1 package edu.berkeley.fleet.fpga;
2 import edu.berkeley.fleet.fpga.*;
3 import edu.berkeley.fleet.api.*;
4 import edu.berkeley.fleet.two.*;
5 import edu.berkeley.fleet.*;
6 import java.lang.reflect.*;
7 import edu.berkeley.sbp.chr.*;
8 import edu.berkeley.sbp.misc.*;
9 import edu.berkeley.sbp.meta.*;
10 import edu.berkeley.sbp.util.*;
13 import edu.berkeley.fleet.two.*;
14 import static edu.berkeley.fleet.two.FleetTwoFleet.*;
15 import static edu.berkeley.fleet.fpga.verilog.Verilog.*;
16 import static edu.berkeley.fleet.fpga.verilog.Verilog.PercolatedPort;
19 public class Fpga extends FleetTwoFleet {
24 public LinkedHashMap<String,FpgaShip> ships = new LinkedHashMap<String,FpgaShip>();
25 public Iterator<Ship> iterator() { return (Iterator<Ship>)(Object)ships.values().iterator(); }
27 public Ship getShip(String type, int ordinal) {
29 if (s.getType().equals(type))
35 public static void main(String[] s) throws Exception {
36 new Fpga(new Module("main")).top.dump(s[0]);
39 pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/timescale.v")));
40 pw.println("`timescale 1ns / 10ps");
43 pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/vram.v")));
44 pw.println("`define BRAM_ADDR_WIDTH 19");
45 pw.println("`define BRAM_DATA_WIDTH 3");
46 pw.println("`define BRAM_SIZE (640*480)");
47 pw.println("`define BRAM_NAME vram");
48 pw.println("`include \"bram.inc\"");
52 public Module getVerilogModule() { return top; }
54 public FleetProcess run(Instruction[] instructions) {
56 return new Client(this, "none", instructions);
57 } catch (Exception e) { throw new RuntimeException(e); }
60 protected BitVector getDestAddr(Path path) {
61 return ((FpgaPath)path).toBitVector();
64 // Setup //////////////////////////////////////////////////////////////////////////////
66 Ship createShip(String type) throws IOException {
67 ShipDescription sd = new ShipDescription(type, new BufferedReader(new InputStreamReader(new FileInputStream("ships/"+type+".ship"))));
69 for(Ship ship : ships.values()) if (ship.getType().equals(type)) count++;
70 String name = type+count;
71 FpgaShip ship = new FpgaShip(this, sd);
72 ships.put(name, ship);
76 public Fpga() throws Exception { this(new Module("main")); }
77 public Fpga(Module top) throws Exception {
79 debugShip = createShip("Debug");
82 //boolean small = false;
85 for(int i=0; i<1; i++) createShip("Memory");
86 for(int i=0; i<2; i++) createShip("Fifo");
87 for(int i=0; i<2; i++) createShip("Alu");
88 createShip("Counter");
89 createShip("CarrySaveAdder");
90 createShip("Rotator");
94 for(int i=0; i<3; i++) createShip("Memory");
95 for(int i=0; i<3; i++) createShip("Alu");
96 for(int i=0; i<2; i++) createShip("Fifo");
97 for(int i=0; i<14; i++) createShip("Counter");
99 // "really big" configuration: 138 docks
100 for(int i=0; i<10; i++) createShip("Alu");
101 createShip("CarrySaveAdder");
102 createShip("Rotator");
105 //createShip("DRAM");
106 //createShip("Video");
110 new Module.InstantiatedModule(top, new FifoModule(8, WIDTH_WORD));
112 ArrayList dests = new ArrayList<FabricElement>();
113 ArrayList sources = new ArrayList<FabricElement>();
114 for(FpgaShip ship : (Iterable<FpgaShip>)(Object)this) {
115 for(Dock port : ship) {
116 if (port.isInputDock()) {
117 sources.add(((FpgaDock)port));
118 dests.add(port.getInstructionDestination());
119 dests.add(port.getDataDestination());
121 sources.add(((FpgaDock)port));
122 dests.add(port.getInstructionDestination());
123 dests.add(port.getDataDestination());
126 for(Module.SourcePort sp0 : ship.docklessPorts.values()) {
127 final Module.SourcePort sp = sp0;
128 sources.add(new FabricElement.AbstractFabricElement() {
129 private FabricElement upstream;
130 public FpgaPath getPath(FpgaDestination dest, BitVector signal) { return upstream.getPath(dest, signal); }
131 public void addOutput(FabricElement out, Module.Port outPort) {
133 sp.connect((Module.SinkPort)outPort);
138 FabricElement top_horn = mkNode((FabricElement[])dests.toArray(new FabricElement[0]), true);
139 mkNode((FabricElement[])sources.toArray(new FabricElement[0]), false)
140 .addOutput(top_horn, top_horn.getInputPort());
143 public FabricElement mkNode(FabricElement[] ports, boolean is_horn) { return mkNode(ports, is_horn, 0, ports.length); }
144 public FabricElement mkNode(FabricElement[] ports, boolean is_horn, int start, int end) {
146 case 0: throw new RuntimeException("this should never happen");
147 case 1: return ports[start];
149 FabricElement leftPort = mkNode(ports, is_horn, start, (end+start)/2);
150 FabricElement rightPort = mkNode(ports, is_horn, (end+start)/2, end);
152 ? new HornModule.HornInstance(this, top, leftPort, rightPort)
153 : new FunnelModule.FunnelInstance(this, top, leftPort, rightPort);
159 // Expand //////////////////////////////////////////////////////////////////////////////
161 public void expand(ShipDescription sd) {
163 if (sd.getSection("fpga")==null) return;
164 String filename = sd.getName().toLowerCase();
165 File outf = new File("build/fpga/"+filename+".v");
166 new File(outf.getParent()).mkdirs();
167 System.err.println("writing to " + outf);
168 FileOutputStream out = new FileOutputStream(outf);
169 PrintWriter pw = new PrintWriter(out);
171 pw.println("`define WORDWIDTH "+WIDTH_WORD);
172 pw.println("`define CODEBAG_SIZE_BITS "+CBD_SIZE.valmaskwidth);
175 for(DockDescription dd : sd.ports()) {
176 String name = dd.getName();
177 pw.println("`define "+name+"_full ("+name+"_r && !"+name+"_a)");
178 pw.println("`define "+name+"_empty (!"+name+"_r && !"+name+"_a)");
179 if (dd.isInputDock()) {
180 pw.println("`define drain_"+name+" "+name+"_a <= 1;");
182 pw.println("`define fill_"+name+" "+name+"_r <= 1;");
186 pw.print("`define reset ");
187 for(DockDescription bb : sd.ports()) {
188 String bb_name = bb.getName();
189 if (bb.isInputDock()) pw.print(bb_name+"_a <= 1; "+bb_name+"_f <= 0; ");
190 else pw.print(bb_name+"_r <= 0; ");
194 pw.print("`define cleanup ");
195 for(DockDescription bb : sd.ports()) {
196 String bb_name = bb.getName();
197 if (bb.isInputDock()) pw.print("if (!"+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_a <= 0; ");
198 else pw.print("if ( "+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_r <= 0; ");
202 // FIXME: this corresponds to something
204 pw.print("`define flush_happening (1");
205 for(DockDescription bb : sd.ports())
206 if (bb.isInputDock())
207 pw.print(" && "+bb.getName()+"_r_ && !"+bb.getName()+"_a && "+bb.getName()+"_d["+WIDTH_WORD+"]");
211 pw.print("`define flush ");
212 for(DockDescription bb : sd.ports())
213 if (bb.isInputDock())
214 pw.print(" if (!"+bb.getName()+"_r_) "+bb.getName()+"_f <= 0; ");
216 for(DockDescription bb : sd.ports())
217 if (bb.isInputDock())
218 pw.print(" && "+bb.getName()+"_r_ && !"+bb.getName()+"_a");
219 pw.print(") begin ");
222 for(DockDescription bb : sd.ports())
223 if (bb.isInputDock())
224 pw.print(" && "+bb.getName()+"_d["+WIDTH_WORD+"] ");
225 pw.print(") begin ");
227 for(DockDescription bb : sd.ports())
228 if (bb.isInputDock())
229 pw.print(bb.getName()+"_f <= 1; ");
231 pw.print(" end else if (0");
232 for(DockDescription bb : sd.ports())
233 if (bb.isInputDock())
234 pw.print(" || "+bb.getName()+"_d["+WIDTH_WORD+"] ");
235 pw.print(") begin ");
237 for(DockDescription bb : sd.ports())
238 if (bb.isInputDock())
239 pw.print(" if (!"+bb.getName()+"_d["+WIDTH_WORD+"]) "+bb.getName()+"_f <= 1; ");
246 pw.println("module " + filename + "( clk, rst ");
247 for(DockDescription bb : sd.ports()) {
248 String bb_name = bb.getName();
250 if (bb.isInputDock()) {
251 pw.print(", " + bb_name+"_r_");
252 pw.print(", " + bb_name+"_a_");
253 pw.print(", " + bb_name+"_d");
255 pw.print(", " + bb_name+"_r_");
256 pw.print(", " + bb_name+"_a");
257 pw.print(", " + bb_name+"_d_");
261 for(PercolatedPort pp : sd.percolatedPorts) {
267 pw.println(" input clk;");
268 pw.println(" input rst;");
269 for(PercolatedPort pp : sd.percolatedPorts) {
271 case UP: pw.print("output"); break;
272 case DOWN: pw.print("input"); break;
273 case INOUT: pw.print("inout"); break;
277 pw.print("["+(pp.width-1)+":0]");
283 for(DockDescription bb : sd.ports()) {
284 String bb_name = bb.getName();
285 int width = bb.isDockless() ? WIDTH_PACKET : WIDTH_WORD;
286 if (bb.isInputDock()) {
287 pw.println(" input ["+width+":0] "+bb_name+"_d;");
288 pw.println(" input "+bb_name+"_r_;");
289 pw.println(" wire "+bb_name+"_r;");
290 pw.println(" assign "+bb_name+"_r = "+bb_name+"_r_ & ~"+bb_name+"_d["+width+"];");
291 pw.println(" output "+bb_name+"_a_;");
292 pw.println(" reg "+bb_name+"_a;");
293 pw.println(" initial "+bb_name+"_a = 0;");
294 pw.println(" reg "+bb_name+"_f;");
295 pw.println(" initial "+bb_name+"_f = 0;");
296 pw.println(" assign "+bb_name+"_a_ = "+bb_name+"_a || "+bb_name+"_f;");
298 pw.println(" output ["+width+":0] "+bb_name+"_d_;");
299 pw.println(" input "+bb_name+"_a;");
300 pw.println(" output "+bb_name+"_r_;");
301 pw.println(" reg "+bb_name+"_r;");
302 pw.println(" initial "+bb_name+"_r = 0;");
303 pw.println(" assign "+bb_name+"_r_ = "+bb_name+"_r;");
308 if (filename.equals("fifo")) {
309 pw.println(" wire in_a__;");
310 pw.println(" wire out_r__;");
311 pw.println(" fifo8x37 fifo8x37(clk, rst,");
312 pw.println(" in_r, in_a__, in_d,");
313 pw.println(" out_r__, out_a, out_d_);");
314 pw.println(" always @(posedge clk) begin");
315 pw.println(" if (!rst) begin");
316 pw.println(" `reset");
317 pw.println(" end else begin");
318 pw.println(" `flush");
319 pw.println(" out_r <= out_r__;");
320 pw.println(" in_a <= in_a__;");
324 pw.println(sd.getSection("fpga"));
327 pw.println("endmodule");
331 } catch (Exception e) { throw new RuntimeException(e); }