1 package edu.berkeley.fleet.fpga;
2 import edu.berkeley.fleet.fpga.*;
3 import edu.berkeley.fleet.api.*;
4 import edu.berkeley.fleet.two.*;
5 import edu.berkeley.fleet.*;
6 import java.lang.reflect.*;
7 import edu.berkeley.sbp.chr.*;
8 import edu.berkeley.sbp.misc.*;
9 import edu.berkeley.sbp.meta.*;
10 import edu.berkeley.sbp.util.*;
13 import edu.berkeley.fleet.two.*;
14 import static edu.berkeley.fleet.two.FleetTwoFleet.*;
15 import static edu.berkeley.fleet.fpga.verilog.Verilog.*;
19 => get rid of getInputPort(String) and instead use members
20 => clean up fabricelement methods
22 => automatic width-setting on ports
24 => serdes and fastclock/slowclock?
27 public class Fpga extends FleetTwoFleet {
30 public FabricElement top_horn;
33 public LinkedHashMap<String,FpgaShip> ships = new LinkedHashMap<String,FpgaShip>();
34 public Iterator<Ship> iterator() { return (Iterator<Ship>)(Object)ships.values().iterator(); }
36 public Ship getShip(String type, int ordinal) {
38 if (s.getType().equals(type))
44 public static void main(String[] s) throws Exception {
45 new Fpga(new Module("root")).top.dump(s[0]);
48 pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/timescale.v")));
49 pw.println("`timescale 1ns / 10ps");
52 pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/bram14.v")));
53 pw.println("`define BRAM_ADDR_WIDTH 14");
54 pw.println("`define BRAM_DATA_WIDTH `DATAWIDTH");
55 pw.println("`define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))");
56 pw.println("`define BRAM_NAME bram14");
57 pw.println("`include \"bram.inc\"");
60 pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/vram.v")));
61 pw.println("`define BRAM_ADDR_WIDTH 19");
62 pw.println("`define BRAM_DATA_WIDTH 3");
63 pw.println("`define BRAM_SIZE (640*480)");
64 pw.println("`define BRAM_NAME vram");
65 pw.println("`include \"bram.inc\"");
69 public Module getVerilogModule() { return top; }
71 public FleetProcess run(Instruction[] instructions) {
73 return new Client(this, "none", instructions);
74 } catch (Exception e) { throw new RuntimeException(e); }
77 public BitVector getDestAddr(Path path) {
78 return ((FpgaPath)path).toBitVector();
81 // Setup //////////////////////////////////////////////////////////////////////////////
83 public Ship createShip(String type, String name) throws IOException {
84 ShipDescription sd = new ShipDescription(type, new BufferedReader(new InputStreamReader(new FileInputStream("ships/"+type+".ship"))));
85 FpgaShip ship = new FpgaShip(this, sd);
86 ships.put(name, ship);
90 public Fpga() throws Exception { this(new Module("root")); }
91 public Fpga(Module top) throws Exception {
93 debugShip = createShip("Debug", "debug");
95 //boolean small = false;
98 createShip("Memory", "memory1");
101 for(int i=0; i<2; i++)
102 createShip("Fifo", "fifo"+i);
103 for(int i=0; i<2; i++)
104 createShip("Alu", "alu"+i);
105 createShip("Counter", "counter");
106 createShip("CarrySaveAdder", "csa1");
107 createShip("Rotator", "rotator");
108 createShip("Lut3", "lut");
110 createShip("Memory", "memory2");
111 createShip("Memory", "memory3");
113 for(int i=0; i<3; i++)
114 createShip("Alu", "alu"+i);
116 for(int i=0; i<1; i++)
117 createShip("Fifo", "fifo"+i);
119 for(int i=0; i<14; i++)
120 createShip("Counter", "counter"+i);
123 createShip("CarrySaveAdder", "csa1");
124 createShip("Rotator", "rotator");
125 createShip("Lut3", "lut");
127 //createShip("DDR2", "ddr2");
129 createShip("DRAM", "dram");
130 createShip("Video", "video");
132 //Module.SourcePort debug_in = top.createWireSourcePort("debug_in", WIDTH_PACKET);
133 Module.SourcePort debug_out = null;
134 for(FpgaShip ship : (Iterable<FpgaShip>)(Object)this) {
135 if (ship.getType().toLowerCase().equals("debug"))
136 debug_out = ship.getVerilogModule().getOutputPort("debug_out");
140 new Module.InstantiatedModule(top, new FifoModule(8, WIDTH_WORD));
142 Module.SourcePort in = top.createInputPort("in", 8);
143 Module.SinkPort out = top.createOutputPort("out", 8, "");
144 Module.Latch temp_in = top.new Latch("temp", WIDTH_PACKET);
145 Module.Latch count = top.new Latch("count", 8);
146 Module.Latch count_out = top.new Latch("count_out", 8);
148 ArrayList inbox_sources = new ArrayList<FabricElement>();
149 ArrayList inbox_dests = new ArrayList<FabricElement>();
150 ArrayList outbox_sources = new ArrayList<FabricElement>();
151 ArrayList outbox_dests = new ArrayList<FabricElement>();
152 ArrayList instruction_dests = new ArrayList<FabricElement>();
154 for(FpgaShip ship : (Iterable<FpgaShip>)(Object)this) {
155 if (ship.getType().toLowerCase().equals("debug"))
156 debug_out = ship.getVerilogModule().getOutputPort("debug_out");
157 for(Dock port : ship) {
158 if (port.isInputDock()) {
159 inbox_sources.add(((FpgaDock)port));
160 instruction_dests.add(port.getInstructionDestination());
161 inbox_dests.add(port.getDataDestination());
163 outbox_sources.add(((FpgaDock)port));
164 instruction_dests.add(port.getInstructionDestination());
165 outbox_dests.add(port.getDataDestination());
170 //System.err.println("dock count = " + numdocks);
171 ArrayList dests = new ArrayList<FabricElement>();
172 ArrayList sources = new ArrayList<FabricElement>();
173 sources.addAll(inbox_sources);
174 sources.addAll(outbox_sources);
175 dests.addAll(inbox_dests);
176 dests.addAll(instruction_dests);
177 dests.addAll(outbox_dests);
178 top_horn = mkNode((FabricElement[])dests.toArray(new FabricElement[0]), true);
179 FabricElement source = mkNode((FabricElement[])sources.toArray(new FabricElement[0]), false);
180 FunnelModule.FunnelInstance top_funnel = new FunnelModule.FunnelInstance(this, top, null, source.getOutputPort());
181 ((FunnelModule.FunnelInstance)source).out = top_funnel;
182 //top_horn.addInput(top_funnel, top_funnel.getOutputPort());
183 top_funnel.addOutput(top_horn, top_horn.getInputPort());
185 //Module.SourcePort debug_in = top.createWireSourcePort("debug_in", WIDTH_PACKET);
186 Module.SinkPort debug_in = top_funnel.getInputPort("in1");
188 top.new Event(new Object[] { in, "count<=7" },
189 new Object[] { new SimpleAction(temp_in.getVerilogName()+" <= {" + temp_in.getVerilogName() + "["+(WIDTH_PACKET-(1+8))+":0], in[7:0] };"),
190 new SimpleAction("count <= count+1;"),
193 top.new Event(new Object[] { debug_in, "count>7" },
194 new Object[] { new SimpleAction(" count <= 0; "),
195 new AssignAction(debug_in, temp_in),
198 top.new Event(new Object[] { out, debug_out },
199 new Object[] { new SimpleAction(out.getVerilogName()+" <= ("+debug_out.getVerilogName()+">> (count_out*8));"),
200 new SimpleAction("if (count_out >= 5) begin "+
201 "count_out <= 0; "+debug_out.getVerilogName()+"_a <= 1; end"+
202 " else count_out <= count_out+1; "),
207 public FabricElement mkNode(FabricElement[] ports, boolean is_horn) { return mkNode(ports, is_horn, 0, ports.length); }
208 public FabricElement mkNode(FabricElement[] ports, boolean is_horn, int start, int end) {
211 case 1: return ports[start];
213 FabricElement leftPort = mkNode(ports, is_horn, start, (end+start)/2);
214 FabricElement rightPort = mkNode(ports, is_horn, (end+start)/2, end);
216 ? new HornModule.HornInstance(this, top, leftPort, rightPort)
217 : new FunnelModule.FunnelInstance(this, top, leftPort, rightPort);
223 // Expand //////////////////////////////////////////////////////////////////////////////
225 public void expand(ShipDescription sd) {
227 if (sd.getSection("fpga")==null) return;
228 String filename = sd.getName().toLowerCase();
229 File outf = new File("build/fpga/"+filename+".v");
230 new File(outf.getParent()).mkdirs();
231 System.err.println("writing to " + outf);
232 FileOutputStream out = new FileOutputStream(outf);
233 PrintWriter pw = new PrintWriter(out);
235 boolean debug = "debug".equals(filename);
237 pw.println("`define DATAWIDTH "+WIDTH_WORD);
238 pw.println("`define CODEBAG_SIZE_BITS "+CBD_SIZE.valmaskwidth);
241 for(DockDescription dd : sd) {
242 String name = dd.getName();
243 pw.println("`define "+name+"_full ("+name+"_r && !"+name+"_a)");
244 pw.println("`define "+name+"_empty (!"+name+"_r && !"+name+"_a)");
245 if (dd.isInputDock()) {
246 pw.println("`define drain_"+name+" "+name+"_a <= 1;");
248 pw.println("`define fill_"+name+" "+name+"_r <= 1;");
249 pw.println("`define "+name+"_draining ("+name+"_r && "+name+"_a)");
254 pw.println("`define "+name+"_full ("+name+"_r && !"+name+"_a)");
255 pw.println("`define "+name+"_empty (!"+name+"_r && !"+name+"_a)");
256 pw.println("`define fill_"+name+" "+name+"_r <= 1;");
257 pw.println("`define "+name+"_draining ("+name+"_r && "+name+"_a)");
260 pw.print("`define reset ");
261 for(DockDescription bb : sd) {
262 String bb_name = bb.getName();
263 if (bb.isInputDock()) pw.print(bb_name+"_a <= 1; "+bb_name+"_f <= 0; ");
264 else pw.print(bb_name+"_r <= 0; ");
267 String bb_name = "out";
268 pw.print(bb_name+"_r <= 0; ");
272 pw.print("`define cleanup ");
273 for(DockDescription bb : sd) {
274 String bb_name = bb.getName();
275 if (bb.isInputDock()) pw.print("if (!"+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_a <= 0; ");
276 else pw.print("if ( "+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_r <= 0; ");
279 String bb_name = "out";
280 pw.print("if ( "+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_r <= 0; ");
284 // FIXME: this corresponds to something
286 pw.print("`define flush_happening (1");
287 for(DockDescription bb : sd)
288 if (bb.isInputDock())
289 pw.print(" && "+bb.getName()+"_r_ && !"+bb.getName()+"_a && "+bb.getName()+"_d["+WIDTH_WORD+"]");
293 pw.print("`define flush ");
294 for(DockDescription bb : sd)
295 if (bb.isInputDock())
296 pw.print(" if (!"+bb.getName()+"_r_) "+bb.getName()+"_f <= 0; ");
298 for(DockDescription bb : sd)
299 if (bb.isInputDock())
300 pw.print(" && "+bb.getName()+"_r_ && !"+bb.getName()+"_a");
301 pw.print(") begin ");
304 for(DockDescription bb : sd)
305 if (bb.isInputDock())
306 pw.print(" && "+bb.getName()+"_d["+WIDTH_WORD+"] ");
307 pw.print(") begin ");
309 for(DockDescription bb : sd)
310 if (bb.isInputDock())
311 pw.print(bb.getName()+"_f <= 1; ");
313 pw.print(" end else if (0");
314 for(DockDescription bb : sd)
315 if (bb.isInputDock())
316 pw.print(" || "+bb.getName()+"_d["+WIDTH_WORD+"] ");
317 pw.print(") begin ");
319 for(DockDescription bb : sd)
320 if (bb.isInputDock())
321 pw.print(" if (!"+bb.getName()+"_d["+WIDTH_WORD+"]) "+bb.getName()+"_f <= 1; ");
328 pw.println("module " + filename + "( clk, rst ");
329 for(DockDescription bb : sd) {
330 String bb_name = bb.getName();
332 if (bb.isInputDock()) {
333 pw.print(", " + bb_name+"_r_");
334 pw.print(", " + bb_name+"_a_");
335 pw.print(", " + bb_name+"_d");
337 pw.print(", " + bb_name+"_r_");
338 pw.print(", " + bb_name+"_a");
339 pw.print(", " + bb_name+"_d_");
343 if (filename.equals("debug")) {
344 pw.println(" , out_r_");
345 pw.println(" , out_a");
346 pw.println(" , out_d_");
348 if (filename.equals("dram")) {
349 pw.println(" , dram_addr_");
350 pw.println(" , dram_addr_r_");
351 pw.println(" , dram_addr_a");
352 pw.println(" , dram_isread_");
353 pw.println(" , dram_write_data_");
354 pw.println(" , dram_write_data_push_");
355 pw.println(" , dram_write_data_full");
356 pw.println(" , dram_read_data");
357 pw.println(" , dram_read_data_pop_");
358 pw.println(" , dram_read_data_empty");
359 pw.println(" , dram_read_data_latency");
361 if (filename.equals("ddr2")) {
362 pw.println(" , ddr2_addr_");
363 pw.println(" , ddr2_addr_r_");
364 pw.println(" , ddr2_addr_a");
365 pw.println(" , ddr2_isread_");
366 pw.println(" , ddr2_write_data_");
367 pw.println(" , ddr2_write_data_push_");
368 pw.println(" , ddr2_write_data_full");
369 pw.println(" , ddr2_read_data");
370 pw.println(" , ddr2_read_data_pop_");
371 pw.println(" , ddr2_read_data_empty");
372 pw.println(" , ddr2_read_data_latency");
374 if (filename.equals("video")) {
375 pw.println(" , vga_clk");
376 pw.println(" , vga_psave");
377 pw.println(" , vga_hsync");
378 pw.println(" , vga_vsync");
379 pw.println(" , vga_sync");
380 pw.println(" , vga_blank");
381 pw.println(" , vga_r");
382 pw.println(" , vga_g");
383 pw.println(" , vga_b");
384 pw.println(" , vga_clkout");
388 pw.println(" input clk;");
389 pw.println(" input rst;");
390 if (filename.equals("dram")) {
391 pw.println("output [31:0] dram_addr_;");
392 pw.println("output dram_addr_r_;");
393 pw.println("input dram_addr_a;");
394 pw.println("output dram_isread_;");
395 pw.println("output [63:0] dram_write_data_;");
396 pw.println("output dram_write_data_push_;");
397 pw.println("input dram_write_data_full;");
398 pw.println("input [63:0] dram_read_data;");
399 pw.println("output dram_read_data_pop_;");
400 pw.println("input dram_read_data_empty;");
401 pw.println("input [1:0] dram_read_data_latency;");
403 if (filename.equals("ddr2")) {
404 pw.println("output [31:0] ddr2_addr_;");
405 pw.println("output ddr2_addr_r_;");
406 pw.println("input ddr2_addr_a;");
407 pw.println("output ddr2_isread_;");
408 pw.println("output [63:0] ddr2_write_data_;");
409 pw.println("output ddr2_write_data_push_;");
410 pw.println("input ddr2_write_data_full;");
411 pw.println("input [63:0] ddr2_read_data;");
412 pw.println("output ddr2_read_data_pop_;");
413 pw.println("input ddr2_read_data_empty;");
414 pw.println("input [1:0] ddr2_read_data_latency;");
416 if (filename.equals("video")) {
417 pw.println("input vga_clk;");
418 pw.println("output vga_psave;");
419 pw.println("output vga_hsync;");
420 pw.println("output vga_vsync;");
421 pw.println("output vga_sync;");
422 pw.println("output vga_blank;");
423 pw.println("output [7:0] vga_r;");
424 pw.println("output [7:0] vga_g;");
425 pw.println("output [7:0] vga_b;");
426 pw.println("output vga_clkout;");
429 for(DockDescription bb : sd) {
430 String bb_name = bb.getName();
431 if (bb.isInputDock()) {
432 pw.println(" input ["+WIDTH_WORD+":0] "+bb_name+"_d;");
433 pw.println(" input "+bb_name+"_r_;");
434 pw.println(" wire "+bb_name+"_r;");
435 pw.println(" assign "+bb_name+"_r = "+bb_name+"_r_ & ~"+bb_name+"_d["+WIDTH_WORD+"];");
436 pw.println(" output "+bb_name+"_a_;");
437 pw.println(" reg "+bb_name+"_a;");
438 pw.println(" initial "+bb_name+"_a = 0;");
439 pw.println(" reg "+bb_name+"_f;");
440 pw.println(" initial "+bb_name+"_f = 0;");
441 pw.println(" assign "+bb_name+"_a_ = "+bb_name+"_a || "+bb_name+"_f;");
443 pw.println(" output ["+WIDTH_WORD+":0] "+bb_name+"_d_;");
444 pw.println(" input "+bb_name+"_a;");
445 pw.println(" output "+bb_name+"_r_;");
446 pw.println(" reg "+bb_name+"_r;");
447 pw.println(" initial "+bb_name+"_r = 0;");
448 pw.println(" assign "+bb_name+"_r_ = "+bb_name+"_r;");
452 if (filename.equals("debug")) {
453 String bb_name = "out";
454 pw.println(" output ["+WIDTH_WORD+":0] "+bb_name+"_d_;");
455 pw.println(" input "+bb_name+"_a;");
456 pw.println(" output "+bb_name+"_r_;");
457 pw.println(" reg "+bb_name+"_r;");
458 pw.println(" initial "+bb_name+"_r = 0;");
459 pw.println(" assign "+bb_name+"_r_ = "+bb_name+"_r;");
462 if (filename.equals("fifo")) {
463 pw.println(" wire in_a__;");
464 pw.println(" wire out_r__;");
465 pw.println(" fifo8x37 fifo8x37(clk, rst,");
466 pw.println(" in_r, in_a__, in_d,");
467 pw.println(" out_r__, out_a, out_d_);");
468 pw.println(" always @(posedge clk) begin");
469 pw.println(" if (!rst) begin");
470 pw.println(" `reset");
471 pw.println(" end else begin");
472 pw.println(" `flush");
473 pw.println(" out_r <= out_r__;");
474 pw.println(" in_a <= in_a__;");
478 pw.println(sd.getSection("fpga"));
481 pw.println("endmodule");
485 } catch (Exception e) { throw new RuntimeException(e); }