1 package edu.berkeley.fleet.fpga;
2 import edu.berkeley.fleet.api.*;
3 import edu.berkeley.fleet.two.*;
4 import edu.berkeley.fleet.*;
5 import java.lang.reflect.*;
6 import edu.berkeley.sbp.chr.*;
7 import edu.berkeley.sbp.misc.*;
8 import edu.berkeley.sbp.meta.*;
9 import edu.berkeley.sbp.util.*;
12 import static edu.berkeley.fleet.two.FleetTwoFleet.*;
13 import static edu.berkeley.fleet.fpga.verilog.Verilog.*;
14 import edu.berkeley.fleet.api.*;
15 import edu.berkeley.fleet.api.Dock;
16 import edu.berkeley.fleet.two.*;
19 public class FpgaDock extends FleetTwoDock implements FabricElement {
21 private static final int INSTRUCTION_FIFO_SIZE = 12;
22 private static final int EPILOGUE_FIFO_SIZE = 0;
23 //private static final int DATA_FIFO_SIZE = 4;
24 static final int DATA_FIFO_SIZE = 8;
26 private FpgaDestination dataDestination;
27 private FpgaDestination instructionDestination;
29 private Module.InstantiatedModule instance;
31 public Module.InstantiatedModule getInstance() { return instance; }
35 public Destination getDataDestination() { return dataDestination; }
36 public Destination getInstructionDestination() { return instructionDestination; }
37 public int getInstructionFifoSize() { return INSTRUCTION_FIFO_SIZE; }
39 FpgaDock(FpgaShip ship, DockDescription bbd) {
41 this.fpga = (Fpga)ship.getFleet();
42 this.instance = new Module.InstantiatedModule(((Fpga)ship.getFleet()).top, new DockModule(isInputDock()));
43 this.dataDestination = new FpgaDestination(this, this.instance.getInputPort("fabric_in"), false);
44 this.instructionDestination = new FpgaDestination(this, this.instance.getInputPort("instruction"), true);
45 Module.InstantiatedModule shipm = ship.getVerilogModule();
47 instance.getOutputPort("ship").connect(shipm.getInputPort(getName()));
49 shipm.getOutputPort(getName()).connect(instance.getInputPort("ship"));
54 // FabricElement methods //////////////////////////////////////////////////////////////////////////////
56 private FabricElement upstream;
57 public Module.SourcePort getOutputPort() { throw new RuntimeException(); }
58 public Module.Port getInputPort() { throw new RuntimeException(); }
59 public Path getPath(Destination dest,BitVector signal) { return getPath((FpgaDestination)dest, signal); }
60 public FpgaPath getPath(FpgaDestination dest,BitVector signal) { return upstream.getPath(dest, signal); }
61 public int getPathLength(FpgaDestination dest) { return upstream.getPathLength(dest)-1; }
62 public void addInput(FabricElement in, Module.Port inPort) { throw new RuntimeException(); }
63 public void addOutput(FabricElement out, Module.Port outPort) {
65 instance.getOutputPort("fabric_out").connect((Module.SinkPort)outPort);
68 public class TorpedoBranchModule extends Module {
69 public TorpedoBranchModule() {
70 super("torpedobranch");
71 Module.SourcePort in = createInputPort ("in", fpga.WIDTH_PACKET);
72 Module.SinkPort out = createOutputPort("out", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
73 Module.SinkPort torpedo = createOutputPort("torpedo", 0);
74 Module.StateWire busy = new StateWire("busy", false);
76 new Event(new Object[] { in, busy.isFull(), out },
77 new Action[] { in, busy.doDrain() });
78 new Event(new Object[] { in, busy.isEmpty(), out, torpedo, in.testMask(fpga.PACKET_IS_TOKEN) },
79 new Action[] { in, torpedo });
80 new Event(new Object[] { in, busy.isEmpty(), out, in.testMask(fpga.PACKET_IS_TOKEN).invert() },
81 new Action[] { busy.doFill(), out });
83 out.connectValue(in.getBits(fpga.PACKET_DATA));
87 public class RequeueModule extends Module {
88 public RequeueModule() {
90 Module.SourcePort fabric_in = createInputPort ("fabric_in", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
91 Module.SourcePort ondeck_in = createInputPort ("ondeck_in", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
92 Module.SourcePort abort = createInputPort ("abort", 1);
93 Module.SinkPort out = createOutputPort("out", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
95 Module.StateWire circulating = new StateWire("circulating", false);
96 Module.StateWire doResetFabric = new StateWire("doResetFabric", false);
97 Module.StateWire doResetOndeck = new StateWire("doResetOndeck", false);
99 out.connectValue(new MuxValue(circulating.isEmpty(), fabric_in, ondeck_in));
101 // always: discard one-shot instructions
102 new Event(new Object[] { doResetFabric.isFull(), out },
103 new Action[] { doResetFabric.doDrain(), fabric_in });
104 new Event(new Object[] { doResetOndeck.isFull(), out },
105 new Action[] { doResetOndeck.doDrain(), ondeck_in });
107 // Updating->Circulating transition
108 new Event(new Object[] { doResetFabric.isEmpty(),
109 doResetOndeck.isEmpty(),
110 circulating.isEmpty(),
112 fpga.TAIL.verilog(fabric_in.getName()),
114 fpga.HEAD.verilog(ondeck_in.getName()) },
115 new Action[] { circulating.doFill(),
119 // Circulating->Updating transition
120 new Event(new Object[] { doResetFabric.isEmpty(),
121 doResetOndeck.isEmpty(),
122 circulating.isFull(),
124 abort.getVerilog() },
125 new Action[] { circulating.doDrain(),
129 new Event(new Object[] { doResetFabric.isEmpty(),
130 doResetOndeck.isEmpty(),
131 circulating.isEmpty(),
133 "!"+fpga.TAIL.verilog(fabric_in.getName()) },
134 new Action[] { doResetFabric.doFill(),
136 new Event(new Object[] { doResetFabric.isEmpty(),
137 doResetOndeck.isEmpty(),
138 circulating.isEmpty(),
140 "!"+fpga.HEAD.verilog(ondeck_in.getName()) },
141 new Action[] { ondeck_in });
144 new Event(new Object[] { doResetFabric.isEmpty(),
145 doResetOndeck.isEmpty(),
146 circulating.isFull(),
148 "!"+abort.getVerilog() },
149 new Action[] { doResetOndeck.doFill(),
154 public class DockModule extends Module {
156 public DockModule(boolean inbox) {
157 super(inbox ? "inbox" : "outbox");
159 int dfifo_width = inbox ? fpga.getWordWidth()+1 : 1;
161 // FIXME: assumes fpga.DISPATCH_PATH is at top of word!!!
162 Module ififo_m = new FifoModule(INSTRUCTION_FIFO_SIZE, fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
163 Module dfifo_m = new FifoModule(DATA_FIFO_SIZE, dfifo_width);
165 Module.SourcePort instruction = createInputPort("instruction", fpga.WIDTH_PACKET);
166 Module.SourcePort fabric_in = createInputPort("fabric_in", fpga.WIDTH_PACKET);
168 // FIXME: at inboxes, no need for a full set of latches
169 Module.SinkPort fabric_out = createOutputPort("fabric_out", fpga.WIDTH_PACKET);
171 Module.InstantiatedModule dfifo = new Module.InstantiatedModule(this, dfifo_m);
173 fabric_in.connect(dfifo.getInputPort("in"));
174 dfifo.getInputPort("in").connectValue(
176 ? fabric_in.getBits(fpga.PACKET_SIGNAL)
177 : new CatValue(new Value[] {
178 fabric_in.getBits(fpga.PACKET_SIGNAL),
179 fabric_in.getBits(fpga.PACKET_DATA)
182 Module.SourcePort dfifo_out = dfifo.getOutputPort("out");
183 Module.SourcePort ship_out = !inbox ? createInputPort("ship", fpga.getWordWidth()+1) : null;
184 Module.SinkPort ship_in = inbox ? createOutputPort("ship", fpga.getWordWidth()+1) : null;
186 Module.Latch ilc = new Latch("ilc", fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth+1, 1);
187 Module.Latch olc = new Latch("olc", fpga.SET_OLC_FROM_IMMEDIATE.valmaskwidth, 1);
188 Module.Latch flag_a = new Latch("flag_a", 1);
189 Module.Latch flag_b = new Latch("flag_b", 1);
190 Module.Latch flag_c = new Latch("flag_c", 1);
191 Module.Latch flag_d = new Latch("flag_d", 1);
193 Module.SinkPort token_out = fabric_out;
194 Module.SourcePort token_in = dfifo_out;
195 Module.SinkPort data_out = inbox ? ship_in : fabric_out;
196 Module.SourcePort data_in = inbox ? dfifo_out : ship_out;
198 Module.InstantiatedModule ififo = new Module.InstantiatedModule(this, ififo_m);
199 Module.SinkPort ififo_in = ififo.getInputPort("in");
200 Module.SourcePort ififo_out = ififo.getOutputPort("out");
202 Module.InstantiatedModule torpedo_branch = new Module.InstantiatedModule(this, new TorpedoBranchModule());
203 instruction.connect(torpedo_branch.getInputPort("in"));
204 Module.SourcePort efifo_out = torpedo_branch.getOutputPort("out");
205 Module.SourcePort torpedo_branch_torpedo = torpedo_branch.getOutputPort("torpedo");
207 Module.InstantiatedModule fanout_module = new Module.InstantiatedModule(this, new FanoutModule(fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth));
208 Module.SinkPort fanout_module_in = fanout_module.getInputPort("in");
209 Module.SourcePort fanout_module_out0 = fanout_module.getOutputPort("out0");
210 Module.SourcePort fanout_module_out1 = fanout_module.getOutputPort("out1");
212 Module.InstantiatedModule requeue_module = new Module.InstantiatedModule(this, new RequeueModule());
213 Module.SinkPort requeue_fabric_in = requeue_module.getInputPort("fabric_in");
214 Module.SinkPort requeue_ondeck = requeue_module.getInputPort("ondeck_in");
215 Module.SinkPort requeue_abort = requeue_module.getInputPort("abort");
216 Module.SourcePort requeue_out = requeue_module.getOutputPort("out");
218 efifo_out.connect(requeue_fabric_in);
219 requeue_out.connect(ififo_in);
220 ififo_out.connect(fanout_module_in);
221 fanout_module_out0.connect(requeue_ondeck);
222 Module.SourcePort ondeck = fanout_module_out1;
224 WireValue decremented = new WireValue("decremented", Math.max(ilc.width,olc.width),
225 new SimpleValue("("+ondeck.testMask(fpga.SET_OLC_FROM_OLC_MINUS_ONE).getVerilogTrigger()+
226 " ? {1'b0, olc} : ilc)-1"));
227 WireValue data_latch_output_p = new WireValue("data_latch_output",
228 inbox ? fpga.getWordWidth()+1 : fpga.getWordWidth(),
230 ? new SimpleValue(data_out.getName())
231 : new SimpleValue(data_out.getBits(fpga.PACKET_DATA).getVerilog()))
234 Assignable data_latch = new SimpleAssignable(inbox ? data_out.getName() : data_out.getBits(fpga.PACKET_DATA).getVerilog());
235 Module.SourcePort data_latch_input = inbox ? data_in : data_in;
237 BitVector bv = new BitVector(fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth+1);
238 bv.set(fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth, true);
239 Value magic_standing_value = new ConstantValue(bv);
241 Trigger done_executing = new SimpleTrigger("((ilc==0) || (ilc==1) || !"+fpga.MOVE.verilog(ondeck.getName())+")");
243 String predicate_met =
246 "!"+fpga.MOVE.verilog(ondeck.getName())+" || (ilc!=0)"+
249 fpga.P_ALWAYS.verilog(ondeck.getName())+
251 fpga.P_OLC_ZERO.verilog(ondeck.getName())+"==flag_d"+
254 " " + fpga.P_A.verilog(ondeck.getName())+" ? flag_a"+
255 ":" + fpga.P_B.verilog(ondeck.getName())+" ? flag_b"+
256 ":" + fpga.P_NOT_A.verilog(ondeck.getName())+" ? !flag_a"+
257 ":" + fpga.P_NOT_B.verilog(ondeck.getName())+" ? !flag_b "+
262 requeue_abort.connectValue(new SimpleValue("("+predicate_met+") && "+fpga.ABORT.verilog(ondeck.getName())));
265 new Event(new Object[] {
270 fpga.MOVE.verilog(ondeck.getName()),
271 "!"+fpga.NOT_INTERRUPTIBLE.verilog(ondeck.getName()),
272 torpedo_branch_torpedo
276 torpedo_branch_torpedo,
277 new AssignAction(olc, new ConstantValue(new BitVector(olc.width).set(0))),
278 new AssignAction(flag_d, new ConstantValue(new BitVector(1).set(1))),
279 new AssignAction(ilc, new ConstantValue(new BitVector(ilc.width).set(1)))
283 new Event(new Object[] { ondeck, "!("+predicate_met+")" },
284 new Action[] { ondeck,
285 new ConditionalAction(ondeck.testMask(fpga.MOVE),
286 new AssignAction(ilc, new ConstantValue(new BitVector(ilc.width).set(1))))
289 new Event(new Object[] { ondeck,
293 "(!"+fpga.MOVE.verilog(ondeck.getName())+" || "+fpga.NOT_INTERRUPTIBLE.verilog(ondeck.getName())+" || !"+torpedo_branch_torpedo.isFull()+")",
294 new ConditionalTrigger(ondeck.testMask(fpga.DI), data_in),
295 new ConditionalTrigger(ondeck.testMask(fpga.TI), token_in)
298 new ConditionalAction(new AndTrigger(done_executing, ondeck.testMask(fpga.MOVE)),
299 new AssignAction(ilc, new ConstantValue(new BitVector(ilc.width).set(1)))),
300 new ConditionalAction(done_executing, ondeck),
301 new ConditionalAction(done_executing.invert(),
302 new AssignAction(ilc, new MuxValue(new TestValue(ilc, TestValue.TestType.EQ, magic_standing_value),
303 magic_standing_value,
305 new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_DATA_LATCH),
306 new AssignAction(olc, new SimpleValue("data_latch_output"))),
307 new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_IMMEDIATE),
308 new AssignAction(olc, ondeck.getBits(fpga.SET_OLC_FROM_IMMEDIATE))),
309 new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_OLC_MINUS_ONE),
310 new AssignAction(olc, new SimpleValue("olc==0 ? 0 : decremented"))),
312 new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_DATA_LATCH),
313 new AssignAction(flag_d, new SimpleValue("data_latch_output==0"))),
314 new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_IMMEDIATE),
315 new AssignAction(flag_d, new SimpleValue(ondeck.getBits(fpga.SET_OLC_FROM_IMMEDIATE).getVerilog()+"==0"))),
316 new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_OLC_MINUS_ONE),
317 new AssignAction(flag_d, new SimpleValue("(olc==0 || olc==1)"))),
319 new ConditionalAction(ondeck.testMask(fpga.SET_ILC_FROM_DATA_LATCH),
320 new AssignAction(ilc, new SimpleValue("data_latch_output"))),
322 new ConditionalAction(ondeck.testMask(fpga.SET_ILC_FROM_IMMEDIATE),
323 new AssignAction(ilc, ondeck.getBits(fpga.SET_ILC_FROM_IMMEDIATE))),
324 new ConditionalAction(ondeck.testMask(fpga.SET_ILC_FROM_INFINITY),
325 new AssignAction(ilc, magic_standing_value)),
326 new ConditionalAction(ondeck.testMask(fpga.SHIFT),
327 new AssignAction(data_latch,
328 new SimpleValue("{ data_latch_output["+(fpga.getWordWidth()-1-fpga.SHIFT.valmaskwidth)+":0], "+
329 ondeck.getBits(fpga.SHIFT).getVerilog()+"}"))),
330 new ConditionalAction(ondeck.testMask(fpga.SET_IMMEDIATE),
331 new AssignAction(data_latch,
332 new SimpleValue("{ {"+(fpga.getWordWidth()-fpga.DataLatch_WIDTH)+
333 "{"+ondeck.getBits(fpga.SET_IMMEDIATE_EXTEND).getVerilog()+"}}, "+
334 ondeck.getBits(fpga.SET_IMMEDIATE).getVerilog()+" }"))),
335 new ConditionalAction(ondeck.testMask(fpga.SET_FLAGS),
336 new AssignAction(flag_a, new_flag(ondeck.getBits(fpga.SET_FLAGS_A),flag_a,flag_b,flag_c))),
337 new ConditionalAction(ondeck.testMask(fpga.SET_FLAGS),
338 new AssignAction(flag_b, new_flag(ondeck.getBits(fpga.SET_FLAGS_B),flag_a,flag_b,flag_c))),
339 new ConditionalAction(ondeck.testMask(fpga.MOVE),
340 new AssignAction(flag_c,
342 ? dfifo_out.getBits(dfifo_width-1, dfifo_width-1)
343 : new MuxValue(ondeck.testMask(fpga.DC),
344 ship_out.getBits(fpga.getWordWidth(), fpga.getWordWidth()),
345 dfifo_out.getBits(dfifo_width-1, dfifo_width-1))
347 new ConditionalAction(ondeck.testMask(fpga.DI), data_in),
348 new ConditionalAction(ondeck.testMask(fpga.DO), data_out),
349 new ConditionalAction(ondeck.testMask(fpga.FLUSH), data_out),
351 ? new AssignAction(new SimpleAssignable(data_out.getName()+"["+fpga.getWordWidth()+"]"),
352 new SimpleValue(fpga.FLUSH.verilog(ondeck.getName())+"?1:0"))
354 new ConditionalAction(ondeck.testMask(fpga.TI), token_in),
355 new ConditionalAction(ondeck.testMask(fpga.TO), token_out),
356 new ConditionalAction(ondeck.testMask(fpga.DC), new AssignAction(data_latch, data_latch_input)),
357 new AssignAction(token_out.getBits(fpga.PACKET_TOKEN),
358 new SimpleValue("("+fpga.TO.verilog(ondeck.getName())+")?1:0")),
359 new ConditionalAction(ondeck.testMask(fpga.PATH_DATA),
360 new AssignAction(new SimpleAssignable("{ "+token_out.getBits(fpga.PACKET_SIGNAL).getVerilog()+", "+
361 token_out.getBits(fpga.PACKET_DEST).getVerilog()+" }"),
362 data_latch_input.getBits(fpga.DISPATCH_PATH))),
363 new ConditionalAction(ondeck.testMask(fpga.PATH_IMMEDIATE),
364 new AssignAction(new SimpleAssignable("{ "+token_out.getBits(fpga.PACKET_SIGNAL).getVerilog()+", "+
365 token_out.getBits(fpga.PACKET_DEST).getVerilog()+" }"),
366 ondeck.getBits(fpga.PATH_IMMEDIATE)))
371 private Value new_flag(Value v, Value flag_a, Value flag_b, Value flag_c) {
372 Value[] vals = new Value[] {
373 new LogicValue(v.getBits(0,0), LogicValue.LogicType.AND, flag_c.invertBits()),
374 new LogicValue(v.getBits(1,1), LogicValue.LogicType.AND, flag_c),
375 new LogicValue(v.getBits(2,2), LogicValue.LogicType.AND, flag_b.invertBits()),
376 new LogicValue(v.getBits(3,3), LogicValue.LogicType.AND, flag_b),
377 new LogicValue(v.getBits(4,4), LogicValue.LogicType.AND, flag_a.invertBits()),
378 new LogicValue(v.getBits(5,5), LogicValue.LogicType.AND, flag_a),
380 Value ret = new ConstantValue(new BitVector(1).set(0));
381 for(int i=0; i<vals.length; i++)
382 ret = new LogicValue(ret, LogicValue.LogicType.OR, vals[i]);