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46 // /___/ \ / Vendor: Xilinx
47 // \ \ \/ Version: 2.3
48 // \ \ Application: MIG
49 // / / Filename: ddr2_mem_if_top.v
50 // /___/ /\ Date Last Modified: $Date: 2008/07/22 15:41:06 $
51 // \ \ / \ Date Created: Wed Aug 16 2006
55 //Design Name: DDR/DDR2
57 // Top-level for parameterizable (DDR or DDR2) memory interface
60 //*****************************************************************************
64 module ddr2_mem_if_top #
66 // Following parameters are for 72-bit RDIMM design (for ML561 Reference
67 // board design). Actual values may be different. Actual parameters values
68 // are passed from design top module ddr2_sdram module. Please refer to
69 // the ddr2_sdram module for actual values.
70 parameter BANK_WIDTH = 2,
71 parameter CKE_WIDTH = 1,
72 parameter CLK_WIDTH = 1,
73 parameter COL_WIDTH = 10,
74 parameter CS_BITS = 0,
76 parameter CS_WIDTH = 1,
77 parameter USE_DM_PORT = 1,
78 parameter DM_WIDTH = 9,
79 parameter DQ_WIDTH = 72,
80 parameter DQ_BITS = 7,
81 parameter DQ_PER_DQS = 8,
82 parameter DQS_BITS = 4,
83 parameter DQS_WIDTH = 9,
84 parameter HIGH_PERFORMANCE_MODE = "TRUE",
85 parameter ODT_WIDTH = 1,
86 parameter ROW_WIDTH = 14,
87 parameter APPDATA_WIDTH = 144,
88 parameter ADDITIVE_LAT = 0,
89 parameter BURST_LEN = 4,
90 parameter BURST_TYPE = 0,
91 parameter CAS_LAT = 5,
92 parameter ECC_ENABLE = 0,
93 parameter MULTI_BANK_EN = 1,
94 parameter TWO_T_TIME_EN = 0,
95 parameter ODT_TYPE = 1,
96 parameter DDR_TYPE = 1,
97 parameter REDUCE_DRV = 0,
98 parameter REG_ENABLE = 1,
99 parameter TREFI_NS = 7800,
100 parameter TRAS = 40000,
101 parameter TRCD = 15000,
102 parameter TRFC = 105000,
103 parameter TRP = 15000,
104 parameter TRTP = 7500,
105 parameter TWR = 15000,
106 parameter TWTR = 10000,
107 parameter CLK_PERIOD = 3000,
108 parameter SIM_ONLY = 0,
109 parameter DEBUG_EN = 0,
110 parameter DQS_IO_COL = 0,
111 parameter DQ_IO_MS = 0,
112 parameter EN_SYN = "FALSE"
121 //added by xtan & gdgib
122 input af_clk, //address fifo clk
123 input rb_clk, //read buffer clk
124 input wb_clk, //write buffer clk
125 input af_rst, //address fifo rst
126 input rb_rst, //read buffer rst
127 input wb_rst, //write buffer rst
128 output rb_full, //read buffer is full
130 input [2:0] app_af_cmd,
131 input [30:0] app_af_addr,
134 input [APPDATA_WIDTH-1:0] app_wdf_data,
135 input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
136 output [1:0] rd_ecc_error,
138 output app_wdf_afull,
139 output rd_data_valid,
141 output [APPDATA_WIDTH-1:0] rd_data_fifo_out,
142 output phy_init_done,
143 output [CLK_WIDTH-1:0] ddr_ck,
144 output [CLK_WIDTH-1:0] ddr_ck_n,
145 output [ROW_WIDTH-1:0] ddr_addr,
146 output [BANK_WIDTH-1:0] ddr_ba,
150 output [CS_WIDTH-1:0] ddr_cs_n,
151 output [CKE_WIDTH-1:0] ddr_cke,
152 output [ODT_WIDTH-1:0] ddr_odt,
153 output [DM_WIDTH-1:0] ddr_dm,
154 inout [DQS_WIDTH-1:0] ddr_dqs,
155 inout [DQS_WIDTH-1:0] ddr_dqs_n,
156 inout [DQ_WIDTH-1:0] ddr_dq,
157 // Debug signals (optional use)
158 input dbg_idel_up_all,
159 input dbg_idel_down_all,
160 input dbg_idel_up_dq,
161 input dbg_idel_down_dq,
162 input dbg_idel_up_dqs,
163 input dbg_idel_down_dqs,
164 input dbg_idel_up_gate,
165 input dbg_idel_down_gate,
166 input [DQ_BITS-1:0] dbg_sel_idel_dq,
167 input dbg_sel_all_idel_dq,
168 input [DQS_BITS:0] dbg_sel_idel_dqs,
169 input dbg_sel_all_idel_dqs,
170 input [DQS_BITS:0] dbg_sel_idel_gate,
171 input dbg_sel_all_idel_gate,
172 output [3:0] dbg_calib_done,
173 output [3:0] dbg_calib_err,
174 output [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt,
175 output [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt,
176 output [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt,
177 output [DQS_WIDTH-1:0] dbg_calib_rd_data_sel,
178 output [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly,
179 output [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly
185 wire [ROW_WIDTH-1:0] ctrl_addr;
187 wire [BANK_WIDTH-1:0] ctrl_ba;
189 wire [CS_NUM-1:0] ctrl_cs_n;
195 wire [DQS_WIDTH-1:0] phy_calib_rden;
196 wire [DQS_WIDTH-1:0] phy_calib_rden_sel;
197 wire [DQ_WIDTH-1:0] rd_data_fall;
198 wire [DQ_WIDTH-1:0] rd_data_rise;
199 wire [(2*DQ_WIDTH)-1:0] wdf_data;
200 wire [((2*DQ_WIDTH)/8)-1:0] wdf_mask_data;
202 wire wr_fifo_clear, wr_fifo_burst, rd_fifo_clear;
204 //***************************************************************************
208 .BANK_WIDTH (BANK_WIDTH),
209 .CKE_WIDTH (CKE_WIDTH),
210 .CLK_WIDTH (CLK_WIDTH),
211 .COL_WIDTH (COL_WIDTH),
213 .CS_WIDTH (CS_WIDTH),
214 .USE_DM_PORT (USE_DM_PORT),
215 .DM_WIDTH (DM_WIDTH),
216 .DQ_WIDTH (DQ_WIDTH),
218 .DQ_PER_DQS (DQ_PER_DQS),
219 .DQS_BITS (DQS_BITS),
220 .DQS_WIDTH (DQS_WIDTH),
221 .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
222 .ODT_WIDTH (ODT_WIDTH),
223 .ROW_WIDTH (ROW_WIDTH),
224 .TWO_T_TIME_EN (TWO_T_TIME_EN),
225 .ADDITIVE_LAT (ADDITIVE_LAT),
226 .BURST_LEN (BURST_LEN),
227 .BURST_TYPE (BURST_TYPE),
229 .ECC_ENABLE (ECC_ENABLE),
230 .ODT_TYPE (ODT_TYPE),
231 .DDR_TYPE (DDR_TYPE),
232 .REDUCE_DRV (REDUCE_DRV),
233 .REG_ENABLE (REG_ENABLE),
235 .CLK_PERIOD (CLK_PERIOD),
236 .SIM_ONLY (SIM_ONLY),
237 .DEBUG_EN (DEBUG_EN),
238 .DQS_IO_COL (DQS_IO_COL),
249 .ctrl_wren (ctrl_wren),
250 .ctrl_addr (ctrl_addr),
252 .ctrl_ras_n (ctrl_ras_n),
253 .ctrl_cas_n (ctrl_cas_n),
254 .ctrl_we_n (ctrl_we_n),
255 .ctrl_cs_n (ctrl_cs_n),
256 .ctrl_rden (ctrl_rden),
257 .ctrl_ref_flag (ctrl_ref_flag),
258 .wdf_data (wdf_data),
259 .wdf_mask_data (wdf_mask_data),
260 .wdf_rden (wdf_rden),
261 .phy_init_done (phy_init_done),
262 .phy_calib_rden (phy_calib_rden),
263 .phy_calib_rden_sel (phy_calib_rden_sel),
264 .rd_data_rise (rd_data_rise),
265 .rd_data_fall (rd_data_fall),
267 .ddr_ck_n (ddr_ck_n),
268 .ddr_addr (ddr_addr),
270 .ddr_ras_n (ddr_ras_n),
271 .ddr_cas_n (ddr_cas_n),
272 .ddr_we_n (ddr_we_n),
273 .ddr_cs_n (ddr_cs_n),
278 .ddr_dqs_n (ddr_dqs_n),
280 .dbg_idel_up_all (dbg_idel_up_all),
281 .dbg_idel_down_all (dbg_idel_down_all),
282 .dbg_idel_up_dq (dbg_idel_up_dq),
283 .dbg_idel_down_dq (dbg_idel_down_dq),
284 .dbg_idel_up_dqs (dbg_idel_up_dqs),
285 .dbg_idel_down_dqs (dbg_idel_down_dqs),
286 .dbg_idel_up_gate (dbg_idel_up_gate),
287 .dbg_idel_down_gate (dbg_idel_down_gate),
288 .dbg_sel_idel_dq (dbg_sel_idel_dq),
289 .dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),
290 .dbg_sel_idel_dqs (dbg_sel_idel_dqs),
291 .dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),
292 .dbg_sel_idel_gate (dbg_sel_idel_gate),
293 .dbg_sel_all_idel_gate (dbg_sel_all_idel_gate),
294 .dbg_calib_done (dbg_calib_done),
295 .dbg_calib_err (dbg_calib_err),
296 .dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),
297 .dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),
298 .dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
299 .dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),
300 .dbg_calib_rden_dly (dbg_calib_rden_dly),
301 .dbg_calib_gate_dly (dbg_calib_gate_dly)
306 .BANK_WIDTH (BANK_WIDTH),
307 .COL_WIDTH (COL_WIDTH),
309 .DQ_WIDTH (DQ_WIDTH),
310 .DQ_PER_DQS (DQ_PER_DQS),
311 .DQS_WIDTH (DQS_WIDTH),
312 .APPDATA_WIDTH (APPDATA_WIDTH),
313 .APPDATA_BURST_LEN(BURST_LEN * DQ_WIDTH / APPDATA_WIDTH),
314 .APPDATA_BURST_BITS(3),
315 .ECC_ENABLE (ECC_ENABLE),
316 .ROW_WIDTH (ROW_WIDTH),
331 .rd_data_in_rise (rd_data_rise),
332 .rd_data_in_fall (rd_data_fall),
333 .phy_calib_rden (phy_calib_rden),
334 .phy_calib_rden_sel(phy_calib_rden_sel),
335 .rd_data_valid (rd_data_valid),
336 .rd_data_rden (rd_data_rden),
337 .rd_ecc_error (rd_ecc_error),
338 .rd_data_fifo_out (rd_data_fifo_out),
339 .app_af_cmd (app_af_cmd),
340 .app_af_addr (app_af_addr),
341 .app_af_wren (app_af_wren),
342 .ctrl_af_rden (ctrl_af_rden),
345 .af_empty (af_empty),
346 .app_af_afull (app_af_afull),
347 .app_wdf_wren (app_wdf_wren),
348 .app_wdf_data (app_wdf_data),
349 .app_wdf_mask_data (app_wdf_mask_data),
350 .wdf_rden (wdf_rden),
351 .app_wdf_afull (app_wdf_afull),
352 .wdf_data (wdf_data),
353 .wdf_mask_data (wdf_mask_data),
354 .wr_fifo_clear (wr_fifo_clear),
355 .wr_fifo_burst (wr_fifo_burst),
356 .rd_fifo_clear (rd_fifo_clear)
362 .BANK_WIDTH (BANK_WIDTH),
363 .COL_WIDTH (COL_WIDTH),
366 .ROW_WIDTH (ROW_WIDTH),
367 .ADDITIVE_LAT (ADDITIVE_LAT),
368 .BURST_LEN (BURST_LEN),
370 .ECC_ENABLE (ECC_ENABLE),
371 .REG_ENABLE (REG_ENABLE),
372 .MULTI_BANK_EN (MULTI_BANK_EN),
373 .TWO_T_TIME_EN (TWO_T_TIME_EN),
374 .TREFI_NS (TREFI_NS),
382 .CLK_PERIOD (CLK_PERIOD),
391 .af_empty (af_empty),
392 .wr_fifo_clear (wr_fifo_clear),
393 .wr_fifo_burst (wr_fifo_burst),
394 .rd_fifo_clear (rd_fifo_clear),
395 .phy_init_done (phy_init_done),
396 .ctrl_ref_flag (ctrl_ref_flag),
397 .ctrl_af_rden (ctrl_af_rden),
398 .ctrl_wren (ctrl_wren),
399 .ctrl_rden (ctrl_rden),
400 .ctrl_addr (ctrl_addr),
402 .ctrl_ras_n (ctrl_ras_n),
403 .ctrl_cas_n (ctrl_cas_n),
404 .ctrl_we_n (ctrl_we_n),
405 .ctrl_cs_n (ctrl_cs_n)