src/edu/berkeley/fleet/fpga/greg/ddr2_phy_top.v

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  44 //   ____  ____
  45 //  /   /\/   /
  46 // /___/  \  /    Vendor: Xilinx
  47 // \   \   \/     Version: 2.3
  48 //  \   \         Application: MIG
  49 //  /   /         Filename: ddr2_phy_top.v
  50 // /___/   /\     Date Last Modified: $Date: 2008/07/22 15:41:06 $
  51 // \   \  /  \    Date Created: Wed Aug 16 2006
  52 //  \___\/\___\
  53 //
  54 //Device: Virtex-5
  55 //Design Name: DDR2
  56 //Purpose:
  57 //   Top-level for memory physical layer (PHY) interface
  58 //Reference:
  59 //Revision History:
  60 //*****************************************************************************
  61
  62 `timescale 1ns/1ps
  63
  64 (* X_CORE_INFO = "mig_v2_3_ddr2_v5, Coregen 10.1.02" , CORE_GENERATION_INFO = "ddr2_v5,mig_v2_3,{component_name=ddr2_phy_top, BANK_WIDTH=2, CKE_WIDTH=1, CLK_WIDTH=2, COL_WIDTH=10, CS_NUM=1, CS_WIDTH=1, DM_WIDTH=8, DQ_WIDTH=64, DQ_PER_DQS=8, DQS_WIDTH=8, ODT_WIDTH=1, ROW_WIDTH=13, ADDITIVE_LAT=0, BURST_LEN=4, BURST_TYPE=0, CAS_LAT=4, ECC_ENABLE=0, MULTI_BANK_EN=1, TWO_T_TIME_EN=1, ODT_TYPE=1, REDUCE_DRV=0, REG_ENABLE=0, TREFI_NS=7800, TRAS=40000, TRCD=15000, TRFC=105000, TRP=15000, TRTP=7500, TWR=15000, TWTR=7500, DDR2_CLK_PERIOD=3750, RST_ACT_LOW=1}" *)
  65 module ddr2_phy_top #
  66   (
  67    // Following parameters are for 72-bit RDIMM design (for ML561 Reference
  68    // board design). Actual values may be different. Actual parameters values
  69    // are passed from design top module ddr2_sdram module. Please refer to
  70    // the ddr2_sdram module for actual values.
  71    parameter BANK_WIDTH            = 2,
  72    parameter CLK_WIDTH             = 1,
  73    parameter CKE_WIDTH             = 1,
  74    parameter COL_WIDTH             = 10,
  75    parameter CS_NUM                = 1,
  76    parameter CS_WIDTH              = 1,
  77    parameter USE_DM_PORT           = 1,
  78    parameter DM_WIDTH              = 9,
  79    parameter DQ_WIDTH              = 72,
  80    parameter DQ_BITS               = 7,
  81    parameter DQ_PER_DQS            = 8,
  82    parameter DQS_WIDTH             = 9,
  83    parameter DQS_BITS              = 4,
  84    parameter HIGH_PERFORMANCE_MODE = "TRUE",
  85    parameter ODT_WIDTH             = 1,
  86    parameter ROW_WIDTH             = 14,
  87    parameter ADDITIVE_LAT          = 0,
  88    parameter TWO_T_TIME_EN         = 0,
  89    parameter BURST_LEN             = 4,
  90    parameter BURST_TYPE            = 0,
  91    parameter CAS_LAT               = 5,
  92    parameter TWR                   = 15000,
  93    parameter ECC_ENABLE            = 0,
  94    parameter ODT_TYPE              = 1,
  95    parameter DDR_TYPE              = 1,
  96    parameter REDUCE_DRV            = 0,
  97    parameter REG_ENABLE            = 1,
  98    parameter CLK_PERIOD            = 3000,
  99    parameter SIM_ONLY              = 0,
 100    parameter DEBUG_EN              = 0,
 101    parameter DQS_IO_COL            = 0,
 102    parameter DQ_IO_MS              = 0
 103    )
 104   (
 105    input                                  clk0,
 106    input                                  clk90,
 107    input                                  clkdiv0,
 108    input                                  rst0,
 109    input                                  rst90,
 110    input                                  rstdiv0,
 111    input                                  ctrl_wren,
 112    input [ROW_WIDTH-1:0]                  ctrl_addr,
 113    input [BANK_WIDTH-1:0]                 ctrl_ba,
 114    input                                  ctrl_ras_n,
 115    input                                  ctrl_cas_n,
 116    input                                  ctrl_we_n,
 117    input [CS_NUM-1:0]                     ctrl_cs_n,
 118    input                                  ctrl_rden,
 119    input                                  ctrl_ref_flag,
 120    input [(2*DQ_WIDTH)-1:0]               wdf_data,
 121    input [(2*DQ_WIDTH/8)-1:0]             wdf_mask_data,
 122    output                                 wdf_rden,
 123    output                                 phy_init_done,
 124    output [DQS_WIDTH-1:0]                 phy_calib_rden,
 125    output [DQS_WIDTH-1:0]                 phy_calib_rden_sel,
 126    output [DQ_WIDTH-1:0]                  rd_data_rise,
 127    output [DQ_WIDTH-1:0]                  rd_data_fall,
 128    output [CLK_WIDTH-1:0]                 ddr_ck,
 129    output [CLK_WIDTH-1:0]                 ddr_ck_n,
 130    output [ROW_WIDTH-1:0]                 ddr_addr,
 131    output [BANK_WIDTH-1:0]                ddr_ba,
 132    output                                 ddr_ras_n,
 133    output                                 ddr_cas_n,
 134    output                                 ddr_we_n,
 135    output [CS_WIDTH-1:0]                  ddr_cs_n,
 136    output [CKE_WIDTH-1:0]                 ddr_cke,
 137    output [ODT_WIDTH-1:0]                 ddr_odt,
 138    output [DM_WIDTH-1:0]                  ddr_dm,
 139    inout [DQS_WIDTH-1:0]                  ddr_dqs,
 140    inout [DQS_WIDTH-1:0]                  ddr_dqs_n,
 141    inout [DQ_WIDTH-1:0]                   ddr_dq,
 142    // Debug signals (optional use)
 143    input                                  dbg_idel_up_all,
 144    input                                  dbg_idel_down_all,
 145    input                                  dbg_idel_up_dq,
 146    input                                  dbg_idel_down_dq,
 147    input                                  dbg_idel_up_dqs,
 148    input                                  dbg_idel_down_dqs,
 149    input                                  dbg_idel_up_gate,
 150    input                                  dbg_idel_down_gate,
 151    input [DQ_BITS-1:0]                    dbg_sel_idel_dq,
 152    input                                  dbg_sel_all_idel_dq,
 153    input [DQS_BITS:0]                     dbg_sel_idel_dqs,
 154    input                                  dbg_sel_all_idel_dqs,
 155    input [DQS_BITS:0]                     dbg_sel_idel_gate,
 156    input                                  dbg_sel_all_idel_gate,
 157    output [3:0]                           dbg_calib_done,
 158    output [3:0]                           dbg_calib_err,
 159    output [(6*DQ_WIDTH)-1:0]              dbg_calib_dq_tap_cnt,
 160    output [(6*DQS_WIDTH)-1:0]             dbg_calib_dqs_tap_cnt,
 161    output [(6*DQS_WIDTH)-1:0]             dbg_calib_gate_tap_cnt,
 162    output [DQS_WIDTH-1:0]                 dbg_calib_rd_data_sel,
 163    output [(5*DQS_WIDTH)-1:0]             dbg_calib_rden_dly,
 164    output [(5*DQS_WIDTH)-1:0]             dbg_calib_gate_dly
 165    );
 166
 167   wire [3:0]               calib_done;
 168   wire                     calib_ref_done;
 169   wire                     calib_ref_req;
 170   wire [3:0]               calib_start;
 171   wire                     dm_ce;
 172   wire [1:0]               dq_oe_n;
 173   wire                     dqs_oe_n;
 174   wire                     dqs_rst_n;
 175   wire [(DQ_WIDTH/8)-1:0]  mask_data_fall;
 176   wire [(DQ_WIDTH/8)-1:0]  mask_data_rise;
 177   wire [CS_NUM-1:0]        odt;
 178   wire [ROW_WIDTH-1:0]     phy_init_addr;
 179   wire [BANK_WIDTH-1:0]    phy_init_ba;
 180   wire                     phy_init_cas_n;
 181   wire [CKE_WIDTH-1:0]     phy_init_cke;
 182   wire [CS_NUM-1:0]        phy_init_cs_n;
 183   wire                     phy_init_data_sel;
 184   wire                     phy_init_ras_n;
 185   wire                     phy_init_rden;
 186   wire                     phy_init_we_n;
 187   wire                     phy_init_wren;
 188   wire [DQ_WIDTH-1:0]      wr_data_fall;
 189   wire [DQ_WIDTH-1:0]      wr_data_rise;
 190
 191   //***************************************************************************
 192
 193   ddr2_phy_write #
 194     (
 195      .DQ_WIDTH     (DQ_WIDTH),
 196      .CS_NUM       (CS_NUM),
 197      .ADDITIVE_LAT (ADDITIVE_LAT),
 198      .CAS_LAT      (CAS_LAT),
 199      .ECC_ENABLE   (ECC_ENABLE),
 200      .ODT_TYPE     (ODT_TYPE),
 201      .REG_ENABLE   (REG_ENABLE),
 202      .DDR_TYPE     (DDR_TYPE)
 203      )
 204     u_phy_write
 205       (
 206        .clk0                    (clk0),
 207        .clk90                   (clk90),
 208        .rst90                   (rst90),
 209        .wdf_data                (wdf_data),
 210        .wdf_mask_data           (wdf_mask_data),
 211        .ctrl_wren               (ctrl_wren),
 212        .phy_init_wren           (phy_init_wren),
 213        .phy_init_data_sel       (phy_init_data_sel),
 214        .dm_ce                   (dm_ce),
 215        .dq_oe_n                 (dq_oe_n),
 216        .dqs_oe_n                (dqs_oe_n),
 217        .dqs_rst_n               (dqs_rst_n),
 218        .wdf_rden                (wdf_rden),
 219        .odt                     (odt),
 220        .wr_data_rise            (wr_data_rise),
 221        .wr_data_fall            (wr_data_fall),
 222        .mask_data_rise          (mask_data_rise),
 223        .mask_data_fall          (mask_data_fall)
 224        );
 225
 226   ddr2_phy_io #
 227     (
 228      .CLK_WIDTH             (CLK_WIDTH),
 229      .USE_DM_PORT           (USE_DM_PORT),
 230      .DM_WIDTH              (DM_WIDTH),
 231      .DQ_WIDTH              (DQ_WIDTH),
 232      .DQ_BITS               (DQ_BITS),
 233      .DQ_PER_DQS            (DQ_PER_DQS),
 234      .DQS_BITS              (DQS_BITS),
 235      .DQS_WIDTH             (DQS_WIDTH),
 236      .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
 237      .ODT_WIDTH             (ODT_WIDTH),
 238      .ADDITIVE_LAT          (ADDITIVE_LAT),
 239      .CAS_LAT               (CAS_LAT),
 240      .REG_ENABLE            (REG_ENABLE),
 241      .CLK_PERIOD            (CLK_PERIOD),
 242      .DDR_TYPE              (DDR_TYPE),
 243      .SIM_ONLY              (SIM_ONLY),
 244      .DEBUG_EN              (DEBUG_EN),
 245      .DQS_IO_COL            (DQS_IO_COL),
 246      .DQ_IO_MS              (DQ_IO_MS)
 247      )
 248     u_phy_io
 249       (
 250        .clk0                   (clk0),
 251        .clk90                  (clk90),
 252        .clkdiv0                (clkdiv0),
 253        .rst0                   (rst0),
 254        .rst90                  (rst90),
 255        .rstdiv0                (rstdiv0),
 256        .dm_ce                  (dm_ce),
 257        .dq_oe_n                (dq_oe_n),
 258        .dqs_oe_n               (dqs_oe_n),
 259        .dqs_rst_n              (dqs_rst_n),
 260        .calib_start            (calib_start),
 261        .ctrl_rden              (ctrl_rden),
 262        .phy_init_rden          (phy_init_rden),
 263        .calib_ref_done         (calib_ref_done),
 264        .calib_done             (calib_done),
 265        .calib_ref_req          (calib_ref_req),
 266        .calib_rden             (phy_calib_rden),
 267        .calib_rden_sel         (phy_calib_rden_sel),
 268        .wr_data_rise           (wr_data_rise),
 269        .wr_data_fall           (wr_data_fall),
 270        .mask_data_rise         (mask_data_rise),
 271        .mask_data_fall         (mask_data_fall),
 272        .rd_data_rise           (rd_data_rise),
 273        .rd_data_fall           (rd_data_fall),
 274        .ddr_ck                 (ddr_ck),
 275        .ddr_ck_n               (ddr_ck_n),
 276        .ddr_dm                 (ddr_dm),
 277        .ddr_dqs                (ddr_dqs),
 278        .ddr_dqs_n              (ddr_dqs_n),
 279        .ddr_dq                 (ddr_dq),
 280        .dbg_idel_up_all        (dbg_idel_up_all),
 281        .dbg_idel_down_all      (dbg_idel_down_all),
 282        .dbg_idel_up_dq         (dbg_idel_up_dq),
 283        .dbg_idel_down_dq       (dbg_idel_down_dq),
 284        .dbg_idel_up_dqs        (dbg_idel_up_dqs),
 285        .dbg_idel_down_dqs      (dbg_idel_down_dqs),
 286        .dbg_idel_up_gate       (dbg_idel_up_gate),
 287        .dbg_idel_down_gate     (dbg_idel_down_gate),
 288        .dbg_sel_idel_dq        (dbg_sel_idel_dq),
 289        .dbg_sel_all_idel_dq    (dbg_sel_all_idel_dq),
 290        .dbg_sel_idel_dqs       (dbg_sel_idel_dqs),
 291        .dbg_sel_all_idel_dqs   (dbg_sel_all_idel_dqs),
 292        .dbg_sel_idel_gate      (dbg_sel_idel_gate),
 293        .dbg_sel_all_idel_gate  (dbg_sel_all_idel_gate),
 294        .dbg_calib_done         (dbg_calib_done),
 295        .dbg_calib_err          (dbg_calib_err),
 296        .dbg_calib_dq_tap_cnt   (dbg_calib_dq_tap_cnt),
 297        .dbg_calib_dqs_tap_cnt  (dbg_calib_dqs_tap_cnt),
 298        .dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
 299        .dbg_calib_rd_data_sel  (dbg_calib_rd_data_sel),
 300        .dbg_calib_rden_dly     (dbg_calib_rden_dly),
 301        .dbg_calib_gate_dly     (dbg_calib_gate_dly)
 302        );
 303
 304   ddr2_phy_ctl_io #
 305     (
 306      .BANK_WIDTH    (BANK_WIDTH),
 307      .CKE_WIDTH     (CKE_WIDTH),
 308      .COL_WIDTH     (COL_WIDTH),
 309      .CS_NUM        (CS_NUM),
 310      .CS_WIDTH      (CS_WIDTH),
 311      .TWO_T_TIME_EN (TWO_T_TIME_EN),
 312      .ODT_WIDTH     (ODT_WIDTH),
 313      .ROW_WIDTH     (ROW_WIDTH),
 314      .DDR_TYPE      (DDR_TYPE)
 315      )
 316     u_phy_ctl_io
 317       (
 318        .clk0                    (clk0),
 319        .clk90                   (clk90),
 320        .rst0                    (rst0),
 321        .rst90                   (rst90),
 322        .ctrl_addr               (ctrl_addr),
 323        .ctrl_ba                 (ctrl_ba),
 324        .ctrl_ras_n              (ctrl_ras_n),
 325        .ctrl_cas_n              (ctrl_cas_n),
 326        .ctrl_we_n               (ctrl_we_n),
 327        .ctrl_cs_n               (ctrl_cs_n),
 328        .phy_init_addr           (phy_init_addr),
 329        .phy_init_ba             (phy_init_ba),
 330        .phy_init_ras_n          (phy_init_ras_n),
 331        .phy_init_cas_n          (phy_init_cas_n),
 332        .phy_init_we_n           (phy_init_we_n),
 333        .phy_init_cs_n           (phy_init_cs_n),
 334        .phy_init_cke            (phy_init_cke),
 335        .phy_init_data_sel       (phy_init_data_sel),
 336        .odt                     (odt),
 337        .ddr_addr                (ddr_addr),
 338        .ddr_ba                  (ddr_ba),
 339        .ddr_ras_n               (ddr_ras_n),
 340        .ddr_cas_n               (ddr_cas_n),
 341        .ddr_we_n                (ddr_we_n),
 342        .ddr_cke                 (ddr_cke),
 343        .ddr_cs_n                (ddr_cs_n),
 344        .ddr_odt                 (ddr_odt)
 345        );
 346
 347   ddr2_phy_init #
 348     (
 349      .BANK_WIDTH   (BANK_WIDTH),
 350      .CKE_WIDTH    (CKE_WIDTH),
 351      .COL_WIDTH    (COL_WIDTH),
 352      .CS_NUM       (CS_NUM),
 353      .DQ_WIDTH     (DQ_WIDTH),
 354      .ODT_WIDTH    (ODT_WIDTH),
 355      .ROW_WIDTH    (ROW_WIDTH),
 356      .ADDITIVE_LAT (ADDITIVE_LAT),
 357      .BURST_LEN    (BURST_LEN),
 358      .BURST_TYPE   (BURST_TYPE),
 359      .TWO_T_TIME_EN(TWO_T_TIME_EN),
 360      .CAS_LAT      (CAS_LAT),
 361      .ODT_TYPE     (ODT_TYPE),
 362      .REDUCE_DRV   (REDUCE_DRV),
 363      .REG_ENABLE   (REG_ENABLE),
 364      .TWR          (TWR),
 365      .CLK_PERIOD   (CLK_PERIOD),
 366      .DDR_TYPE     (DDR_TYPE),
 367      .SIM_ONLY     (SIM_ONLY)
 368      )
 369     u_phy_init
 370       (
 371        .clk0                    (clk0),
 372        .clkdiv0                 (clkdiv0),
 373        .rst0                    (rst0),
 374        .rstdiv0                 (rstdiv0),
 375        .calib_done              (calib_done),
 376        .ctrl_ref_flag           (ctrl_ref_flag),
 377        .calib_ref_req           (calib_ref_req),
 378        .calib_start             (calib_start),
 379        .calib_ref_done          (calib_ref_done),
 380        .phy_init_wren           (phy_init_wren),
 381        .phy_init_rden           (phy_init_rden),
 382        .phy_init_addr           (phy_init_addr),
 383        .phy_init_ba             (phy_init_ba),
 384        .phy_init_ras_n          (phy_init_ras_n),
 385        .phy_init_cas_n          (phy_init_cas_n),
 386        .phy_init_we_n           (phy_init_we_n),
 387        .phy_init_cs_n           (phy_init_cs_n),
 388        .phy_init_cke            (phy_init_cke),
 389        .phy_init_done           (phy_init_done),
 390        .phy_init_data_sel       (phy_init_data_sel)
 391        );
 392
 393 endmodule