1 //*****************************************************************************
2 // DISCLAIMER OF LIABILITY
4 // This text/file contains proprietary, confidential
5 // information of Xilinx, Inc., is distributed under license
6 // from Xilinx, Inc., and may be used, copied and/or
7 // disclosed only pursuant to the terms of a valid license
8 // agreement with Xilinx, Inc. Xilinx hereby grants you a
9 // license to use this text/file solely for design, simulation,
10 // implementation and creation of design files limited
11 // to Xilinx devices or technologies. Use with non-Xilinx
12 // devices or technologies is expressly prohibited and
13 // immediately terminates your license unless covered by
14 // a separate agreement.
16 // Xilinx is providing this design, code, or information
17 // "as-is" solely for use in developing programs and
18 // solutions for Xilinx devices, with no obligation on the
19 // part of Xilinx to provide support. By providing this design,
20 // code, or information as one possible implementation of
21 // this feature, application or standard, Xilinx is making no
22 // representation that this implementation is free from any
23 // claims of infringement. You are responsible for
24 // obtaining any rights you may require for your implementation.
25 // Xilinx expressly disclaims any warranty whatsoever with
26 // respect to the adequacy of the implementation, including
27 // but not limited to any warranties or representations that this
28 // implementation is free from claims of infringement, implied
29 // warranties of merchantability or fitness for a particular
32 // Xilinx products are not intended for use in life support
33 // appliances, devices, or systems. Use in such applications is
34 // expressly prohibited.
36 // Any modifications that are made to the Source Code are
37 // done at the user
\92s sole risk and will be unsupported.
39 // Copyright (c) 2006-2007 Xilinx, Inc. All rights reserved.
41 // This copyright and support notice must be retained as part
42 // of this text at all times.
43 //*****************************************************************************
46 // /___/ \ / Vendor: Xilinx
47 // \ \ \/ Version: 2.3
48 // \ \ Application: MIG
49 // / / Filename: ddr2_top.v
50 // /___/ /\ Date Last Modified: $Date: 2008/07/29 15:24:03 $
51 // \ \ / \ Date Created: Wed Aug 16 2006
57 // System level module. This level contains just the memory controller.
58 // This level will be intiantated when the user wants to remove the
59 // synthesizable test bench, IDELAY control block and the clock
60 // generation modules.
63 //*****************************************************************************
69 // Following parameters are for 72-bit RDIMM design (for ML561 Reference
70 // board design). Actual values may be different. Actual parameters values
71 // are passed from design top module ddr2_sdram module. Please refer to
72 // the ddr2_sdram module for actual values.
73 parameter BANK_WIDTH = 2, // # of memory bank addr bits
74 parameter CKE_WIDTH = 1, // # of memory clock enable outputs
75 parameter CLK_WIDTH = 1, // # of clock outputs
76 parameter COL_WIDTH = 10, // # of memory column bits
77 parameter CS_NUM = 1, // # of separate memory chip selects
78 parameter CS_BITS = 0, // set to log2(CS_NUM) (rounded up)
79 parameter CS_WIDTH = 1, // # of total memory chip selects
80 parameter USE_DM_PORT = 1, // enable Data Mask (=1 enable)
81 parameter DM_WIDTH = 9, // # of data mask bits
82 parameter DQ_WIDTH = 72, // # of data width
83 parameter DQ_BITS = 7, // set to log2(DQS_WIDTH*DQ_PER_DQS)
84 parameter DQ_PER_DQS = 8, // # of DQ data bits per strobe
85 parameter DQS_WIDTH = 9, // # of DQS strobes
86 parameter DQS_BITS = 4, // set to log2(DQS_WIDTH)
87 parameter HIGH_PERFORMANCE_MODE = "TRUE", // IODELAY Performance Mode
88 parameter ODT_WIDTH = 1, // # of memory on-die term enables
89 parameter ROW_WIDTH = 14, // # of memory row & # of addr bits
90 parameter APPDATA_WIDTH = 144, // # of usr read/write data bus bits
91 parameter ADDITIVE_LAT = 0, // additive write latency
92 parameter BURST_LEN = 4, // burst length (in double words)
93 parameter BURST_TYPE = 0, // burst type (=0 seq; =1 interlved)
94 parameter CAS_LAT = 5, // CAS latency
95 parameter ECC_ENABLE = 0, // enable ECC (=1 enable)
96 parameter ODT_TYPE = 1, // ODT (=0(none),=1(75),=2(150),=3(50))
97 parameter MULTI_BANK_EN = 1, // enable bank management
98 parameter TWO_T_TIME_EN = 0, // 2t timing for unbuffered dimms
99 parameter REDUCE_DRV = 0, // reduced strength mem I/O (=1 yes)
100 parameter REG_ENABLE = 1, // registered addr/ctrl (=1 yes)
101 parameter TREFI_NS = 7800, // auto refresh interval (ns)
102 parameter TRAS = 40000, // active->precharge delay
103 parameter TRCD = 15000, // active->read/write delay
104 parameter TRFC = 105000, // ref->ref, ref->active delay
105 parameter TRP = 15000, // precharge->command delay
106 parameter TRTP = 7500, // read->precharge delay
107 parameter TWR = 15000, // used to determine wr->prech
108 parameter TWTR = 10000, // write->read delay
109 parameter CLK_PERIOD = 3000, // Core/Mem clk period (in ps)
110 parameter SIM_ONLY = 0, // = 1 to skip power up delay
111 parameter DEBUG_EN = 0, // Enable debug signals/controls
112 parameter DQS_IO_COL = 0, // I/O column location of DQS groups
113 parameter DQ_IO_MS = 0, // Master/Slave location of DQ I/O
114 parameter EN_SYN = "FALSE"
123 //added by xtan & gdgib
124 input af_clk, //address fifo clk
125 input rb_clk, //read buffer clk
126 input wb_clk, //write buffer clk
127 input af_rst, //address fifo rst
128 input rb_rst, //read buffer rst
129 input wb_rst, //write buffer rst
130 output rb_full, //read buffer is full
132 input [2:0] app_af_cmd,
133 input [30:0] app_af_addr,
136 input [APPDATA_WIDTH-1:0] app_wdf_data,
137 input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
139 output app_wdf_afull,
140 output rd_data_valid,
142 output [APPDATA_WIDTH-1:0] rd_data_fifo_out,
143 output [1:0] rd_ecc_error,
144 output phy_init_done,
145 output [CLK_WIDTH-1:0] ddr2_ck,
146 output [CLK_WIDTH-1:0] ddr2_ck_n,
147 output [ROW_WIDTH-1:0] ddr2_a,
148 output [BANK_WIDTH-1:0] ddr2_ba,
152 output [CS_WIDTH-1:0] ddr2_cs_n,
153 output [CKE_WIDTH-1:0] ddr2_cke,
154 output [ODT_WIDTH-1:0] ddr2_odt,
155 output [DM_WIDTH-1:0] ddr2_dm,
156 inout [DQS_WIDTH-1:0] ddr2_dqs,
157 inout [DQS_WIDTH-1:0] ddr2_dqs_n,
158 inout [DQ_WIDTH-1:0] ddr2_dq,
159 // Debug signals (optional use)
160 input dbg_idel_up_all,
161 input dbg_idel_down_all,
162 input dbg_idel_up_dq,
163 input dbg_idel_down_dq,
164 input dbg_idel_up_dqs,
165 input dbg_idel_down_dqs,
166 input dbg_idel_up_gate,
167 input dbg_idel_down_gate,
168 input [DQ_BITS-1:0] dbg_sel_idel_dq,
169 input dbg_sel_all_idel_dq,
170 input [DQS_BITS:0] dbg_sel_idel_dqs,
171 input dbg_sel_all_idel_dqs,
172 input [DQS_BITS:0] dbg_sel_idel_gate,
173 input dbg_sel_all_idel_gate,
174 output [3:0] dbg_calib_done,
175 output [3:0] dbg_calib_err,
176 output [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt,
177 output [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt,
178 output [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt,
179 output [DQS_WIDTH-1:0] dbg_calib_rd_data_sel,
180 output [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly,
181 output [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly
184 // memory initialization/control logic
187 .BANK_WIDTH (BANK_WIDTH),
188 .CKE_WIDTH (CKE_WIDTH),
189 .CLK_WIDTH (CLK_WIDTH),
190 .COL_WIDTH (COL_WIDTH),
193 .CS_WIDTH (CS_WIDTH),
194 .USE_DM_PORT (USE_DM_PORT),
195 .DM_WIDTH (DM_WIDTH),
196 .DQ_WIDTH (DQ_WIDTH),
198 .DQ_PER_DQS (DQ_PER_DQS),
199 .DQS_BITS (DQS_BITS),
200 .DQS_WIDTH (DQS_WIDTH),
201 .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
202 .ODT_WIDTH (ODT_WIDTH),
203 .ROW_WIDTH (ROW_WIDTH),
204 .APPDATA_WIDTH (APPDATA_WIDTH),
205 .ADDITIVE_LAT (ADDITIVE_LAT),
206 .BURST_LEN (BURST_LEN),
207 .BURST_TYPE (BURST_TYPE),
209 .ECC_ENABLE (ECC_ENABLE),
210 .MULTI_BANK_EN (MULTI_BANK_EN),
211 .TWO_T_TIME_EN (TWO_T_TIME_EN),
212 .ODT_TYPE (ODT_TYPE),
214 .REDUCE_DRV (REDUCE_DRV),
215 .REG_ENABLE (REG_ENABLE),
216 .TREFI_NS (TREFI_NS),
224 .CLK_PERIOD (CLK_PERIOD),
225 .SIM_ONLY (SIM_ONLY),
226 .DEBUG_EN (DEBUG_EN),
227 .DQS_IO_COL (DQS_IO_COL),
228 .DQ_IO_MS (DQ_IO_MS),
246 .app_af_cmd (app_af_cmd),
247 .app_af_addr (app_af_addr),
248 .app_af_wren (app_af_wren),
249 .app_wdf_wren (app_wdf_wren),
250 .app_wdf_data (app_wdf_data),
251 .app_wdf_mask_data (app_wdf_mask_data),
252 .app_af_afull (app_af_afull),
253 .app_wdf_afull (app_wdf_afull),
254 .rd_data_valid (rd_data_valid),
255 .rd_data_rden (rd_data_rden),
256 .rd_data_fifo_out (rd_data_fifo_out),
257 .rd_ecc_error (rd_ecc_error),
258 .phy_init_done (phy_init_done),
260 .ddr_ck_n (ddr2_ck_n),
263 .ddr_ras_n (ddr2_ras_n),
264 .ddr_cas_n (ddr2_cas_n),
265 .ddr_we_n (ddr2_we_n),
266 .ddr_cs_n (ddr2_cs_n),
271 .ddr_dqs_n (ddr2_dqs_n),
273 .dbg_idel_up_all (dbg_idel_up_all),
274 .dbg_idel_down_all (dbg_idel_down_all),
275 .dbg_idel_up_dq (dbg_idel_up_dq),
276 .dbg_idel_down_dq (dbg_idel_down_dq),
277 .dbg_idel_up_dqs (dbg_idel_up_dqs),
278 .dbg_idel_down_dqs (dbg_idel_down_dqs),
279 .dbg_idel_up_gate (dbg_idel_up_gate),
280 .dbg_idel_down_gate (dbg_idel_down_gate),
281 .dbg_sel_idel_dq (dbg_sel_idel_dq),
282 .dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),
283 .dbg_sel_idel_dqs (dbg_sel_idel_dqs),
284 .dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),
285 .dbg_sel_idel_gate (dbg_sel_idel_gate),
286 .dbg_sel_all_idel_gate (dbg_sel_all_idel_gate),
287 .dbg_calib_done (dbg_calib_done),
288 .dbg_calib_err (dbg_calib_err),
289 .dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),
290 .dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),
291 .dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
292 .dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),
293 .dbg_calib_rden_dly (dbg_calib_rden_dly),
294 .dbg_calib_gate_dly (dbg_calib_gate_dly)