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43 //*****************************************************************************
46 // /___/ \ / Vendor: Xilinx
47 // \ \ \/ Version: 2.3
48 // \ \ Application: MIG
49 // / / Filename: ddr2_usr_addr_fifo.v
50 // /___/ /\ Date Last Modified: $Date: 2008/05/08 15:20:47 $
51 // \ \ / \ Date Created: Mon Aug 28 2006
57 // This module instantiates the block RAM based FIFO to store the user
58 // address and the command information. Also calculates potential bank/row
59 // conflicts by comparing the new address with last address issued.
62 //*****************************************************************************
66 module ddr2_usr_addr_fifo #
68 // Following parameters are for 72-bit RDIMM design (for ML561 Reference
69 // board design). Actual values may be different. Actual parameters values
70 // are passed from design top module ddr2_sdram module. Please refer to
71 // the ddr2_sdram module for actual values.
72 parameter BANK_WIDTH = 2,
73 parameter COL_WIDTH = 10,
74 parameter CS_BITS = 0,
75 parameter ROW_WIDTH = 14,
76 parameter EN_SYN = "FALSE"
79 input clk0, //ddr2 phy clock
81 //start new port by xtan & gdgib
82 input af_clk, //user side clock
83 input af_rst, //user side reset
84 //end new port by xtan & gdgib
85 input [2:0] app_af_cmd,
86 input [30:0] app_af_addr,
90 output [30:0] af_addr,
95 wire [35:0] fifo_data_out;
99 always @(posedge clk0)
103 //***************************************************************************
105 assign af_cmd = fifo_data_out[33:31];
106 assign af_addr = fifo_data_out[30:0];
108 //***************************************************************************
112 .ALMOST_EMPTY_OFFSET (13'h0007),
113 .ALMOST_FULL_OFFSET (13'h000F),
117 .FIRST_WORD_FALL_THROUGH ("FALSE")
122 .ALMOSTFULL (app_af_afull),
123 .DO (fifo_data_out[31:0]),
124 .DOP (fifo_data_out[35:32]),
131 .DI ({app_af_cmd[0],app_af_addr}),
132 .DIP ({2'b00,app_af_cmd[2:1]}),
134 .RDEN (ctrl_af_rden),
135 .RST (rst_r | af_rst),
136 .WRCLK (af_clk), //changed by xtan: clk0 -> af_clk