src/edu/berkeley/fleet/fpga/main.ucf

   1 ############################################################################
   2 ## This system.ucf file is generated by Base System Builder based on the
   3 ## settings in the selected Xilinx Board Definition file. Please add other
   4 ## user constraints to this file based on customer design specifications.
   5 ############################################################################
   6
   7 #Net fpga_0_PCI32_BRIDGE_PCI_INTA LOC=P5;
   8 #Net fpga_0_PCI32_BRIDGE_PCI_INTA IOSTANDARD = PCI33_3;
   9 #Net fpga_0_PCI32_BRIDGE_PCI_INTA TIG;
  10 #Net fpga_0_PCI32_BRIDGE_PCI_INTB LOC=R8;
  11 #Net fpga_0_PCI32_BRIDGE_PCI_INTB IOSTANDARD = PCI33_3;
  12 #Net fpga_0_PCI32_BRIDGE_PCI_INTB TIG;
  13 #Net fpga_0_PCI32_BRIDGE_PCI_INTC LOC=P9;
  14 #Net fpga_0_PCI32_BRIDGE_PCI_INTC IOSTANDARD = PCI33_3;
  15 #Net fpga_0_PCI32_BRIDGE_PCI_INTC TIG;
  16 #Net fpga_0_PCI32_BRIDGE_PCI_INTD LOC=V4;
  17 #Net fpga_0_PCI32_BRIDGE_PCI_INTD IOSTANDARD = PCI33_3;
  18 #Net fpga_0_PCI32_BRIDGE_PCI_INTD TIG;
  19 #Net fpga_0_PCI32_BRIDGE_PCI_SBR_INT LOC=AE21;
  20 #Net fpga_0_PCI32_BRIDGE_PCI_SBR_INT IOSTANDARD = LVCMOS25;
  21 #Net fpga_0_PCI32_BRIDGE_PCI_SBR_INT TIG;
  22 Net sys_clk_pin LOC=J16;
  23 Net sys_clk_pin IOSTANDARD = LVCMOS25;
  24 Net sys_rst_pin LOC=H7;
  25 Net sys_rst_pin PULLUP;
  26 Net sys_rst_pin IOSTANDARD = LVCMOS33;
  27 ### System level constraints
  28 #Net sys_clk_pin TNM_NET = sys_clk_pin;
  29 #TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
  30 #Net sys_rst_pin TIG;
  31 #NET "C405RSTCORERESETREQ" TPTHRU = "RST_GRP";
  32 #NET "C405RSTCHIPRESETREQ" TPTHRU = "RST_GRP";
  33 #NET "C405RSTSYSRESETREQ" TPTHRU = "RST_GRP";
  34 #TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS  TIG;
  35 #Net fpga_0_PCI_CLK_FB LOC=H17;
  36 #Net fpga_0_PCI_CLK_FB IOSTANDARD = LVCMOS25;
  37 #Net fpga_0_PCI_CLK_FB TNM_NET = PCI_CLK;
  38 #Net PCI32_BRIDGE/OPB_Clk TNM_NET = SYS_CLK;
  39 ##TIMESPEC TS_PCI_BUS = FROM PCI_CLK TO SYS_CLK 10000 ps;
  40 #TIMESPEC "TS_PCI_BUS" = FROM "PCI_CLK" TO "SYS_CLK" 9.9ns datapathonly;
  41 #TIMESPEC TS_BUS_PCI = FROM SYS_CLK TO PCI_CLK 30000 ps;
  42 #Net fpga_0_PCI_CLK_OUT0 LOC=V5;
  43 #Net fpga_0_PCI_CLK_OUT0 IOSTANDARD = PCI33_3;
  44 #Net fpga_0_PCI_CLK_OUT1 LOC=T11;
  45 #Net fpga_0_PCI_CLK_OUT1 IOSTANDARD = PCI33_3;
  46 #Net fpga_0_PCI_CLK_OUT2 LOC=U6;
  47 #Net fpga_0_PCI_CLK_OUT2 IOSTANDARD = PCI33_3;
  48 #Net fpga_0_PCI_CLK_OUT3 LOC=U7;
  49 #Net fpga_0_PCI_CLK_OUT3 IOSTANDARD = PCI33_3;
  50 #Net fpga_0_PCI_CLK_OUT4 LOC=U3;
  51 #Net fpga_0_PCI_CLK_OUT4 IOSTANDARD = PCI33_3;
  52 #Net fpga_0_PCI_CLK_OUT5 LOC=U5;
  53 #Net fpga_0_PCI_CLK_OUT5 IOSTANDARD = PCI33_3;
  54 #Net fpga_0_DDR_CLK_FB LOC=K18;
  55 #Net fpga_0_DDR_CLK_FB IOSTANDARD = LVCMOS25;
  56 #
  57 ### IO Devices constraints
  58 #
  59 ##### Module RS232_Uart_1 constraints
  60 #
  61 Net fpga_0_RS232_Uart_1_ctsN_pin LOC=G6;
  62 Net fpga_0_RS232_Uart_1_ctsN_pin IOSTANDARD = LVCMOS33;
  63 Net fpga_0_RS232_Uart_1_ctsN_pin TIG;
  64 Net fpga_0_RS232_Uart_1_rtsN_pin LOC=F6;
  65 Net fpga_0_RS232_Uart_1_rtsN_pin IOSTANDARD = LVCMOS33;
  66 Net fpga_0_RS232_Uart_1_rtsN_pin TIG;
  67
  68 Net fpga_0_RS232_Uart_1_sin_pin LOC=E6;
  69 Net fpga_0_RS232_Uart_1_sin_pin IOSTANDARD = LVCMOS33;
  70 Net fpga_0_RS232_Uart_1_sin_pin TIG;
  71 Net fpga_0_RS232_Uart_1_sin_pin PULLUP;
  72
  73 Net fpga_0_RS232_Uart_1_sout_pin LOC=D6;
  74 Net fpga_0_RS232_Uart_1_sout_pin IOSTANDARD = LVCMOS33;
  75 Net fpga_0_RS232_Uart_1_sout_pin TIG;
  76 Net fpga_0_RS232_Uart_1_sout_pin PULLUP;
  77
  78 ##### Module DDR_SDRAM_32Mx64 constraints
  79 #
  80 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<12> LOC=P24;
  81 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I;
  82 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<11> LOC=P22;
  83 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I;
  84 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<10> LOC=N22;
  85 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I;
  86 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<9> LOC=N23;
  87 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I;
  88 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<8> LOC=N24;
  89 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I;
  90 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<7> LOC=M23;
  91 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I;
  92 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<6> LOC=L24;
  93 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I;
  94 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<5> LOC=L25;
  95 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I;
  96 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<4> LOC=L26;
  97 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I;
  98 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<3> LOC=K23;
  99 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I;
 100 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<2> LOC=K24;
 101 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I;
 102 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<1> LOC=K26;
 103 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I;
 104 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<0> LOC=J24;
 105 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I;
 106 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<1> LOC=J25;
 107 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
 108 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<0> LOC=J26;
 109 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
 110 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_CASn_pin LOC=D26;
 111 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_CASn_pin IOSTANDARD = SSTL2_I;
 112 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_CKE_pin LOC=H14;
 113 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_CKE_pin IOSTANDARD = SSTL2_I;
 114 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_CSn_pin LOC=C27;
 115 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_CSn_pin IOSTANDARD = SSTL2_I;
 116 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_RASn_pin LOC=D27;
 117 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_RASn_pin IOSTANDARD = SSTL2_I;
 118 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_WEn_pin LOC=E27;
 119 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_WEn_pin IOSTANDARD = SSTL2_I;
 120 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<0> LOC=G23;
 121 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<0> IOSTANDARD = SSTL2_II;
 122 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<1> LOC=E23;
 123 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<1> IOSTANDARD = SSTL2_II;
 124 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<2> LOC=G22;
 125 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<2> IOSTANDARD = SSTL2_II;
 126 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<3> LOC=F21;
 127 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<3> IOSTANDARD = SSTL2_II;
 128 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<0> LOC=F25;
 129 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<0> IOSTANDARD = SSTL2_II;
 130 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<1> LOC=G25;
 131 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<1> IOSTANDARD = SSTL2_II;
 132 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<2> LOC=G20;
 133 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<2> IOSTANDARD = SSTL2_II;
 134 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<3> LOC=F20;
 135 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<3> IOSTANDARD = SSTL2_II;
 136 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<0> LOC=E22;
 137 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<0> IOSTANDARD = SSTL2_II;
 138 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<1> LOC=E24;
 139 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<1> IOSTANDARD = SSTL2_II;
 140 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<2> LOC=H24;
 141 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<2> IOSTANDARD = SSTL2_II;
 142 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<3> LOC=H25;
 143 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<3> IOSTANDARD = SSTL2_II;
 144 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<4> LOC=G26;
 145 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<4> IOSTANDARD = SSTL2_II;
 146 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<5> LOC=F26;
 147 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<5> IOSTANDARD = SSTL2_II;
 148 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<6> LOC=F24;
 149 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<6> IOSTANDARD = SSTL2_II;
 150 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<7> LOC=F23;
 151 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<7> IOSTANDARD = SSTL2_II;
 152 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<8> LOC=C28;
 153 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<8> IOSTANDARD = SSTL2_II;
 154 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<9> LOC=D25;
 155 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<9> IOSTANDARD = SSTL2_II;
 156 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<10> LOC=D24;
 157 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<10> IOSTANDARD = SSTL2_II;
 158 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<11> LOC=D22;
 159 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<11> IOSTANDARD = SSTL2_II;
 160 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<12> LOC=C25;
 161 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<12> IOSTANDARD = SSTL2_II;
 162 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<13> LOC=C24;
 163 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<13> IOSTANDARD = SSTL2_II;
 164 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<14> LOC=C23;
 165 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<14> IOSTANDARD = SSTL2_II;
 166 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<15> LOC=C22;
 167 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<15> IOSTANDARD = SSTL2_II;
 168 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<16> LOC=H22;
 169 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<16> IOSTANDARD = SSTL2_II;
 170 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<17> LOC=J22;
 171 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<17> IOSTANDARD = SSTL2_II;
 172 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<18> LOC=L21;
 173 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<18> IOSTANDARD = SSTL2_II;
 174 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<19> LOC=K21;
 175 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<19> IOSTANDARD = SSTL2_II;
 176 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<20> LOC=J21;
 177 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<20> IOSTANDARD = SSTL2_II;
 178 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<21> LOC=J20;
 179 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<21> IOSTANDARD = SSTL2_II;
 180 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<22> LOC=H20;
 181 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<22> IOSTANDARD = SSTL2_II;
 182 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<23> LOC=G21;
 183 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<23> IOSTANDARD = SSTL2_II;
 184 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<24> LOC=E21;
 185 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<24> IOSTANDARD = SSTL2_II;
 186 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<25> LOC=D21;
 187 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<25> IOSTANDARD = SSTL2_II;
 188 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<26> LOC=E19;
 189 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<26> IOSTANDARD = SSTL2_II;
 190 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<27> LOC=F19;
 191 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<27> IOSTANDARD = SSTL2_II;
 192 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<28> LOC=G18;
 193 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<28> IOSTANDARD = SSTL2_II;
 194 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<29> LOC=F18;
 195 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<29> IOSTANDARD = SSTL2_II;
 196 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<30> LOC=E18;
 197 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<30> IOSTANDARD = SSTL2_II;
 198 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<31> LOC=E17;
 199 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<31> IOSTANDARD = SSTL2_II;
 200 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clk_pin LOC=F28;
 201 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clk_pin IOSTANDARD = SSTL2_I;
 202 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn_pin LOC=E28;
 203 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn_pin IOSTANDARD = SSTL2_I;
 204 #
 205 ##### Module SPI_EEPROM constraints
 206 #
 207 #Net fpga_0_SPI_EEPROM_SCK_pin LOC=AF21;
 208 #Net fpga_0_SPI_EEPROM_SCK_pin IOSTANDARD = LVCMOS25;
 209 #Net fpga_0_SPI_EEPROM_SCK_pin TIG;
 210 #Net fpga_0_SPI_EEPROM_SCK_pin PULLUP;
 211 #Net fpga_0_SPI_EEPROM_MOSI_pin LOC=AH22;
 212 #Net fpga_0_SPI_EEPROM_MOSI_pin TIG;
 213 #Net fpga_0_SPI_EEPROM_MOSI_pin PULLUP;
 214 #Net fpga_0_SPI_EEPROM_MISO_pin LOC=AJ22;
 215 #Net fpga_0_SPI_EEPROM_MISO_pin TIG;
 216 #Net fpga_0_SPI_EEPROM_MISO_pin PULLUP;
 217 #Net fpga_0_SPI_EEPROM_SS_pin<0> LOC=AG22;
 218 #Net fpga_0_SPI_EEPROM_SS_pin<0> TIG;
 219 #Net fpga_0_SPI_EEPROM_SS_pin<0> PULLUP;
 220 #
 221 ##### Module LEDs_8Bit constraints
 222 #
 223 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> LOC=AF19;
 224 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
 225 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> TIG;
 226 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> LOC=AD5;
 227 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS33;
 228 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> TIG;
 229 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> LOC=AD6;
 230 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS33;
 231 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> TIG;
 232 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> LOC=AD7;
 233 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS33;
 234 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> TIG;
 235 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> LOC=AB8;
 236 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> IOSTANDARD = LVCMOS33;
 237 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> TIG;
 238 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> LOC=AC7;
 239 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> IOSTANDARD = LVCMOS33;
 240 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> TIG;
 241 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> LOC=AC9;
 242 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> IOSTANDARD = LVCMOS33;
 243 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> TIG;
 244 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> LOC=AC10;
 245 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> IOSTANDARD = LVCMOS33;
 246 #Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> TIG;
 247 #
 248 ##### Module LCD_OPTIONAL constraints
 249 #
 250 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<0> LOC=AH19;
 251 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
 252 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<0> TIG;
 253 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<1> LOC=AJ19;
 254 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
 255 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<1> TIG;
 256 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<2> LOC=AK19;
 257 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
 258 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<2> TIG;
 259 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<3> LOC=AG20;
 260 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
 261 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<3> TIG;
 262 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<4> LOC=AH20;
 263 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;
 264 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<4> TIG;
 265 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<5> LOC=AJ20;
 266 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<5> IOSTANDARD = LVCMOS25;
 267 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<5> TIG;
 268 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<6> LOC=AG21;
 269 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<6> IOSTANDARD = LVCMOS25;
 270 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<6> TIG;
 271 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<7> LOC=AJ21;
 272 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<7> IOSTANDARD = LVCMOS25;
 273 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<7> TIG;
 274 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<8> LOC=AK17;
 275 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<8> IOSTANDARD = LVCMOS25;
 276 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<8> TIG;
 277 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<9> LOC=AH18;
 278 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<9> IOSTANDARD = LVCMOS25;
 279 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<9> TIG;
 280 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<10> LOC=AK18;
 281 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<10> IOSTANDARD = LVCMOS25;
 282 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<10> TIG;
 283 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<11> LOC=AJ17;
 284 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<11> IOSTANDARD = LVCMOS25;
 285 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<11> TIG;
 286 #
 287 ##### Module pci_arbiter_0 constraints
 288 #
 289 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<1> LOC=T4;
 290 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<1> IOSTANDARD = PCI33_3;
 291 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<2> LOC=T5;
 292 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<2> IOSTANDARD = PCI33_3;
 293 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<3> LOC=U8;
 294 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<3> IOSTANDARD = PCI33_3;
 295 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<4> LOC=V3;
 296 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<4> IOSTANDARD = PCI33_3;
 297 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<5> LOC=T6;
 298 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<5> IOSTANDARD = PCI33_3;
 299 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<1> LOC=T3;
 300 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<1> IOSTANDARD = PCI33_3;
 301 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<2> LOC=R7;
 302 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<2> IOSTANDARD = PCI33_3;
 303 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<3> LOC=T8;
 304 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<3> IOSTANDARD = PCI33_3;
 305 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<4> LOC=T9;
 306 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<4> IOSTANDARD = PCI33_3;
 307 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<5> LOC=R9;
 308 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<5> IOSTANDARD = PCI33_3;
 309 #
 310 ##### Module PCI32_BRIDGE constraints
 311 #
 312 #Net fpga_0_PCI32_BRIDGE_PAR LOC=L8;
 313 #Net fpga_0_PCI32_BRIDGE_PAR IOSTANDARD = PCI33_3;
 314 #Net fpga_0_PCI32_BRIDGE_PAR BYPASS;
 315 #Net fpga_0_PCI32_BRIDGE_PERR_N LOC=M6;
 316 #Net fpga_0_PCI32_BRIDGE_PERR_N IOSTANDARD = PCI33_3;
 317 #Net fpga_0_PCI32_BRIDGE_PERR_N BYPASS;
 318 #Net fpga_0_PCI32_BRIDGE_SERR_N LOC=M7;
 319 #Net fpga_0_PCI32_BRIDGE_SERR_N IOSTANDARD = PCI33_3;
 320 #Net fpga_0_PCI32_BRIDGE_SERR_N BYPASS;
 321 #Net fpga_0_PCI32_BRIDGE_IRDY_N LOC=N5;
 322 #Net fpga_0_PCI32_BRIDGE_IRDY_N IOSTANDARD = PCI33_3;
 323 #Net fpga_0_PCI32_BRIDGE_IRDY_N BYPASS;
 324 #Net fpga_0_PCI32_BRIDGE_FRAME_N LOC=N8;
 325 #Net fpga_0_PCI32_BRIDGE_FRAME_N IOSTANDARD = PCI33_3;
 326 #Net fpga_0_PCI32_BRIDGE_FRAME_N BYPASS;
 327 #Net fpga_0_PCI32_BRIDGE_DEVSEL_N LOC=R3;
 328 #Net fpga_0_PCI32_BRIDGE_DEVSEL_N IOSTANDARD = PCI33_3;
 329 #Net fpga_0_PCI32_BRIDGE_DEVSEL_N BYPASS;
 330 #Net fpga_0_PCI32_BRIDGE_STOP_N LOC=P11;
 331 #Net fpga_0_PCI32_BRIDGE_STOP_N IOSTANDARD = PCI33_3;
 332 #Net fpga_0_PCI32_BRIDGE_STOP_N BYPASS;
 333 #Net fpga_0_PCI32_BRIDGE_TRDY_N LOC=M3;
 334 #Net fpga_0_PCI32_BRIDGE_TRDY_N IOSTANDARD = PCI33_3;
 335 #Net fpga_0_PCI32_BRIDGE_TRDY_N BYPASS;
 336 #Net fpga_0_PCI32_BRIDGE_AD<31> LOC=P7;
 337 #Net fpga_0_PCI32_BRIDGE_AD<31> IOSTANDARD = PCI33_3;
 338 #Net fpga_0_PCI32_BRIDGE_AD<31> BYPASS;
 339 #Net fpga_0_PCI32_BRIDGE_AD<30> LOC=P6;
 340 #Net fpga_0_PCI32_BRIDGE_AD<30> IOSTANDARD = PCI33_3;
 341 #Net fpga_0_PCI32_BRIDGE_AD<30> BYPASS;
 342 #Net fpga_0_PCI32_BRIDGE_AD<29> LOC=K7;
 343 #Net fpga_0_PCI32_BRIDGE_AD<29> IOSTANDARD = PCI33_3;
 344 #Net fpga_0_PCI32_BRIDGE_AD<29> BYPASS;
 345 #Net fpga_0_PCI32_BRIDGE_AD<28> LOC=K6;
 346 #Net fpga_0_PCI32_BRIDGE_AD<28> IOSTANDARD = PCI33_3;
 347 #Net fpga_0_PCI32_BRIDGE_AD<28> BYPASS;
 348 #Net fpga_0_PCI32_BRIDGE_AD<27> LOC=L3;
 349 #Net fpga_0_PCI32_BRIDGE_AD<27> IOSTANDARD = PCI33_3;
 350 #Net fpga_0_PCI32_BRIDGE_AD<27> BYPASS;
 351 #Net fpga_0_PCI32_BRIDGE_AD<26> LOC=K8;
 352 #Net fpga_0_PCI32_BRIDGE_AD<26> IOSTANDARD = PCI33_3;
 353 #Net fpga_0_PCI32_BRIDGE_AD<26> BYPASS;
 354 #Net fpga_0_PCI32_BRIDGE_AD<25> LOC=M10;
 355 #Net fpga_0_PCI32_BRIDGE_AD<25> IOSTANDARD = PCI33_3;
 356 #Net fpga_0_PCI32_BRIDGE_AD<25> BYPASS;
 357 #Net fpga_0_PCI32_BRIDGE_AD<24> LOC=M8;
 358 #Net fpga_0_PCI32_BRIDGE_AD<24> IOSTANDARD = PCI33_3;
 359 #Net fpga_0_PCI32_BRIDGE_AD<24> BYPASS;
 360 #Net fpga_0_PCI32_BRIDGE_AD<23> LOC=J7;
 361 #Net fpga_0_PCI32_BRIDGE_AD<23> IOSTANDARD = PCI33_3;
 362 #Net fpga_0_PCI32_BRIDGE_AD<23> BYPASS;
 363 #Net fpga_0_PCI32_BRIDGE_AD<22> LOC=J6;
 364 #Net fpga_0_PCI32_BRIDGE_AD<22> IOSTANDARD = PCI33_3;
 365 #Net fpga_0_PCI32_BRIDGE_AD<22> BYPASS;
 366 #Net fpga_0_PCI32_BRIDGE_AD<21> LOC=K4;
 367 #Net fpga_0_PCI32_BRIDGE_AD<21> IOSTANDARD = PCI33_3;
 368 #Net fpga_0_PCI32_BRIDGE_AD<21> BYPASS;
 369 #Net fpga_0_PCI32_BRIDGE_AD<20> LOC=K3;
 370 #Net fpga_0_PCI32_BRIDGE_AD<20> IOSTANDARD = PCI33_3;
 371 #Net fpga_0_PCI32_BRIDGE_AD<20> BYPASS;
 372 #Net fpga_0_PCI32_BRIDGE_AD<19> LOC=N10;
 373 #Net fpga_0_PCI32_BRIDGE_AD<19> IOSTANDARD = PCI33_3;
 374 #Net fpga_0_PCI32_BRIDGE_AD<19> BYPASS;
 375 #Net fpga_0_PCI32_BRIDGE_AD<18> LOC=N9;
 376 #Net fpga_0_PCI32_BRIDGE_AD<18> IOSTANDARD = PCI33_3;
 377 #Net fpga_0_PCI32_BRIDGE_AD<18> BYPASS;
 378 #Net fpga_0_PCI32_BRIDGE_AD<17> LOC=H5;
 379 #Net fpga_0_PCI32_BRIDGE_AD<17> IOSTANDARD = PCI33_3;
 380 #Net fpga_0_PCI32_BRIDGE_AD<17> BYPASS;
 381 #Net fpga_0_PCI32_BRIDGE_AD<16> LOC=H4;
 382 #Net fpga_0_PCI32_BRIDGE_AD<16> IOSTANDARD = PCI33_3;
 383 #Net fpga_0_PCI32_BRIDGE_AD<16> BYPASS;
 384 #Net fpga_0_PCI32_BRIDGE_AD<15> LOC=J5;
 385 #Net fpga_0_PCI32_BRIDGE_AD<15> IOSTANDARD = PCI33_3;
 386 #Net fpga_0_PCI32_BRIDGE_AD<15> BYPASS;
 387 #Net fpga_0_PCI32_BRIDGE_AD<14> LOC=J4;
 388 #Net fpga_0_PCI32_BRIDGE_AD<14> IOSTANDARD = PCI33_3;
 389 #Net fpga_0_PCI32_BRIDGE_AD<14> BYPASS;
 390 #Net fpga_0_PCI32_BRIDGE_AD<13> LOC=L10;
 391 #Net fpga_0_PCI32_BRIDGE_AD<13> IOSTANDARD = PCI33_3;
 392 #Net fpga_0_PCI32_BRIDGE_AD<13> BYPASS;
 393 #Net fpga_0_PCI32_BRIDGE_AD<12> LOC=L9;
 394 #Net fpga_0_PCI32_BRIDGE_AD<12> IOSTANDARD = PCI33_3;
 395 #Net fpga_0_PCI32_BRIDGE_AD<12> BYPASS;
 396 #Net fpga_0_PCI32_BRIDGE_AD<11> LOC=G3;
 397 #Net fpga_0_PCI32_BRIDGE_AD<11> IOSTANDARD = PCI33_3;
 398 #Net fpga_0_PCI32_BRIDGE_AD<11> BYPASS;
 399 #Net fpga_0_PCI32_BRIDGE_AD<10> LOC=F5;
 400 #Net fpga_0_PCI32_BRIDGE_AD<10> IOSTANDARD = PCI33_3;
 401 #Net fpga_0_PCI32_BRIDGE_AD<10> BYPASS;
 402 #Net fpga_0_PCI32_BRIDGE_AD<9> LOC=F3;
 403 #Net fpga_0_PCI32_BRIDGE_AD<9> IOSTANDARD = PCI33_3;
 404 #Net fpga_0_PCI32_BRIDGE_AD<9> BYPASS;
 405 #Net fpga_0_PCI32_BRIDGE_AD<8> LOC=G5;
 406 #Net fpga_0_PCI32_BRIDGE_AD<8> IOSTANDARD = PCI33_3;
 407 #Net fpga_0_PCI32_BRIDGE_AD<8> BYPASS;
 408 #Net fpga_0_PCI32_BRIDGE_AD<7> LOC=N4;
 409 #Net fpga_0_PCI32_BRIDGE_AD<7> IOSTANDARD = PCI33_3;
 410 #Net fpga_0_PCI32_BRIDGE_AD<7> BYPASS;
 411 #Net fpga_0_PCI32_BRIDGE_AD<6> LOC=N3;
 412 #Net fpga_0_PCI32_BRIDGE_AD<6> IOSTANDARD = PCI33_3;
 413 #Net fpga_0_PCI32_BRIDGE_AD<6> BYPASS;
 414 #Net fpga_0_PCI32_BRIDGE_AD<5> LOC=E4;
 415 #Net fpga_0_PCI32_BRIDGE_AD<5> IOSTANDARD = PCI33_3;
 416 #Net fpga_0_PCI32_BRIDGE_AD<5> BYPASS;
 417 #Net fpga_0_PCI32_BRIDGE_AD<4> LOC=E3;
 418 #Net fpga_0_PCI32_BRIDGE_AD<4> IOSTANDARD = PCI33_3;
 419 #Net fpga_0_PCI32_BRIDGE_AD<4> BYPASS;
 420 #Net fpga_0_PCI32_BRIDGE_AD<3> LOC=F4;
 421 #Net fpga_0_PCI32_BRIDGE_AD<3> IOSTANDARD = PCI33_3;
 422 #Net fpga_0_PCI32_BRIDGE_AD<3> BYPASS;
 423 #Net fpga_0_PCI32_BRIDGE_AD<2> LOC=H3;
 424 #Net fpga_0_PCI32_BRIDGE_AD<2> IOSTANDARD = PCI33_3;
 425 #Net fpga_0_PCI32_BRIDGE_AD<2> BYPASS;
 426 #Net fpga_0_PCI32_BRIDGE_AD<1> LOC=L5;
 427 #Net fpga_0_PCI32_BRIDGE_AD<1> IOSTANDARD = PCI33_3;
 428 #Net fpga_0_PCI32_BRIDGE_AD<1> BYPASS;
 429 #Net fpga_0_PCI32_BRIDGE_AD<0> LOC=L4;
 430 #Net fpga_0_PCI32_BRIDGE_AD<0> IOSTANDARD = PCI33_3;
 431 #Net fpga_0_PCI32_BRIDGE_AD<0> BYPASS;
 432 #Net fpga_0_PCI32_BRIDGE_CBE<3> LOC=R6;
 433 #Net fpga_0_PCI32_BRIDGE_CBE<3> IOSTANDARD = PCI33_3;
 434 #Net fpga_0_PCI32_BRIDGE_CBE<3> BYPASS;
 435 #Net fpga_0_PCI32_BRIDGE_CBE<2> LOC=R4;
 436 #Net fpga_0_PCI32_BRIDGE_CBE<2> IOSTANDARD = PCI33_3;
 437 #Net fpga_0_PCI32_BRIDGE_CBE<2> BYPASS;
 438 #Net fpga_0_PCI32_BRIDGE_CBE<1> LOC=L6;
 439 #Net fpga_0_PCI32_BRIDGE_CBE<1> IOSTANDARD = PCI33_3;
 440 #Net fpga_0_PCI32_BRIDGE_CBE<1> BYPASS;
 441 #Net fpga_0_PCI32_BRIDGE_CBE<0> LOC=M5;
 442 #Net fpga_0_PCI32_BRIDGE_CBE<0> IOSTANDARD = PCI33_3;
 443 #Net fpga_0_PCI32_BRIDGE_CBE<0> BYPASS;
 444 #
 445 ##### Module SysACE_CompactFlash constraints
 446 #
 447 #Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AF16;
 448 #Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 29000 ps;
 449 #Net fpga_0_SysACE_CompactFlash_clk_enable_n_pin LOC=AD4;
 450 #Net fpga_0_SysACE_CompactFlash_clk_enable_n_pin IOSTANDARD = LVCMOS33;
 451 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=AE6;
 452 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> IOSTANDARD = LVCMOS33;
 453 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=AE4;
 454 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS33;
 455 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AE3;
 456 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS33;
 457 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AF6;
 458 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS33;
 459 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=AF5;
 460 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS33;
 461 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AF4;
 462 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS33;
 463 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=AF3;
 464 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS33;
 465 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AG6;
 466 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS33;
 467 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AG5;
 468 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS33;
 469 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AG3;
 470 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS33;
 471 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AH5;
 472 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS33;
 473 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=AH4;
 474 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS33;
 475 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AH3;
 476 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS33;
 477 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=AJ6;
 478 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS33;
 479 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AJ5;
 480 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS33;
 481 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=AJ4;
 482 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS33;
 483 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AK6;
 484 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS33;
 485 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AK4;
 486 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS33;
 487 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AK3;
 488 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS33;
 489 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AL6;
 490 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS33;
 491 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AL5;
 492 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS33;
 493 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AL4;
 494 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS33;
 495 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AA3;
 496 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS33;
 497 #Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AB6;
 498 #Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS33;
 499 #Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AM5;
 500 #Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS33;
 501 #Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=AB3;
 502 #Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS33;
 503 #Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=AM6;
 504 #Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS33;
 505 #
 506 ##### Module IIC_Bus constraints
 507 #
 508 #Net fpga_0_IIC_Bus_Scl_pin LOC=E7;
 509 #Net fpga_0_IIC_Bus_Scl_pin IOSTANDARD = LVCMOS33;
 510 #Net fpga_0_IIC_Bus_Sda_pin LOC=D7;
 511 #Net fpga_0_IIC_Bus_Sda_pin IOSTANDARD = LVCMOS33;
 512 #
 513 ##### Module ORGate_1 constraints
 514 #
 515 #Net fpga_0_ORGate_1_Res_pin LOC=AE18;
 516 #Net fpga_0_ORGate_1_Res_pin TIG;
 517 #Net fpga_0_ORGate_1_Res_1_pin LOC=AE17;
 518 #Net fpga_0_ORGate_1_Res_1_pin TIG;
 519 #Net fpga_0_ORGate_1_Res_2_pin LOC=R11;
 520 #Net fpga_0_ORGate_1_Res_2_pin IOSTANDARD = PCI33_3;
 521 #
 522 ##### Module TriMode_MAC_GMII constraints
 523 #
 524 #Net fpga_0_TriMode_MAC_GMII_PhyResetN_pin LOC = M12;
 525 #Net fpga_0_TriMode_MAC_GMII_PhyResetN_pin IOSTANDARD=LVCMOS33;
 526 #Net fpga_0_TriMode_MAC_GMII_PhyResetN_pin TIG;
 527 #
 528 ##### Module Hard_Temac_0 constraints
 529 #
 530 #Net fpga_0_Hard_Temac_0_MII_TXD_0<3> LOC = K9;
 531 #Net fpga_0_Hard_Temac_0_MII_TXD_0<3> IOSTANDARD=LVCMOS33;
 532 #Net fpga_0_Hard_Temac_0_MII_TXD_0<3> SLEW=FAST;
 533 #Net fpga_0_Hard_Temac_0_MII_TXD_0<2> LOC = K11;
 534 #Net fpga_0_Hard_Temac_0_MII_TXD_0<2> IOSTANDARD=LVCMOS33;
 535 #Net fpga_0_Hard_Temac_0_MII_TXD_0<2> SLEW=FAST;
 536 #Net fpga_0_Hard_Temac_0_MII_TXD_0<1> LOC = K12;
 537 #Net fpga_0_Hard_Temac_0_MII_TXD_0<1> IOSTANDARD=LVCMOS33;
 538 #Net fpga_0_Hard_Temac_0_MII_TXD_0<1> SLEW=FAST;
 539 #Net fpga_0_Hard_Temac_0_MII_TXD_0<0> LOC = K13;
 540 #Net fpga_0_Hard_Temac_0_MII_TXD_0<0> IOSTANDARD=LVCMOS33;
 541 #Net fpga_0_Hard_Temac_0_MII_TXD_0<0> SLEW=FAST;
 542 #Net fpga_0_Hard_Temac_0_MII_TX_EN_0 LOC = L11;
 543 #Net fpga_0_Hard_Temac_0_MII_TX_EN_0 IOSTANDARD=LVCMOS33;
 544 #Net fpga_0_Hard_Temac_0_MII_TX_EN_0 SLEW=FAST;
 545 #Net fpga_0_Hard_Temac_0_MII_TX_ER_0 LOC = L14;
 546 #Net fpga_0_Hard_Temac_0_MII_TX_ER_0 IOSTANDARD=LVCMOS25;
 547 #Net fpga_0_Hard_Temac_0_MII_RXD_0<3> LOC = J9;
 548 #Net fpga_0_Hard_Temac_0_MII_RXD_0<3> IOSTANDARD=LVCMOS33;
 549 #Net fpga_0_Hard_Temac_0_MII_RXD_0<3> IOBDELAY = NONE;
 550 #Net fpga_0_Hard_Temac_0_MII_RXD_0<2> LOC = J10;
 551 #Net fpga_0_Hard_Temac_0_MII_RXD_0<2> IOSTANDARD=LVCMOS33;
 552 #Net fpga_0_Hard_Temac_0_MII_RXD_0<2> IOBDELAY = NONE;
 553 #Net fpga_0_Hard_Temac_0_MII_RXD_0<1> LOC = J11;
 554 #Net fpga_0_Hard_Temac_0_MII_RXD_0<1> IOSTANDARD=LVCMOS33;
 555 #Net fpga_0_Hard_Temac_0_MII_RXD_0<1> IOBDELAY = NONE;
 556 #Net fpga_0_Hard_Temac_0_MII_RXD_0<0> LOC = J12;
 557 #Net fpga_0_Hard_Temac_0_MII_RXD_0<0> IOSTANDARD=LVCMOS33;
 558 #Net fpga_0_Hard_Temac_0_MII_RXD_0<0> IOBDELAY = NONE;
 559 #Net fpga_0_Hard_Temac_0_MII_RX_DV_0 LOC = H12;
 560 #Net fpga_0_Hard_Temac_0_MII_RX_DV_0 IOSTANDARD=LVCMOS33;
 561 #Net fpga_0_Hard_Temac_0_MII_RX_DV_0 IOBDELAY = NONE;
 562 #Net fpga_0_Hard_Temac_0_MII_RX_ER_0 LOC = H18;
 563 #Net fpga_0_Hard_Temac_0_MII_RX_ER_0 IOSTANDARD=LVCMOS25;
 564 #Net fpga_0_Hard_Temac_0_MII_RX_ER_0 IOBDELAY = NONE;
 565 #Net fpga_0_Hard_Temac_0_MII_TX_CLK_0 LOC=J14;
 566 #Net fpga_0_Hard_Temac_0_MII_TX_CLK_0 MAXSKEW= 2.0 ns;
 567 #Net fpga_0_Hard_Temac_0_MII_TX_CLK_0 IOSTANDARD=LVCMOS25;
 568 #Net fpga_0_Hard_Temac_0_MII_RX_CLK_0 LOC=K19;
 569 #Net fpga_0_Hard_Temac_0_MII_RX_CLK_0 MAXSKEW= 2.0 ns;
 570 #Net fpga_0_Hard_Temac_0_MII_RX_CLK_0 IOSTANDARD=LVCMOS25;
 571 #Net fpga_0_Hard_Temac_0_MDIO_0_pin LOC = L13;
 572 #Net fpga_0_Hard_Temac_0_MDIO_0_pin IOSTANDARD=LVCMOS33;
 573 #Net fpga_0_Hard_Temac_0_MDC_0_pin LOC = M13;
 574 #Net fpga_0_Hard_Temac_0_MDC_0_pin IOSTANDARD=LVCMOS33;
 575 #
 576 #Net fpga_0_DDR_CLK_FB TNM_NET = fpga_0_DDR_CLK_FB;
 577 #TIMESPEC TS_fpga_0_DDR_CLK_FB = PERIOD fpga_0_DDR_CLK_FB 10000 ps;
 578 #
 579 ##### AR 22677
 580 #
 581 #AREA_GROUP "opb2plb" RANGE=SLICE_X20Y104:SLICE_X33Y139, SLICE_X34Y96:SLICE_X51Y139;
 582 #INST "opb2plb" AREA_GROUP = "opb2plb";
 583 #AREA_GROUP "pblock_spi_eeprom" RANGE=SLICE_X54Y92:SLICE_X67Y111;
 584 #INST "spi_eeprom" AREA_GROUP = "pblock_spi_eeprom";
 585 #AREA_GROUP "pblock_plb2opb" RANGE= SLICE_X34Y140:SLICE_X51Y191;
 586 #INST "plb2opb" AREA_GROUP = "pblock_plb2opb";
 587 ## These two items here no longer exist in 8.2i
 588 ## INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/CARRY_MUX*" AREA_GROUP = "pblock_plb2opb";
 589 ## INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/CYMUX_FIRST*" AREA_GROUP = "pblock_plb2opb";
 590 #
 591 ## The path "I_PLB_ADDRPATH/I_PLBADDR_MUX" doesn't exist either; using *? to replace it
 592 ## INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/_n*" AREA_GROUP = "pblock_plb2opb";
 593 #INST "plb/plb/*?/_n*" AREA_GROUP = "pblock_plb2opb";
 594 #INST "plb/plb/I_PLB_ARBITER_LOGIC/I_MUXEDSIGNALS/*" AREA_GROUP = "pblock_plb2opb";
 595 #
 596 ###################################
 597 #### Virtex-4 FX60-FF1152 MGT Null Tile LOCs ###
 598 ###################################
 599 ##MGT113A
 600 #INST MGT113AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y7;
 601 #NET "MGT113AB_TXN<1>" LOC = "A3"; #TXN
 602 #NET "MGT113AB_TXP<1>" LOC = "A4"; #TXP
 603 #NET "MGT113AB_RXN<1>" LOC = "A6"; #RXN
 604 #NET "MGT113AB_RXP<1>" LOC = "A7"; #RXP
 605 ##MGT113B
 606 #INST MGT113AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y6;
 607 #NET "MGT113AB_TXN<0>" LOC = "D1"; #TXN
 608 #NET "MGT113AB_TXP<0>" LOC = "C1"; #TXP
 609 #NET "MGT113AB_RXN<0>" LOC = "G1"; #RXN
 610 #NET "MGT113AB_RXP<0>" LOC = "F1"; #RXP
 611 ##MGT112A
 612 #INST MGT112AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y5;
 613 #NET "MGT112AB_TXN<1>" LOC = "T1"; #TXN
 614 #NET "MGT112AB_TXP<1>" LOC = "R1"; #TXP
 615 #NET "MGT112AB_RXN<1>" LOC = "N1"; #RXN
 616 #NET "MGT112AB_RXP<1>" LOC = "M1"; #RXP
 617 ##MGT112B
 618 #INST MGT112AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y4;
 619 #NET "MGT112AB_TXN<0>" LOC = "V1"; #TXN
 620 #NET "MGT112AB_TXP<0>" LOC = "U1"; #TXP
 621 #NET "MGT112AB_RXN<0>" LOC = "AA1"; #RXN
 622 #NET "MGT112AB_RXP<0>" LOC = "Y1"; #RXP
 623 ##MGT110A
 624 #INST MGT110AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y3;
 625 #NET "MGT110AB_TXN<1>" LOC = "AG1"; #TXN
 626 #NET "MGT110AB_TXP<1>" LOC = "AF1"; #TXP
 627 #NET "MGT110AB_RXN<1>" LOC = "AD1"; #RXN
 628 #NET "MGT110AB_RXP<1>" LOC = "AC1"; #RXP
 629 ##MGT110B
 630 #INST MGT110AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y2;
 631 #NET "MGT110AB_TXN<0>" LOC = "AJ1"; #TXN
 632 #NET "MGT110AB_TXP<0>" LOC = "AH1"; #TXP
 633 #NET "MGT110AB_RXN<0>" LOC = "AM1"; #RXN
 634 #NET "MGT110AB_RXP<0>" LOC = "AL1"; #RXP
 635 ##MGT109A
 636 #INST MGT109AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y1;
 637 #NET "MGT109AB_TXN<1>" LOC = "AP10"; #TXN
 638 #NET "MGT109AB_TXP<1>" LOC = "AP9"; #TXP
 639 #NET "MGT109AB_RXN<1>" LOC = "AP7"; #RXN
 640 #NET "MGT109AB_RXP<1>" LOC = "AP6"; #RXP
 641 ##MGT109B
 642 #INST MGT109AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y0;
 643 #NET "MGT109AB_TXN<0>" LOC = "AP12"; #TXN
 644 #NET "MGT109AB_TXP<0>" LOC = "AP11"; #TXP
 645 #NET "MGT109AB_RXN<0>" LOC = "AP15"; #RXN
 646 #NET "MGT109AB_RXP<0>" LOC = "AP14"; #RXP
 647 ##MGT102A
 648 #INST MGT102AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y7;
 649 #NET "MGT102AB_TXN<1>" LOC = "E34"; #TXN
 650 #NET "MGT102AB_TXP<1>" LOC = "D34"; #TXP
 651 #NET "MGT102AB_RXN<1>" LOC = "A32"; #RXN
 652 #NET "MGT102AB_RXP<1>" LOC = "A31"; #RXP
 653 #
 654 ##MGT102B
 655 #INST MGT102AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y6;
 656 #NET "MGT102AB_TXN<0>" LOC = "G34"; #TXN
 657 #NET "MGT102AB_TXP<0>" LOC = "F34"; #TXP
 658 #NET "MGT102AB_RXN<0>" LOC = "K34"; #RXN
 659 #NET "MGT102AB_RXP<0>" LOC = "J34"; #RXP
 660 ##MGT103A
 661 #INST MGT103AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y5;
 662 #NET "MGT103AB_TXN<1>" LOC = "W34"; #TXN
 663 #NET "MGT103AB_TXP<1>" LOC = "V34"; #TXP
 664 #NET "MGT103AB_RXN<1>" LOC = "T34"; #RXN
 665 #NET "MGT103AB_RXP<1>" LOC = "R34"; #RXP
 666 ##MGT103B
 667 #INST MGT103AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y4;
 668 #NET "MGT103AB_TXN<0>" LOC = "AA34"; #TXN
 669 #NET "MGT103AB_TXP<0>" LOC = "Y34"; #TXP
 670 #NET "MGT103AB_RXN<0>" LOC = "AD34"; #RXN
 671 #NET "MGT103AB_RXP<0>" LOC = "AC34"; #RXP
 672 ##MGT105A
 673 #INST MGT105AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y3;
 674 #NET "MGT105AB_TXN<1>" LOC = "AK34"; #TXN
 675 #NET "MGT105AB_TXP<1>" LOC = "AJ34"; #TXP
 676 #NET "MGT105AB_RXN<1>" LOC = "AG34"; #RXN
 677 #NET "MGT105AB_RXP<1>" LOC = "AF34"; #RXP
 678 ##MGT105B
 679 #INST MGT105AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y2;
 680 #NET "MGT105AB_TXN<0>" LOC = "AM34"; #TXN
 681 #NET "MGT105AB_TXP<0>" LOC = "AL34"; #TXP
 682 #NET "MGT105AB_RXN<0>" LOC = "AP31"; #RXN
 683 #NET "MGT105AB_RXP<0>" LOC = "AP32"; #RXP
 684 ##MGT106A
 685 #INST MGT106AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y1;
 686 #NET "MGT106AB_TXN<1>" LOC = "AP22"; #TXN
 687 #NET "MGT106AB_TXP<1>" LOC = "AP23"; #TXP
 688 #NET "MGT106AB_RXN<1>" LOC = "AP25"; #RXN
 689 #NET "MGT106AB_RXP<1>" LOC = "AP26"; #RXP
 690 ##MGT106B
 691 #INST MGT106AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y0;
 692 #NET "MGT106AB_TXN<0>" LOC = "AP20"; #TXN
 693 #NET "MGT106AB_TXP<0>" LOC = "AP21"; #TXP
 694 #NET "MGT106AB_RXN<0>" LOC = "AP17"; #RXN
 695 #NET "MGT106AB_RXP<0>" LOC = "AP18"; #RXP
 696 #