src/edu/berkeley/fleet/fpga/main.v

   1
   2 module main
   3  (sys_clk_pin,   /* I think this is 100Mhz */
   4   sys_rst_pin,
   5   fpga_0_RS232_Uart_1_ctsN_pin,
   6   fpga_0_RS232_Uart_1_rtsN_pin,
   7   fpga_0_RS232_Uart_1_sin_pin,
   8   fpga_0_RS232_Uart_1_sout_pin
   9  );
  10
  11   input  sys_clk_pin;
  12   input  sys_rst_pin;
  13   input  fpga_0_RS232_Uart_1_ctsN_pin;
  14   output fpga_0_RS232_Uart_1_rtsN_pin;
  15   input  fpga_0_RS232_Uart_1_sin_pin;
  16   output fpga_0_RS232_Uart_1_sout_pin;
  17
  18   wire clk;
  19   assign clk = sys_clk_pin;
  20   wire break_o;
  21   wire break;
  22   reg break_last;
  23   reg send_k;                initial send_k = 0;
  24   wire rst;
  25   assign rst = sys_rst_pin;
  26
  27   wire       data_to_host_full;
  28   wire       data_to_host_write_enable;
  29   wire [7:0] data_to_host;
  30
  31   wire       data_to_fleet_empty;
  32   wire       data_to_fleet_read_enable;
  33   wire [7:0] data_to_fleet;
  34
  35   reg we;
  36   reg re;
  37   reg [7:0] data_to_host_r;
  38   assign data_to_host = data_to_host_r;
  39
  40   wire ser_rst;
  41   reg ser_rst_r;
  42   initial ser_rst_r = 0;
  43   assign ser_rst = (rst & ser_rst_r);
  44
  45   wire sio_ce;
  46   wire sio_ce_x4;
  47   //sasc_brg sasc_brg(clk, ser_rst, 10, 217, sio_ce, sio_ce_x4);
  48   sasc_brg sasc_brg(clk, ser_rst, 8, 65, sio_ce, sio_ce_x4);
  49   sasc_top sasc_top(clk, ser_rst,
  50                     fpga_0_RS232_Uart_1_sin_pin,
  51                     fpga_0_RS232_Uart_1_sout_pin,
  52                     fpga_0_RS232_Uart_1_ctsN_pin,
  53                     fpga_0_RS232_Uart_1_rtsN_pin,
  54                     sio_ce,
  55                     sio_ce_x4,
  56                     data_to_host,
  57                     data_to_fleet,
  58                     data_to_fleet_read_enable,
  59                     data_to_host_write_enable,
  60                     data_to_host_full,
  61                     data_to_fleet_empty,
  62                     break_o,
  63                     break);
  64
  65    // break and break_o are _active high_
  66    always @(posedge clk) break_last <= break_o;
  67    assign break      =  break_o && !break_last;
  68    assign break_done = !break_o &&  break_last;
  69
  70    reg data_to_host_write_enable_reg;
  71    reg data_to_fleet_read_enable_reg;
  72
  73    reg root_out_a_reg;
  74    reg root_in_r_reg;
  75    reg [7:0] root_in_d_reg;
  76    wire root_in_a;
  77    wire root_in_r;
  78    wire root_out_a;
  79    wire root_out_r;
  80    wire [7:0] root_in_d;
  81    wire [7:0] root_out_d;
  82
  83    /*
  84     * There is some very weird timing thing going on here; we need to
  85     * hold reset low for more than one clock in order for it to propagate
  86     * all the way to the docks.
  87     */
  88    root my_root(clk, rst && !break_o,
  89                 root_in_r,  root_in_a,  root_in_d,
  90                 root_out_r, root_out_a, root_out_d);
  91 /*
  92    fifo4 my_root(clk, rst,
  93                 root_in_r,  root_in_a,  root_in_d,
  94                 root_out_r, root_out_a, data_to_host);
  95 */
  96    assign root_out_a                = root_out_a_reg;
  97    assign root_in_r                 = root_in_r_reg;
  98    assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;
  99    assign data_to_host_write_enable = data_to_host_write_enable_reg;
 100    assign root_in_d                 = root_in_d_reg;
 101
 102    // fpga -> host
 103    always @(posedge clk)
 104    begin
 105      if (break) begin
 106        root_out_a_reg = 0;
 107        data_to_host_write_enable_reg <= 0;
 108
 109      end else if (break_done) begin
 110        data_to_host_write_enable_reg <= 1;
 111        data_to_host_r <= 111;
 112        send_k <= 1;
 113      end else if (send_k) begin
 114        data_to_host_write_enable_reg <= 1;
 115        data_to_host_r <= 107;
 116        send_k <= 0;
 117
 118
 119      end else if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
 120        data_to_host_write_enable_reg <= 1;
 121        data_to_host_r <= root_out_d;
 122        root_out_a_reg = 1;
 123      end else if (root_out_a_reg && !root_out_r) begin
 124        data_to_host_write_enable_reg <= 0;
 125        root_out_a_reg = 0;
 126      end else begin
 127        data_to_host_write_enable_reg <= 0;
 128      end
 129    end
 130
 131    // host -> fpga
 132    always @(posedge clk)
 133    begin
 134      ser_rst_r <= 1;
 135      if (break) begin
 136        root_in_r_reg <= 0;
 137        root_in_d_reg <= 0;
 138        data_to_fleet_read_enable_reg <= 0;
 139      end else
 140
 141      if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
 142         root_in_r_reg <= 1;
 143         root_in_d_reg <= data_to_fleet;
 144         data_to_fleet_read_enable_reg <= 1;
 145      end else begin
 146        data_to_fleet_read_enable_reg <= 0;
 147         if (root_in_a) begin
 148           root_in_r_reg <= 0;
 149         end
 150      end
 151    end
 152
 153    initial
 154    begin
 155      root_in_r_reg = 0;
 156      root_in_d_reg = 0;
 157      root_out_a_reg = 0;
 158      data_to_fleet_read_enable_reg = 0;
 159      data_to_host_write_enable_reg = 0;
 160    end
 161 endmodule
 162
 163