src/edu/berkeley/fleet/fpga/main.v

   1
   2 module main
   3  (sys_clk_pin,   /* 100Mhz */
   4   sys_rst_pin,
   5   fpga_0_RS232_Uart_1_ctsN_pin,
   6   fpga_0_RS232_Uart_1_rtsN_pin,
   7   fpga_0_RS232_Uart_1_sin_pin,
   8   fpga_0_RS232_Uart_1_sout_pin,
   9
  10   ddr1_Clk_pin,
  11   ddr1_Clk_n_pin,
  12   ddr1_Addr_pin,
  13   ddr1_BankAddr_pin,
  14   ddr1_CAS_n_pin,
  15   ddr1_CE_pin,
  16   ddr1_CS_n_pin,
  17   ddr1_RAS_n_pin,
  18   ddr1_WE_n_pin,
  19   ddr1_DM_pin,
  20   ddr1_DQS,
  21   ddr1_DQ,
  22
  23   ddr2_ODT_pin,
  24   ddr2_Clk_pin,
  25   ddr2_Clk_n_pin,
  26   ddr2_Addr_pin,
  27   ddr2_BankAddr_pin,
  28   ddr2_CAS_n_pin,
  29   ddr2_CE_pin,
  30   ddr2_CS_n_pin,
  31   ddr2_RAS_n_pin,
  32   ddr2_WE_n_pin,
  33   ddr2_DM_pin,
  34   ddr2_DQS,
  35   ddr2_DQS_n,
  36   ddr2_DQ,
  37
  38   vga_psave,
  39   vga_hsync,
  40   vga_vsync,
  41   vga_sync,
  42   vga_blank,
  43   vga_r,
  44   vga_g,
  45   vga_b,
  46   vga_clkout,
  47
  48   fpga_0_LEDs_8Bit_GPIO_IO_pin
  49  );
  50
  51   input  sys_clk_pin;
  52   input  sys_rst_pin;
  53   input  fpga_0_RS232_Uart_1_ctsN_pin;
  54   output fpga_0_RS232_Uart_1_rtsN_pin;
  55   input  fpga_0_RS232_Uart_1_sin_pin;
  56   output fpga_0_RS232_Uart_1_sout_pin;
  57
  58   output        ddr1_Clk_pin;
  59   output        ddr1_Clk_n_pin;
  60   output [12:0] ddr1_Addr_pin;
  61   output [1:0]  ddr1_BankAddr_pin;
  62   output        ddr1_CAS_n_pin;
  63   output        ddr1_CE_pin;
  64   output        ddr1_CS_n_pin;
  65   output        ddr1_RAS_n_pin;
  66   output        ddr1_WE_n_pin;
  67   output [3:0]  ddr1_DM_pin;
  68   inout  [3:0]  ddr1_DQS;
  69   inout  [31:0] ddr1_DQ;
  70
  71   output        ddr2_ODT_pin;
  72   output        ddr2_Clk_pin;
  73   output        ddr2_Clk_n_pin;
  74   output [12:0] ddr2_Addr_pin;
  75   output [1:0]  ddr2_BankAddr_pin;
  76   output        ddr2_CAS_n_pin;
  77   output        ddr2_CE_pin;
  78   output        ddr2_CS_n_pin;
  79   output        ddr2_RAS_n_pin;
  80   output        ddr2_WE_n_pin;
  81   output [7:0]  ddr2_DM_pin;
  82   inout  [7:0]  ddr2_DQS;
  83   inout  [7:0]  ddr2_DQS_n;
  84   inout  [63:0] ddr2_DQ;
  85
  86   wire  [31:0]  dram_addr;
  87   wire          dram_addr_r;
  88   wire          dram_addr_a;
  89   wire          dram_isread;
  90   wire  [63:0]  dram_write_data;
  91   wire          dram_write_data_push;
  92   wire          dram_write_data_full;
  93   wire   [63:0] dram_read_data;
  94   wire          dram_read_data_pop;
  95   wire          dram_read_data_empty;
  96   wire   [1:0]  dram_read_data_latency;
  97
  98   wire  [31:0]  ddr2_addr;
  99   wire          ddr2_addr_r;
 100   wire          ddr2_addr_a;
 101   wire          ddr2_isread;
 102   wire  [63:0]  ddr2_write_data;
 103   wire          ddr2_write_data_push;
 104   wire          ddr2_write_data_full;
 105   wire   [63:0] ddr2_read_data;
 106   wire          ddr2_read_data_pop;
 107   wire          ddr2_read_data_empty;
 108   wire   [1:0]  ddr2_read_data_latency;
 109
 110   output vga_psave;
 111   output vga_hsync;
 112   output vga_vsync;
 113   output vga_sync;
 114   output vga_blank;
 115   output [7:0] vga_r;
 116   output [7:0] vga_g;
 117   output [7:0] vga_b;
 118   output vga_clkout;
 119
 120   wire clk;
 121   wire clk_fb;
 122   wire clk50mhz;
 123   wire clk_unbuffered;
 124
 125   wire vga_clk;
 126   wire vga_clk_fb;
 127   wire vga_clk_unbuffered;
 128
 129   output [7:0] fpga_0_LEDs_8Bit_GPIO_IO_pin;
 130   wire [7:0] leds;
 131   assign fpga_0_LEDs_8Bit_GPIO_IO_pin = ~leds;
 132
 133   assign leds[5:0] = dram_read_data[5:0];
 134   assign leds[6] = dram_addr_r;
 135   assign leds[7] = dram_addr_a;
 136
 137   BUFG GBUF_FOR_MUX_CLOCK (.I(clk_unbuffered), .O(clk));
 138
 139   DCM
 140    #(
 141       .CLKFX_MULTIPLY(4),
 142       .CLKFX_DIVIDE(8),
 143       .CLKIN_PERIOD("10 ns")
 144     ) mydcm(
 145       .CLKIN (sys_clk_pin),
 146       .CLKFB(clk_fb),
 147       .CLKFX (clk_unbuffered),
 148       .CLK0  (clk_fb)
 149     );
 150
 151   BUFG GBUF_FOR_VGA_CLOCK (.I(vga_clk_unbuffered), .O(vga_clk));
 152   DCM  // 25Mhz VGA clock
 153    #(
 154       .CLKFX_MULTIPLY(4),
 155       .CLKFX_DIVIDE(16),
 156       .CLKIN_PERIOD("20 ns")
 157     ) vgadcm (
 158       .CLKIN (clk_unbuffered),
 159       .CLKFB(vga_clk_fb),
 160       .CLKFX (vga_clk_unbuffered),
 161       .CLK0  (vga_clk_fb)
 162     );
 163
 164
 165   wire break_o;
 166   wire break;
 167   reg break_last;
 168   reg send_k;                initial send_k = 0;
 169   wire rst;
 170   assign rst = sys_rst_pin;
 171
 172   wire       data_to_host_full;
 173   wire       data_to_host_write_enable;
 174   wire [7:0] data_to_host;
 175
 176   wire       data_to_fleet_empty;
 177   wire       data_to_fleet_read_enable;
 178   wire [7:0] data_to_fleet;
 179
 180   reg we;
 181   reg re;
 182   reg [7:0] data_to_host_r;
 183   assign data_to_host = data_to_host_r;
 184
 185   wire ser_rst;
 186   reg ser_rst_r;
 187   initial ser_rst_r = 0;
 188   assign ser_rst = (rst & ser_rst_r);
 189
 190   wire sio_ce;
 191   wire sio_ce_x4;
 192
 193   sasc_brg sasc_brg(sys_clk_pin, ser_rst, 8, 65, sio_ce, sio_ce_x4);
 194   sasc_top sasc_top(clk, ser_rst,
 195                     fpga_0_RS232_Uart_1_sin_pin,
 196                     fpga_0_RS232_Uart_1_sout_pin,
 197                     fpga_0_RS232_Uart_1_ctsN_pin,
 198                     fpga_0_RS232_Uart_1_rtsN_pin,
 199                     sio_ce,
 200                     sio_ce_x4,
 201                     data_to_host,
 202                     data_to_fleet,
 203                     data_to_fleet_read_enable,
 204                     data_to_host_write_enable,
 205                     data_to_host_full,
 206                     data_to_fleet_empty,
 207                     break_o,
 208                     break);
 209
 210    // break and break_o are _active high_
 211    always @(posedge clk) break_last <= break_o;
 212    assign break      =  break_o && !break_last;
 213    assign break_done = !break_o &&  break_last;
 214
 215    reg data_to_host_write_enable_reg;
 216    reg data_to_fleet_read_enable_reg;
 217
 218    reg root_out_a_reg;
 219    reg root_in_r_reg;
 220    reg [7:0] root_in_d_reg;
 221    wire root_in_a;
 222    wire root_in_r;
 223    wire root_out_a;
 224    wire root_out_r;
 225    wire [7:0] root_in_d;
 226    wire [7:0] root_out_d;
 227
 228    /*
 229     * There is some very weird timing thing going on here; we need to
 230     * hold reset low for more than one clock in order for it to propagate
 231     * all the way to the docks.
 232     */
 233    root my_root(clk, rst && !break_o,
 234                 root_in_r,  root_in_a,  root_in_d,
 235                 root_out_r, root_out_a, root_out_d,
 236                 dram_addr,
 237                 dram_addr_r,
 238                 dram_addr_a,
 239                 dram_isread,
 240                 dram_write_data,
 241                 dram_write_data_push,
 242                 dram_write_data_full,
 243                 dram_read_data,
 244                 dram_read_data_pop,
 245                 dram_read_data_empty,
 246                 dram_read_data_latency,
 247                 vga_clk,
 248                 vga_psave,
 249                 vga_hsync,
 250                 vga_vsync,
 251                 vga_sync,
 252                 vga_blank,
 253                 vga_r,
 254                 vga_g,
 255                 vga_b,
 256                 vga_clkout
 257                );
 258 /*
 259    fifo4 my_root(clk, rst,
 260                 root_in_r,  root_in_a,  root_in_d,
 261                 root_out_r, root_out_a, data_to_host);
 262 */
 263    assign root_out_a                = root_out_a_reg;
 264    assign root_in_r                 = root_in_r_reg;
 265    assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;
 266    assign data_to_host_write_enable = data_to_host_write_enable_reg;
 267    assign root_in_d                 = root_in_d_reg;
 268
 269    // fpga -> host
 270    always @(posedge clk)
 271    begin
 272      if (break) begin
 273        root_out_a_reg = 0;
 274        data_to_host_write_enable_reg <= 0;
 275
 276      end else if (break_done) begin
 277        data_to_host_write_enable_reg <= 1;
 278        data_to_host_r <= 111;
 279        send_k <= 1;
 280      end else if (send_k) begin
 281        data_to_host_write_enable_reg <= 1;
 282        data_to_host_r <= 107;
 283        send_k <= 0;
 284
 285
 286      end else if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
 287        data_to_host_write_enable_reg <= 1;
 288        data_to_host_r <= root_out_d;
 289        root_out_a_reg = 1;
 290      end else if (root_out_a_reg && !root_out_r) begin
 291        data_to_host_write_enable_reg <= 0;
 292        root_out_a_reg = 0;
 293      end else begin
 294        data_to_host_write_enable_reg <= 0;
 295      end
 296    end
 297
 298    // host -> fpga
 299    always @(posedge clk)
 300    begin
 301      ser_rst_r <= 1;
 302      if (break) begin
 303        root_in_r_reg <= 0;
 304        root_in_d_reg <= 0;
 305        data_to_fleet_read_enable_reg <= 0;
 306      end else
 307
 308      if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
 309         root_in_r_reg <= 1;
 310         root_in_d_reg <= data_to_fleet;
 311         data_to_fleet_read_enable_reg <= 1;
 312      end else begin
 313        data_to_fleet_read_enable_reg <= 0;
 314         if (root_in_a) begin
 315           root_in_r_reg <= 0;
 316         end
 317      end
 318    end
 319
 320    initial
 321    begin
 322      root_in_r_reg = 0;
 323      root_in_d_reg = 0;
 324      root_out_a_reg = 0;
 325      data_to_fleet_read_enable_reg = 0;
 326      data_to_host_write_enable_reg = 0;
 327    end
 328
 329    ddr_ctrl
 330    #(
 331         .clk_freq( 50000000 ),
 332         .clk_multiply( 12 ),
 333         .clk_divide( 5 ),
 334         .phase_shift( 0 ),
 335         .wait200_init( 26 )
 336    ) ddr_ctrl (
 337           .ddr_a( ddr1_Addr_pin ),
 338           .ddr_clk( ddr1_Clk_pin ),
 339           .ddr_clk_n( ddr1_Clk_n_pin ),
 340           .ddr_ba( ddr1_BankAddr_pin ),
 341           .ddr_dq( ddr1_DQ ),
 342           .ddr_dm( ddr1_DM_pin ),
 343           .ddr_dqs( ddr1_DQS ),
 344           .ddr_cs_n( ddr1_CS_n_pin ),
 345           .ddr_ras_n( ddr1_RAS_n_pin ),
 346           .ddr_cas_n( ddr1_CAS_n_pin ),
 347           .ddr_we_n( ddr1_WE_n_pin ),
 348           .ddr_cke( ddr1_CE_pin ),
 349
 350           .clk(clk),
 351           .reset(!rst),
 352           .rot(3'b100),
 353
 354           .fml_wr(!dram_isread && dram_addr_r),
 355           .fml_done(dram_addr_a),
 356           .fml_rd( dram_isread && dram_addr_r),
 357           .fml_adr(dram_addr),
 358           .fml_din(dram_write_data),
 359           .fml_dout(dram_read_data),
 360           .fml_msk(16'h0)
 361    );
 362
 363 endmodule
 364