src/edu/berkeley/fleet/slipway/dcache.v

   1 `include "macros.v"
   2 `define BRAM_ADDR_WIDTH 8
   3 `define BRAM_DATA_WIDTH `DATAWIDTH
   4 `define BRAM_NAME dcache_bram
   5 `include "bram.inc"
   6
   7 module dcache (clk,
   8                read_addr_r,    read_addr_a_,   read_addr_d,
   9                read_data_r_,   read_data_a,    read_data_d_,
  10                write_addr_r,   write_addr_a_,  write_addr_d,
  11                write_data_r,   write_data_a_,  write_data_d,
  12                write_done_r_,  write_done_a,   write_done_d_
  13               );
  14
  15   input  clk;
  16   `input(read_addr_r,    read_addr_a,   read_addr_a_,   [(`DATAWIDTH-1):0],  read_addr_d)
  17   `output(read_data_r,   read_data_r_,  read_data_a,    [(`DATAWIDTH-1):0],  read_data_d_)
  18   `defreg(read_data_d_,                                 [(`DATAWIDTH-1):0],  read_data_d)
  19
  20   `include "cache.inc"
  21
  22   reg have_read;    initial have_read = 0;
  23   reg read_pending; initial read_pending = 0;
  24   assign bram_read_address = read_addr_d;
  25
  26   always @(posedge clk) begin
  27     `include "cache_write.inc"
  28
  29     if (read_pending) begin
  30         read_pending <= 0;
  31         have_read    <= 1;
  32         read_data_d  <= bram_read_data;
  33     end else if (have_read) begin
  34       `onwrite(read_data_r, read_data_a)
  35         have_read <= 0;
  36       end
  37     end else begin
  38       `onread(read_addr_r, read_addr_a)
  39         // ======= Careful with the timing here! =====================
  40         // We MUST capture bram_read_data on the very next clock since
  41         // read_addr_d is free to change after the next clock
  42         // ===========================================================
  43         read_pending <= 1;
  44       end
  45     end
  46
  47   end
  48
  49 endmodule